CN112259524A - Manufacturing method of MIM capacitor in copper interconnection process - Google Patents
Manufacturing method of MIM capacitor in copper interconnection process Download PDFInfo
- Publication number
- CN112259524A CN112259524A CN202011189148.6A CN202011189148A CN112259524A CN 112259524 A CN112259524 A CN 112259524A CN 202011189148 A CN202011189148 A CN 202011189148A CN 112259524 A CN112259524 A CN 112259524A
- Authority
- CN
- China
- Prior art keywords
- mim
- layer
- pattern
- forming
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 87
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 87
- 239000010949 copper Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 86
- 239000003990 capacitor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 120
- 239000002184 metal Substances 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 161
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The application discloses a manufacturing method of an MIM capacitor in a copper interconnection process, and relates to the field of semiconductor manufacturing. The method comprises providing a substrate with an x-th copper metal wiring layer; forming an insulating medium layer; simultaneously defining a contraposition mark pattern and an MIM lower polar plate pattern on the surface of the insulating medium layer; etching according to the alignment mark pattern and the MIM lower pole plate pattern; forming an MIM lower pole plate metal layer; performing CMP treatment on the substrate to form an MIM lower polar plate in the insulating dielectric layer; forming a dielectric layer and an MIM upper plate metal layer of the MIM capacitor; defining an MIM upper polar plate pattern; etching the MIM upper electrode plate metal layer and the MIM capacitor dielectric layer to form the MIM capacitor; the problems that multiple exposure and etching are needed during manufacturing of the MIM capacitor in the existing copper interconnection process, and the process risk of the generation cost is high are solved; the effects of reducing sequential exposure etching and reducing production cost and process risk are achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an MIM capacitor in a copper interconnection process.
Background
The MIM capacitor has a structure of metal-insulating medium-metal, is widely applied to integrated circuit chips, and can be used for charge storage, voltage control, radio frequency control and the like. Due to the structural characteristics of the MIM capacitor, the MIM capacitor can be manufactured in a back-end metal interconnection process.
The copper interconnection process is the mainstream back-end metal interconnection process in the current very large scale integrated circuit. Since copper has a high diffusivity, when a MIM capacitor is manufactured, a material such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten needs to be used instead of copper as the upper and lower plates of the MIM. When the filling capacity of the insulating medium is limited, three times of photoetching are usually required to manufacture the MIM capacitor in the copper interconnection process, and the alignment mark, the upper electrode plate of the MIM capacitor and the lower electrode plate of the MIM capacitor are obtained by etching respectively.
Since alignment is required before each photolithography, the more times the photolithography is performed, the more shift that may be caused, resulting in more process risk.
Disclosure of Invention
In order to solve the problems in the related art, the application provides a method for manufacturing an MIM capacitor in a copper interconnection process.
In one aspect, an embodiment of the present application provides a method for manufacturing an MIM capacitor in a copper interconnect process, where the method includes:
providing a substrate, wherein an x copper metal connecting line layer is manufactured on the substrate; x is an integer of 1 or more;
forming an insulating medium layer on the surface of the x copper metal connecting layer;
simultaneously defining a contraposition mark pattern and an MIM lower pole plate pattern on the surface of the insulating medium layer through a photoetching process, wherein a copper metal wire exists below the MIM lower pole plate pattern, and the copper metal wire does not exist below the contraposition mark pattern;
etching according to the alignment mark pattern and the MIM lower pole plate pattern, forming the MIM lower pole plate pattern in the insulating dielectric layer, and forming an alignment mark in the substrate;
forming an MIM lower pole plate metal layer;
performing CMP treatment on the substrate, forming an MIM lower polar plate in the insulating dielectric layer, and reserving a step in the alignment mark region;
sequentially forming a dielectric layer of the MIM capacitor and a MIM upper electrode plate metal layer;
carrying out alignment according to the alignment mark, and defining the MIM upper plate pattern through a photoetching process;
and etching the MIM upper pole plate metal layer and the dielectric layer of the MIM capacitor according to the MIM upper pole plate pattern to form the MIM capacitor.
Optionally, forming an insulating dielectric layer on the surface of the x-th copper metal connecting layer, including:
forming an NDC layer on the surface of the x copper metal connecting layer;
and forming a silicon oxide layer on the surface of the NDC layer.
Optionally, defining the alignment mark pattern and the MIM lower plate pattern on the surface of the insulating dielectric layer by a photolithography process, including:
coating photoresist on the surface of the insulating medium layer;
and simultaneously forming an alignment mark pattern and an MIM lower plate pattern in the photoresist layer by a photoetching process, wherein the alignment mark pattern and the MIM lower plate pattern exist in a mask used by the photoetching process.
Optionally, forming a MIM lower plate metal layer includes:
and depositing titanium, titanium nitride and tungsten in sequence to form the MIM lower pole plate metal layer.
Optionally, forming a MIM lower plate metal layer includes:
and depositing tantalum nitride to form the MIM lower plate metal layer.
Optionally, the dielectric layer of the MIM capacitor is made of silicon nitride.
Optionally, the MIM top plate metal layer is made of titanium nitride or tantalum nitride.
Optionally, the method further includes:
depositing a metal interlayer dielectric material, and performing CMP (chemical mechanical polishing) treatment to form an x +1 th metal interlayer dielectric layer;
and manufacturing a copper metal connecting line and a copper through hole by using a Damascus process to form an x +1 copper metal connecting line layer.
The technical scheme at least comprises the following advantages:
an insulating dielectric layer is formed above the x-th copper metal connecting line layer, the alignment mark pattern and the MIM lower pole plate pattern are defined by using the same mask, the MIM lower pole plate pattern and the alignment mark pattern are formed by etching in the same etching process, the lower pole plate of the MIM capacitor is directly manufactured on the copper metal line by using a diffusion-proof conductive material, and then a dielectric medium and an upper pole plate of the MIM capacitor are formed, so that the problems that the MIM capacitor in the existing copper interconnection process needs to be exposed and etched for multiple times and the generation cost process risk is high are solved; the effects of reducing sequential exposure etching and reducing production cost and process risk are achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating an implementation of a method for fabricating an MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating an implementation of a method for fabricating an MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating an implementation of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating an implementation of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating an implementation of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating an implementation of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating an implementation of a method for fabricating a MIM capacitor in a copper interconnect process according to an embodiment of the present disclosure;
fig. 9 is a schematic implementation diagram of a method for manufacturing a MIM capacitor in a copper interconnect process according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for fabricating an MIM capacitor in a copper interconnect process according to an embodiment of the present application is shown, the method at least includes the following steps:
x is an integer of 1 or more. The value of x is determined according to the actual manufacturing process of the semiconductor device, and is not limited in the embodiments of the present application.
The x-th copper metal connecting layer consists of a metal interlayer medium and a copper metal wire positioned in the metal interlayer medium.
Optionally, the x-th copper metal connecting layer is prepared by adopting a Damascus process.
And 102, forming an insulating medium layer on the surface of the x copper metal connecting layer.
As shown in fig. 2, an insulating dielectric layer 23 is formed on the surface of the x-th copper metal wire layer 20, and the x-th copper metal wire layer 20 is composed of a metal interlayer dielectric 22 and a copper metal wire 21 located in the metal interlayer dielectric 22.
And step 103, simultaneously defining a registration mark pattern and an MIM lower plate pattern on the surface of the insulating medium layer through a photoetching process.
As shown in fig. 3, an alignment mark pattern 24 and a MIM lower plate pattern 25 are formed on the surface of the insulating dielectric layer 23, a copper metal line 21 is present under the MIM lower plate pattern 25, and no copper metal line is present under the alignment mark pattern.
And 104, etching according to the alignment mark pattern and the MIM lower plate pattern, forming the MIM lower plate pattern in the insulating dielectric layer, and forming an alignment mark in the substrate.
Etching the substrate according to the alignment mark pattern and the MIM lower pole plate pattern, wherein in the MIM capacitor region, due to the fact that the copper metal wire 21 exists below the MIM lower pole plate pattern 25, after the insulating medium layer above the copper metal wire 21 is etched, due to the blocking of the lower copper metal wire, the copper metal wire can stay on the surface of the copper metal wire; in the alignment mark area, because no copper metal wire exists below the alignment mark, after the insulating medium layer is etched, the metal interlayer medium layer in the x-th copper metal connecting wire layer below the alignment mark is continuously etched until the alignment mark with the preset depth is formed in the substrate.
And removing the photoresist 26 on the surface of the insulating medium layer after the etching is finished.
As shown in fig. 4, a MIM lower plate pattern 25 is formed in the insulating dielectric layer 23, and alignment marks 31 are formed in the substrate.
And depositing an MIM lower plate metal layer with a preset thickness, wherein the MIM lower plate metal layer is used for manufacturing a lower plate of the MIM capacitor, and the thickness of the MIM metal layer is determined according to actual requirements, which is not limited in the embodiment of the application.
The metal layer of the MIM lower polar plate is made of a diffusion-proof conductive material. Since the lower plate of the MIM capacitor will be in direct contact with the lower copper metal line, the material of the MIM lower plate needs to have a function of preventing copper diffusion.
As shown in fig. 5, a MIM lower plate metal layer 27 covers the substrate, and there is a step in the MIM lower plate region and the alignment mark region.
And 106, performing CMP treatment on the substrate to form an MIM lower polar plate in the insulating dielectric layer, wherein a step is reserved in the alignment mark region.
The substrate is subjected to CMP processing to polish the MIM lower plate region, form MIM lower plate 32 in insulating dielectric layer 23, and leave a step to align mark region 31, as shown in fig. 6.
And 107, sequentially forming a dielectric layer of the MIM capacitor and an MIM upper plate metal layer.
As shown in fig. 7, a dielectric layer 28 of the MIM capacitor and a MIM top plate metal layer 29 are formed on the substrate.
And 108, carrying out alignment according to the alignment mark, and defining the MIM upper plate pattern through a photoetching process.
And coating photoresist on the surface of the substrate, carrying out alignment by using a mask plate with an MIM upper polar plate pattern structure and an alignment mark on the substrate, and then exposing, and developing to form an MIM upper polar plate pattern on the surface of the substrate.
And step 109, etching the MIM upper electrode plate metal layer and the MIM capacitor dielectric layer according to the MIM upper electrode plate pattern to form the MIM capacitor.
As shown in fig. 8, the MIM top plate metal layer is etched to form the top plate 33 of the MIM capacitor; the dielectric layer 28 of the MIM capacitor is etched to form the MIM capacitor with the upper electrode plate 33 and the lower electrode plate 32 of the MIM capacitor.
In summary, according to the manufacturing method of the MIM capacitor in the copper interconnection process provided by the embodiment of the present application, the insulating dielectric layer is formed above the x-th copper metal interconnection layer, the alignment mark pattern and the MIM lower plate pattern are defined by using the same mask, the MIM lower plate pattern and the alignment mark pattern are formed by etching in the same etching process, the lower plate of the MIM capacitor is directly manufactured on the copper metal line by using the anti-diffusion conductive material, and then the dielectric and the upper plate of the MIM capacitor are formed, so that the problems that the MIM capacitor in the current copper interconnection process needs to be exposed and etched for multiple times, and the generation cost process risk is high are solved; the effects of reducing sequential exposure etching and reducing production cost and process risk are achieved.
Another embodiment of the present application provides a method for manufacturing an MIM capacitor in a copper interconnect process, the method at least including the following steps:
step 201, a substrate is provided, and the x-th copper metal wiring layer is formed on the substrate.
x is an integer of 1 or more.
Optionally, the x-th copper metal connecting layer is prepared by adopting a Damascus process.
In step 202, an NDC layer is formed on the surface of the x-th copper metal wiring layer.
Optionally, NDC (Nitride Doped Silicon Carbide) with a required thickness is deposited on the surface of the x copper metal connecting layer by a CVD process to form an NDC layer.
Step 203, a silicon oxide layer is formed on the surface of the NDC layer.
Optionally, a silicon oxide layer is deposited over the NDC layer by a CVD process to form a silicon oxide layer.
The NDC layer and the silicon oxide layer jointly form an insulating medium layer.
As shown in fig. 2, an NDC layer 231 and a silicon oxide layer 232 are formed on the surface of the x-th copper interconnect layer 20, and the NDC layer 231 and the silicon oxide layer 232 collectively serve as an insulating dielectric layer 23.
Step 204, coating photoresist on the surface of the insulating medium layer.
Optionally, a photoresist is coated on the surface of the silicon oxide layer.
In step 205, an alignment mark pattern and a MIM bottom plate pattern are simultaneously formed in the photoresist layer by a photolithography process.
The alignment mark pattern and the MIM lower plate pattern are simultaneously formed in the photoresist layer 26 after the exposure using the mask, and the alignment mark pattern 24 and the MIM lower plate pattern 25 are simultaneously formed in the photoresist layer 26 after the development, as shown in fig. 3.
The copper metal line 21 is present under the MIM lower plate pattern 25, and the copper metal line is not present under the alignment mark pattern.
And step 206, etching according to the alignment mark pattern and the MIM lower plate pattern, forming the MIM lower plate pattern in the insulating dielectric layer, and forming an alignment mark in the substrate.
And etching the substrate according to the alignment mark pattern and the MIM lower plate pattern. In the MIM capacitor region, since the silicon oxide layer 232, the NDC layer 231 and the copper metal line 21 are sequentially arranged below the MIM lower plate pattern 25, in the etching process, after the silicon oxide layer 232 and the NDC layer 231 below the MIM lower plate pattern 25 are etched, the silicon oxide layer 232 and the NDC layer 231 stay on the surface of the copper metal line due to the blocking of the lower copper metal line; in the alignment mark area, a silicon oxide layer 232, an NDC layer 231 and an inter-metal dielectric layer 22 are sequentially arranged below the alignment mark, and in the etching process, after the silicon oxide layer 232 and the NDC layer 231 below the alignment mark are etched, the inter-metal dielectric layer 22 below the alignment mark is continuously etched until the alignment mark with the preset depth is formed in the substrate.
And removing the photoresist on the surface of the silicon oxide layer after the etching is finished.
As shown in fig. 4, a MIM lower plate pattern is formed in the insulating dielectric layer 23, and an alignment mark 31 is formed in the substrate.
Step 207, forming a MIM bottom plate metal layer.
And depositing an MIM lower plate metal layer with a preset thickness, wherein the MIM lower plate metal layer is used for manufacturing a lower plate of the MIM capacitor, and the thickness of the MIM metal layer is determined according to actual requirements, which is not limited in the embodiment of the application.
The metal layer of the MIM lower polar plate is made of a diffusion-proof conductive material. Since the lower plate of the MIM capacitor will be in direct contact with the lower copper metal line, the material of the MIM lower plate needs to have a function of preventing copper diffusion.
In one example, titanium (Ti), titanium nitride (TiN), tungsten (W) are sequentially deposited to form a MIM bottom plate metal layer; the deposition thicknesses of titanium, titanium nitride and tungsten are determined according to actual conditions.
In another example, tantalum nitride (TaN) is deposited by a PVD process to form a MIM lower plate metal layer.
As shown in fig. 5, a MIM lower plate metal layer 27 covers the substrate, and there is a step in the MIM lower plate region and the alignment mark region.
And step 208, performing CMP treatment on the substrate to form an MIM lower polar plate in the insulating dielectric layer, wherein a step is reserved in the alignment mark region.
The substrate is subjected to CMP processing to polish the MIM lower plate region, form MIM lower plate 32 in insulating dielectric layer 23, and leave a step to align mark region 31, as shown in fig. 6. And the step of the alignment mark area is used for subsequent exposure alignment.
And step 209, sequentially forming a dielectric layer of the MIM capacitor and an MIM upper plate metal layer.
In one example, the dielectric layer of the MIM capacitor is silicon nitride.
In one example, the material of the MIM top plate metal layer is titanium nitride; in another example, the material of the IM top plate metal layer is tantalum nitride.
As shown in fig. 7, a dielectric layer 28 of the MIM capacitor and a MIM top plate metal layer 29 are formed on the substrate.
And step 210, carrying out alignment according to the alignment mark, and defining the MIM upper plate pattern through a photoetching process.
Coating photoresist on the surface of the substrate, aligning the mask plate with the MIM upper polar plate pattern structure with the alignment mark on the substrate for exposure, and developing to form the MIM upper polar plate pattern on the surface of the substrate.
And step 211, etching the MIM upper electrode plate metal layer and the MIM capacitor dielectric layer according to the MIM upper electrode plate pattern to form the MIM capacitor.
And etching the MIM upper pole plate metal layer and the MIM capacitor dielectric layer in sequence.
As shown in fig. 8, the MIM top plate metal layer is etched to form the top plate 33 of the MIM capacitor; the dielectric layer 28 of the MIM capacitor is etched to form the MIM capacitor with the upper electrode plate 33 and the lower electrode plate 32 of the MIM capacitor.
Step 212, depositing inter-metal dielectric material and performing CMP to form the (x + 1) th inter-metal dielectric layer.
And depositing the metal interlayer dielectric material with the required thickness on the surface of the substrate, completely covering the MIM capacitor and the alignment mark by the deposited metal interlayer dielectric material, and polishing the surface of the substrate by CMP.
Optionally, the inter-metal layer dielectric material is HARP (High Aspect Ratio Process) and HDP (High Density Plasma oxide).
Step 213, forming a copper metal connecting line and a copper through hole by using a damascene process to form an x +1 copper metal connecting line layer.
As shown in fig. 9, the copper via 35 in the x +1 th inter-metal dielectric layer is connected to the copper metal line 21 in the x-th copper metal line layer 20 through the copper metal line 36, so as to complete the inter-metal interconnection.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method for manufacturing an MIM capacitor in a copper interconnection process is characterized by comprising the following steps:
providing a substrate, wherein an x copper metal connecting line layer is manufactured on the substrate; x is an integer of 1 or more;
forming an insulating medium layer on the surface of the x copper metal connecting layer;
simultaneously defining a contraposition marking pattern and an MIM lower polar plate pattern on the surface of the insulating medium layer through a photoetching process, wherein a copper metal wire exists below the MIM lower polar plate pattern, and the copper metal wire does not exist below the contraposition marking pattern;
etching according to the alignment mark pattern and the MIM lower pole plate pattern, forming the MIM lower pole plate pattern in the insulating dielectric layer, and forming an alignment mark in the substrate;
forming an MIM lower pole plate metal layer;
performing CMP (chemical mechanical polishing) treatment on the substrate, forming an MIM (metal-insulator-metal) lower polar plate in the insulating dielectric layer, and reserving a step in the alignment mark region;
sequentially forming a dielectric layer of the MIM capacitor and an MIM upper electrode plate metal layer;
carrying out alignment according to the alignment mark, and defining the MIM upper polar plate pattern through a photoetching process;
and etching the MIM upper electrode plate metal layer and the dielectric layer of the MIM capacitor according to the MIM upper electrode plate pattern to form the MIM capacitor.
2. The method of claim 1, wherein forming an insulating dielectric layer on the surface of the x-th copper metal line layer comprises:
forming an NDC layer on the surface of the x copper metal connecting layer;
and forming a silicon oxide layer on the surface of the NDC layer.
3. The method of claim 1, wherein the simultaneously defining the alignment mark pattern and the MIM bottom plate pattern on the surface of the insulating dielectric layer by the photolithography process comprises:
coating photoresist on the surface of the insulating medium layer;
and simultaneously forming an alignment mark pattern and an MIM lower plate pattern in the photoresist layer by a photoetching process, wherein the alignment mark pattern and the MIM lower plate pattern exist in a mask used by the photoetching process.
4. The method of claim 1, wherein forming the MIM bottom plate metal layer comprises:
and depositing titanium, titanium nitride and tungsten in sequence to form the MIM lower pole plate metal layer.
5. The method of claim 1, wherein forming the MIM bottom plate metal layer comprises:
and depositing tantalum nitride to form the MIM lower plate metal layer.
6. The method of claim 1, wherein the dielectric layer of the MIM capacitor is comprised of silicon nitride.
7. The method of claim 1, wherein the MIM top plate metal layer comprises titanium nitride or tantalum nitride.
8. The method of any of claims 1 to 7, further comprising:
depositing a metal interlayer dielectric material, and performing CMP (chemical mechanical polishing) treatment to form an x +1 th metal interlayer dielectric layer;
and manufacturing a copper metal connecting line and a copper through hole by using a Damascus process to form an x +1 copper metal connecting line layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011189148.6A CN112259524A (en) | 2020-10-30 | 2020-10-30 | Manufacturing method of MIM capacitor in copper interconnection process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011189148.6A CN112259524A (en) | 2020-10-30 | 2020-10-30 | Manufacturing method of MIM capacitor in copper interconnection process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112259524A true CN112259524A (en) | 2021-01-22 |
Family
ID=74267412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011189148.6A Pending CN112259524A (en) | 2020-10-30 | 2020-10-30 | Manufacturing method of MIM capacitor in copper interconnection process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112259524A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400286A (en) * | 2022-01-14 | 2022-04-26 | 成都海威华芯科技有限公司 | High-reliability through hole capacitor and manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941371A (en) * | 2005-09-29 | 2007-04-04 | 富士通株式会社 | Semiconductor device |
| CN111627812A (en) * | 2020-06-28 | 2020-09-04 | 华虹半导体(无锡)有限公司 | Etching method applied to MIM capacitor |
-
2020
- 2020-10-30 CN CN202011189148.6A patent/CN112259524A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941371A (en) * | 2005-09-29 | 2007-04-04 | 富士通株式会社 | Semiconductor device |
| CN111627812A (en) * | 2020-06-28 | 2020-09-04 | 华虹半导体(无锡)有限公司 | Etching method applied to MIM capacitor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400286A (en) * | 2022-01-14 | 2022-04-26 | 成都海威华芯科技有限公司 | High-reliability through hole capacitor and manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100803489B1 (en) | A capacitor for a semiconductor device and method for fabrication therefor | |
| US20080093746A1 (en) | Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface | |
| US20060234464A1 (en) | Method for fabricating an integrated circuit comprising a three-dimensional capacitor | |
| US7796372B2 (en) | Manufacture of 3 dimensional MIM capacitors in the last metal level of an integrated circuit | |
| US7470969B2 (en) | Semiconductor device and fabrication method thereof | |
| CN111696954A (en) | Metal interconnection structure and forming method thereof | |
| US20070158714A1 (en) | One-mask high-k metal-insulator-metal capacitor integration in copper back-end-of-line processing | |
| CN112259524A (en) | Manufacturing method of MIM capacitor in copper interconnection process | |
| CN112259522B (en) | Rear-end structure comprising MIM capacitor and manufacturing method thereof | |
| US6284619B1 (en) | Integration scheme for multilevel metallization structures | |
| US6894364B2 (en) | Capacitor in an interconnect system and method of manufacturing thereof | |
| US20070075348A1 (en) | High density, high Q capacitor on top of a protective layer | |
| KR100778850B1 (en) | Capacitor Of Semiconductor Device And Method For Forming The Same | |
| KR100720519B1 (en) | Semiconductor device and method for fabricating semiconductor device | |
| CN112259523B (en) | Forming method of MIM capacitor and back-end structure | |
| CN112185887B (en) | Manufacturing method of MIM capacitor | |
| CN118099126A (en) | MIM capacitor manufacturing method | |
| US11804406B2 (en) | Top via cut fill process for line extension reduction | |
| KR100870315B1 (en) | Method for manufacturing semiconductor device | |
| US20240170404A1 (en) | Subtractive skip via | |
| KR100667914B1 (en) | MIM capacitor having horizontal structure and fabricating method thereof | |
| CN111128956A (en) | Manufacturing process of copper interconnection MIM capacitor and copper interconnection MIM capacitor structure | |
| CN111128866A (en) | Method for integrating MIM capacitor in aluminum interconnection structure and aluminum interconnection structure | |
| CN116314015A (en) | Method for manufacturing back-end structure of integrated circuit | |
| CN115394708A (en) | Metal interconnection structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210122 |