CN112397386A - Manufacturing method of MIM capacitor - Google Patents

Manufacturing method of MIM capacitor Download PDF

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Publication number
CN112397386A
CN112397386A CN202011289254.1A CN202011289254A CN112397386A CN 112397386 A CN112397386 A CN 112397386A CN 202011289254 A CN202011289254 A CN 202011289254A CN 112397386 A CN112397386 A CN 112397386A
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China
Prior art keywords
metal layer
mim capacitor
layer
etching
forming
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Application number
CN202011289254.1A
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Chinese (zh)
Inventor
马莉娜
孟艳秋
熊磊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Hua Hong Semiconductor Wuxi Co Ltd
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Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp, Hua Hong Semiconductor Wuxi Co Ltd filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202011289254.1A priority Critical patent/CN112397386A/en
Publication of CN112397386A publication Critical patent/CN112397386A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application discloses a manufacturing method of an MIM capacitor, and relates to the field of semiconductor manufacturing. The manufacturing method of the MIM capacitor comprises the steps of forming a first metal layer on the surface of a substrate, wherein the first metal layer is used for forming a lower plate of the MIM capacitor; forming a dielectric layer on the surface of the first metal layer; forming a second metal layer on the surface of the dielectric layer, wherein the second metal layer is used for forming an upper plate of the MIM capacitor; sequentially etching the second metal layer, the dielectric layer and the first metal layer to form the MIM capacitor; wherein, in the etching process of the first metal layer and the second metal layer, the etching gas comprises CH4Chlorine-based gas or fluorine-based gas; the first metal layer and the second metal layer are made of tantalum nitride; the problem that the tantalum-containing polymer generated in the existing etching process for etching tantalum nitride is difficult to remove is solved; the residual of the MIM capacitor made of tantalum nitride in the manufacturing process is avoidedLeaving the effect of tantalum containing polymer.

Description

Manufacturing method of MIM capacitor
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an MIM capacitor.
Background
Capacitors are important components of integrated circuits and are widely used in a variety of chips. The MIM capacitor is structurally composed of a metal layer, an insulating dielectric layer and a metal layer, and can be formed in a back-end metal interconnection process in an integrated mode.
At present, in the manufacturing process of the MIM capacitor, the upper plate and the lower plate may be made of titanium nitride, tantalum nitride, or other materials. However, when tantalum nitride is used to fabricate MIM capacitors, a polymer containing tantalum (Ta) is generated during etching, the polymer containing tantalum (Ta) adheres to the substrate, and the polymer cannot be removed by wet cleaning, which may adversely affect the device performance.
Disclosure of Invention
In order to solve the problems in the related art, the present application provides a method of manufacturing an MIM capacitor.
In one aspect, an embodiment of the present application provides a method for manufacturing an MIM capacitor, where the method includes:
forming a first metal layer on the surface of a substrate, wherein the first metal layer is used for forming a lower plate of the MIM capacitor;
forming a dielectric layer on the surface of the first metal layer;
forming a second metal layer on the surface of the dielectric layer, wherein the second metal layer is used for forming an upper plate of the MIM capacitor;
etching the second metal layer, the dielectric layer and the first metal layer to form an MIM capacitor;
wherein, in the etching process of the first metal layer and the second metal layer, the etching gas comprises chlorine-based gas or fluorine-based gas, CH4(ii) a The first metal layer and the second metal layer are made of tantalum nitride.
Optionally, the etching the second metal layer, the dielectric layer, and the first metal layer to form an MIM capacitor includes:
forming a hard mask layer on the surface of the first metal layer;
forming an MIM capacitor pattern on the surface of the hard mask layer through a photoetching process;
etching the hard mask layer according to the MIM capacitor pattern;
and etching the second metal layer, the dielectric layer and the first metal layer in sequence according to the MIM capacitor pattern to form the MIM capacitor.
Optionally, the hard mask layer is a silicon nitride layer.
Optionally, the dielectric layer is a silicon nitride layer.
Optionally, the manufacturing method of the MIM capacitor is integrated in a metal interconnect process.
The technical scheme at least comprises the following advantages:
in the method for manufacturing the MIM capacitor according to the embodiment of the present application, the first metal layer is formed on the surface of the substrate, the dielectric layer is formed on the surface of the first metal layer, the second metal layer is formed on the surface of the dielectric layer, and the MIM capacitor is formed by etching using the gas containing chlorine-based gas or fluorine-based gas and CH4The etching gas etching material is a first metal layer and a second metal layer of tantalum nitride, so that the problem that a tantalum-containing polymer generated when the tantalum nitride is etched by the existing etching process is difficult to remove is solved; the effect of avoiding the tantalum-containing polymer residue in the manufacturing process of the MIM capacitor made of tantalum nitride is achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an MIM capacitor according to an embodiment of the present disclosure;
fig. 2 is a cross-sectional view of a MIM capacitor according to an embodiment of the present disclosure during fabrication;
fig. 3 is a cross-sectional view of a MIM capacitor according to an embodiment of the present disclosure during fabrication.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, a flow chart of a method for manufacturing a MIM capacitor according to an embodiment of the present application is shown, the method including the following steps:
step 101, forming a first metal layer on a surface of a substrate.
Optionally, the MIM capacitor is integrated in the back-end metal interconnect process.
In one example, after forming an x-th metal layer on a substrate, before fabricating a MIM capacitor, an NDC (nitrogen doped silicon carbide) layer is formed on a surface of the x-th metal layer, an oxide layer is formed on a surface of the NDC layer, and a first metal layer is formed on a surface of the oxide layer; x is a positive integer.
The first metal layer is used for forming a lower plate of the MIM capacitor, and the material of the first metal layer is tantalum nitride (TaN).
Optionally, tantalum nitride is deposited by a PVD process.
Step 102, forming a dielectric layer on the surface of the first metal layer.
Step 103, forming a second metal layer on the surface of the dielectric layer.
The second metal layer is used for forming an upper plate of the MIM capacitor.
The material of the second metal layer is tantalum nitride.
As shown in fig. 2, an x-th metal layer is formed on the substrate, the x-th metal layer includes an inter-metal interlayer dielectric layer 11 and a metal connection line 12, an NDC layer 13 is formed on a surface of the x-th metal layer, an oxide layer 14 is formed on a surface of the NDC layer 13, and a first metal layer 15, a dielectric layer 16, and a second metal layer 17 are sequentially formed above the oxide layer 14.
And 104, etching the second metal layer, the dielectric layer and the first metal layer to form the MIM capacitor.
And etching the second metal layer, etching the dielectric layer and then etching the first metal layer to form the MIM capacitor.
During the etching of the first metal layer and the second metal layer, the etching gas comprises CH4Chlorine-based gas or fluorine-based gas.
When the second metal layer is etched, the etching gas used is chlorine-based gas and CH4Or, fluorine-based gas and CH4。
When the first metal layer is etched, the etching gas used is chlorine-based gas and CH4Or, fluorine-based gas and CH4。
In an etching gas, CH4Is less than the content of the chlorine-based gas or the fluorine-based gas. CH (CH)4The ratio to the chlorine-based gas or the fluorine-based gas is about 1:10 to 1: 30.
Using a gas containing chlorine or fluorine, and CH4The etching gas can be used for etching the tantalum nitride, so that a byproduct which is easy to volatilize can be generated, and the generated tantalum-containing polymer residue is avoided.
In summary, in the manufacturing method of the MIM capacitor according to the embodiment of the present invention, the first metal layer is formed on the surface of the substrate, the dielectric layer is formed on the surface of the first metal layer, the second metal layer is formed on the surface of the dielectric layer, and the MIM capacitor is formed by etching using the gas containing chlorine-based gas or fluorine-based gas and CH4The etching gas etching material is a first metal layer and a second metal layer of tantalum nitride, so that the problem that a tantalum-containing polymer generated when the tantalum nitride is etched by the existing etching process is difficult to remove is solved; the effect of avoiding the tantalum-containing polymer residue in the manufacturing process of the MIM capacitor made of tantalum nitride is achieved.
In an alternative embodiment based on the embodiment shown in fig. 1, the dielectric layer is a silicon nitride layer.
In an alternative embodiment based on the embodiment shown in fig. 1, the step 104, i.e. the step of etching the second metal layer, the dielectric layer, and the first metal layer to form the MIM capacitor, can be implemented as follows:
in step 1041, a hard mask layer is formed on the surface of the first metal layer.
Optionally, the hard mask layer is a silicon nitride layer.
In step 1042, an MIM capacitor pattern is formed on the surface of the hard mask layer by a photolithography process.
A photoresist is coated on the surface of the hard mask layer 21, and a MIM capacitor pattern 22 is formed in the photoresist by a photolithography process, as shown in fig. 3.
And 1043, etching the hard mask layer according to the MIM capacitor pattern.
And etching the hard mask layer according to the MIM capacitor pattern in the photoresist layer, and transferring the MIM capacitor pattern into the hard mask layer.
And step 1044, sequentially etching the second metal layer, the dielectric layer and the first metal layer according to the MIM capacitor pattern to form the MIM capacitor.
Etching the second metal layer according to the MIM capacitor pattern, and taking the dielectric layer as an etching stop layer; and after the second metal layer is etched, continuously etching the dielectric layer and the first metal layer according to the MIM capacitor pattern to form the MIM capacitor.
When etching the first metal layer and the second metal layer, it is necessary to use a gas containing chlorine-based gas or fluorine-based gas, and CH4Of the etching gas.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (5)

1. A method of fabricating a MIM capacitor, the method comprising:
forming a first metal layer on the surface of a substrate, wherein the first metal layer is used for forming a lower plate of the MIM capacitor;
forming a dielectric layer on the surface of the first metal layer;
forming a second metal layer on the surface of the dielectric layer, wherein the second metal layer is used for forming an upper plate of the MIM capacitor;
etching the second metal layer, the dielectric layer and the first metal layer to form an MIM capacitor;
wherein, in the etching process of the first metal layer and the second metal layer, the etching gas comprises chlorine-based gas or fluorine-based gas, CH4(ii) a The first metal layer and the second metal layer are made of tantalum nitride.
2. The method of claim 1, wherein etching the second metal layer, the dielectric layer, and the first metal layer to form a MIM capacitor comprises:
forming a hard mask layer on the surface of the first metal layer;
forming an MIM capacitor pattern on the surface of the hard mask layer through a photoetching process;
etching the hard mask layer according to the MIM capacitor pattern;
and etching the second metal layer, the dielectric layer and the first metal layer in sequence according to the MIM capacitor pattern to form the MIM capacitor.
3. The method of claim 2, wherein the hard mask layer is a silicon nitride layer.
4. A method according to any one of claims 1 to 3, wherein the dielectric layer is a silicon nitride layer.
5. The method of any of claims 1 to 3, wherein the method of manufacturing the MIM capacitor is integrated in a metal interconnect process.
CN202011289254.1A 2020-11-17 2020-11-17 Manufacturing method of MIM capacitor Withdrawn CN112397386A (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050170583A1 (en) * 2003-12-31 2005-08-04 Park Jeong H. Methods of fabricating MIM capacitors of semiconductor devices
CN102054756A (en) * 2009-11-10 2011-05-11 中芯国际集成电路制造(上海)有限公司 Copper interconnection structure and formation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050170583A1 (en) * 2003-12-31 2005-08-04 Park Jeong H. Methods of fabricating MIM capacitors of semiconductor devices
CN102054756A (en) * 2009-11-10 2011-05-11 中芯国际集成电路制造(上海)有限公司 Copper interconnection structure and formation method thereof

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