JPH0574963A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0574963A
JPH0574963A JP3245673A JP24567391A JPH0574963A JP H0574963 A JPH0574963 A JP H0574963A JP 3245673 A JP3245673 A JP 3245673A JP 24567391 A JP24567391 A JP 24567391A JP H0574963 A JPH0574963 A JP H0574963A
Authority
JP
Japan
Prior art keywords
film
insulating film
tungsten
ladder polymer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3245673A
Other languages
Japanese (ja)
Inventor
Hiroshi Adachi
廣士 足達
Etsushi Adachi
悦志 足立
Shintarou Minami
伸太朗 南
Hideo Kotani
秀夫 小谷
Yoshio Hayashide
吉生 林出
Toshiaki Tsutsumi
聡明 堤
Masazumi Matsuura
正純 松浦
Atsushi Ishii
敦司 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3245673A priority Critical patent/JPH0574963A/en
Priority to DE4218495A priority patent/DE4218495A1/en
Priority to KR1019920009752A priority patent/KR930001312A/en
Publication of JPH0574963A publication Critical patent/JPH0574963A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain substantially uniform insulating film between wiring layers by substantially equalizing heights of protrusions corresponding to patterns of first wiring formed on an insulating film, and employing an insulating film having a groove wider than that of the groove of the pattern of the first wiring. CONSTITUTION:An insulating film is buried in a height higher than an Al pattern 1 between the Al patterns 1 to become first wiring, heights of protrusions to be formed corresponding to the patterns 1 are substantially equalized, an insulating film, in which a groove interposed to be held between the protrusions is wider than the interval between the patterns 1, is formed as a first layer insulating film 3, and a second layer insulating film 4 is continuously formed of an insulating film having high fluidity. Thus, the film 4 is easily introduced into the groove interposed to be held between the protrusions of the film 3, and formed in a shape accumulated between the protrusions. Thus, a substantially uniform insulting film between wiring layers can be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関するもの
であり、特にコンタクト孔を介した配線の形成が容易で
ある層間絶縁膜を有する半導体装置、及びその製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an interlayer insulating film in which wiring can be easily formed through a contact hole, and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】ＬＳＩの高集積化、微細化に伴い層間配
線のためのコンタクト孔の径が小さくなり、配線の段差
被覆が悪く接触抵抗が大きくなるという問題点が生じて
いた。そのため、従来よりコンタクト孔を金属で埋め込
むという方法が採用されている。2. Description of the Related Art Along with the high integration and miniaturization of LSIs, the diameter of contact holes for interlayer wiring has become small, and the step coverage of the wiring has been poor and the contact resistance has increased. Therefore, conventionally, a method of filling the contact hole with metal has been adopted.

【０００３】例えば図２３（ａ）〜（ｆ）はそれぞれ従
来のコンタクト孔をタングステン（Ｗ）で埋め込む場合
について工程順に示した断面モデル図である。図におい
て、１は素子が形成された半導体基板、２は絶縁膜であ
るシリコン酸化膜、３はＡｌ合金、例えばＡｌＳｉ合金
からなる第１の金属配線、４は層間絶縁膜である例えば
シリコン酸化膜、６はコンタクト孔を形成するためのマ
スクとなるフォトレジスト、７はコンタクト孔に埋め込
まれた金属層で、例えばタングステン、８はコンタクト
孔を介して配線される第２の金属配線であり、Ａｌ合
金、例えばＡｌＳｉ合金からなる。For example, FIGS. 23 (a) to 23 (f) are cross-sectional model diagrams showing the order of steps in the case where a conventional contact hole is filled with tungsten (W). In the figure, 1 is a semiconductor substrate on which elements are formed, 2 is a silicon oxide film that is an insulating film, 3 is a first metal wiring made of an Al alloy, for example, AlSi alloy, and 4 is a silicon oxide film that is an interlayer insulating film. , 6 is a photoresist serving as a mask for forming a contact hole, 7 is a metal layer embedded in the contact hole, for example, tungsten, 8 is a second metal wiring to be wired through the contact hole, and Al It is made of an alloy such as an AlSi alloy.

【０００４】次に製造方法について説明する。まず、図
２３（ａ）に示すように半導体基板１上に絶縁膜である
シリコン酸化膜２をＣＶＤ法により形成し、更にこの上
にＡｌ合金例えばＡｌＳｉ合金からなる第１の金属配線
３を、スパッタリング及びフォトリソグラフィ技術で作
製する。なお、ここではこの第１の金属配線３に接続さ
れるべきトランジスタ等の能動素子については、簡単の
ため省略している。Next, the manufacturing method will be described. First, as shown in FIG. 23A, a silicon oxide film 2 as an insulating film is formed on a semiconductor substrate 1 by a CVD method, and a first metal wiring 3 made of an Al alloy, for example, an AlSi alloy, is further formed thereon. It is produced by sputtering and photolithography technology. Here, active elements such as transistors to be connected to the first metal wiring 3 are omitted for simplicity.

【０００５】次に、層間絶縁膜であるシリコン酸化膜４
をＣＶＤ法によってシリコン酸化膜２及び第１の金属配
線３上に形成する（図２３(ｂ)）。更にその後フォトレ
ジスト６を形成し、露光、現像によってコンタクト孔部
分のシリコン酸化膜４を暴露させる（図２３(ｃ)）。次
に、シリコン酸化膜４のエッチング、フォトレジスト６
の除去を行い、コンタクト孔を形成する（図２３
(ｄ)）。Next, the silicon oxide film 4 which is an interlayer insulating film
Is formed on the silicon oxide film 2 and the first metal wiring 3 by the CVD method (FIG. 23B). After that, a photoresist 6 is formed, and the silicon oxide film 4 in the contact hole portion is exposed by exposure and development (FIG. 23 (c)). Next, the silicon oxide film 4 is etched and the photoresist 6 is used.
Are removed to form contact holes (FIG. 23).
(d)).

【０００６】次に、金属弗化物、例えばＷＦ6 を原料ガ
スとして含むＣＶＤ法により金属層であるタングステン
７を形成し、コンタクト孔を埋め込む（図２３(ｅ)）。
この時にＣＶＤ法の条件を適当に選べばタングステン７
は第１の金属配線３上にのみ形成され、埋め込みは自己
整合的に行われる。例えば原材料ガスとしてＷＦ6 とＳ
ｉＨ4 を含有するものを用いてそれぞれの分圧を数ｍＴ
ｏｒｒとし、流量比をＳｉＨ4 ／ＷＦ6 ＜０．６とし、
形成温度を約３００℃とすればよい。Next, a metal layer of tungsten 7 is formed by a CVD method containing a metal fluoride such as WF 6 as a source gas, and the contact hole is filled (FIG. 23 (e)).
At this time, if the conditions of the CVD method are properly selected, tungsten 7
Are formed only on the first metal wiring 3, and the filling is performed in a self-aligned manner. For example, WF 6 and S as raw material gases
Each of the partial pressures is several mT using the one containing iH 4.
orr and the flow rate ratio is SiH 4 / WF 6 <0.6,
The formation temperature may be about 300 ° C.

【０００７】最後に、タングステン７とコンタクトをと
るように、ＡｌＳｉ合金からなる第２の金属配線８を、
スパッタリング及びフォトリソグラフィ技術で作製す
る。これにより第１の金属配線３と第２の金属配線８
は、層間をシリコン酸化膜４に開けられたコンタクト孔
中の金属層（タングステン７）を介して導通する（図２
３（ｆ））。Finally, a second metal wiring 8 made of an AlSi alloy is formed so as to make contact with the tungsten 7.
It is produced by sputtering and photolithography technology. Thereby, the first metal wiring 3 and the second metal wiring 8
Conducts between the layers via the metal layer (tungsten 7) in the contact hole formed in the silicon oxide film 4 (FIG. 2).
3 (f)).

【０００８】[0008]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されており、層間絶縁膜にＣＶＤ法によ
るシリコン酸化膜が用いられている。ところで、コンタ
クト孔の埋め込み金属であるタングステンをＣＶＤ法に
よって形成するとき、成長速度が下地材料に依存する事
が知られている。例えば、刊行物（ＮＩＫＫＥＩ ＭＩ
ＣＲＯＤＥＶＩＣＥＳ １９９１年２月号４８頁）に示
されるように、タングステンの成長は下地材料が金属の
方が絶縁物より成長しやすい。即ち、電気陰性度が小さ
く、電子を与え易い材料ほどタングステンは成長し易
い。The conventional semiconductor device is configured as described above, and the silicon oxide film formed by the CVD method is used as the interlayer insulating film. By the way, it is known that the growth rate depends on the underlying material when tungsten, which is the metal for filling the contact hole, is formed by the CVD method. For example, the publication (NIKKEI MI
As shown in CRODEVICES, February 1991, p. 48), the growth of tungsten is easier when the underlying material is metal than when it is an insulator. That is, the smaller the electronegativity and the easier it is to give electrons, the more easily tungsten grows.

【０００９】また、絶縁膜としてよく用いられるシリコ
ン酸化膜４の種類によってもタングステン７の成長速度
が異なることもわかっており、タングステンＣＶＤ法で
はシリコンの熱酸化による膜が最も成長しにくく、プラ
ズマＣＶＤ膜上には成長しやすい。従って、層間絶縁膜
にシリコンの熱酸化膜を用いると良いようであるが、第
１の金属配線の耐熱性に制限を受けるため、層間絶縁膜
には従来、上述したＣＶＤ法によるシリコン酸化膜が用
いられてきた。It is also known that the growth rate of tungsten 7 varies depending on the type of the silicon oxide film 4 often used as an insulating film. In the tungsten CVD method, a film formed by thermal oxidation of silicon is the most difficult to grow, and plasma CVD is used. It is easy to grow on the film. Therefore, it seems to be good to use a thermal oxide film of silicon for the interlayer insulating film, but since the heat resistance of the first metal wiring is limited, the silicon oxide film by the above-mentioned CVD method is conventionally used for the interlayer insulating film. Has been used.

【００１０】そこで例えば、刊行物（Ｊ．Ｅｌｅｃｔｒ
ｏｃｈｅｍ．Ｓｏｃ．：ＳＯＬＩＤーＳＴＡＴＥ ＳＣ
ＩＥＮＣＥ ＡＮＤ ＴＥＣＨＮＯＬＯＧＹ Ｖｏｌ．
１３３，Ｎｏ．６，Ｊｕｎｅ １９８６）に示されてい
るように、ＣＶＤ法による層間絶縁膜にリンをドープす
ることにより、シリコン酸化膜（層間絶縁膜）上にタン
グステンが成長しないようにする方法が考えられてい
る。ところが、リンを多くドープするほど膜の耐湿性が
低下し、半導体装置の信頼性が低くなる。Therefore, for example, publications (J. Electr
ochem. Soc. : SOLID-STATE SC
IENCE AND TECHNOLOGY Vol.
133, No. 6, June 1986), a method has been considered in which tungsten is not grown on a silicon oxide film (interlayer insulating film) by doping phosphorus into the interlayer insulating film by the CVD method. .. However, the more phosphorus is doped, the lower the moisture resistance of the film and the lower the reliability of the semiconductor device.

【００１１】また、ＣＶＤ法によるシリコン酸化膜を用
いた場合、コンタクト孔にタングステン５をＣＶＤ法に
より形成するとき、第１の金属配線上にのみ形成できる
プロセス条件が極めて少なく、多くの条件下では、層間
絶縁膜上にもタングステンが析出する。この析出したタ
ングステンは、配線間ショートを引き起こし、半導体装
置としての機能を破壊する問題があった。そしてまた、
析出したタングステンを除去するためには、全面エッチ
バックを行う必要があり、工程が複雑になり、その際、
コンタクト孔に埋め込まれたタングステンも膜減りする
という問題もあった。Further, when a silicon oxide film formed by the CVD method is used, when tungsten 5 is formed in the contact hole by the CVD method, there are very few process conditions that can be formed only on the first metal wiring, and under many conditions. Tungsten is also deposited on the interlayer insulating film. The deposited tungsten causes a short circuit between wirings, and there is a problem that the function as a semiconductor device is destroyed. and again,
In order to remove the deposited tungsten, it is necessary to perform a full etch back, which complicates the process.
There is also a problem that the film of tungsten embedded in the contact hole is also reduced.

【００１２】本発明は上記のような問題点を解消するた
めになされたもので、例えばタングステン７をＣＶＤ法
により形成するとき、いかなる条件下でも層間絶縁膜上
には成長せず、コンタクト孔にのみタングステンを埋め
込むことができ、その結果、電気抵抗が低いタングステ
ンのＣＶＤ条件を選ぶことができ、また、層間絶縁膜上
にタングステンが析出せず、エッチバックする必要がな
い半導体装置及びその製造方法を得ることを目的とす
る。The present invention has been made in order to solve the above problems. For example, when tungsten 7 is formed by the CVD method, it does not grow on the interlayer insulating film under any conditions and contact holes are formed. Only the tungsten can be embedded, and as a result, the CVD condition of the tungsten having a low electric resistance can be selected, and the tungsten is not deposited on the interlayer insulating film and the semiconductor device is not required to be etched back. Aim to get.

【００１３】而して、本発明者等は鋭意研究の結果、樹
脂膜上にはタングステンの核が成長しないことを見いだ
し本発明を完成するに至った。即ち、プラズマＣＶＤ膜
は組成が化学量論比よりずれ、不対電子が表面に存在
し、これに核が成長すると考えた。従って組成が化学量
論比であり、不対電子が存在しない樹脂膜をマスク材と
して用いる方法を研究し、本発明を完成するに至った。As a result of earnest studies, the present inventors have found that the nucleus of tungsten does not grow on the resin film and completed the present invention. That is, it was considered that the composition of the plasma CVD film deviated from the stoichiometric ratio, unpaired electrons existed on the surface, and nuclei grew on this. Therefore, the present invention has been completed by researching a method of using a resin film having a stoichiometric composition and no unpaired electrons as a mask material.

【００１４】[0014]

【課題を解決するための手段】本発明に係る半導体装置
は、第１、第２の金属配線間に介在する層間絶縁膜の少
なくとも最上層部が樹脂膜からなるものである。In the semiconductor device according to the present invention, at least the uppermost layer of the interlayer insulating film interposed between the first and second metal wirings is made of a resin film.

【００１５】また、樹脂膜には下記化学式（１）で示さ
れるシリコーンラダーポリマーの硬化膜を用いる。As the resin film, a cured film of silicone ladder polymer represented by the following chemical formula (1) is used.

【００１６】[0016]

【化２】 [Chemical 2]

【００１７】さらに、シリコーンラダーポリマーの硬化
膜として光重合性のシリコーンラダーポリマーの硬化膜
をを用いる。Further, as the cured film of the silicone ladder polymer, a cured film of a photopolymerizable silicone ladder polymer is used.

【００１８】そして、本発明の半導体の製造方法は、上
記化学式（１）で示されるシリコーンラダーポリマー膜
をマスク材としてＣＶＤ法によって層間絶縁膜に開けら
れたコンタクト孔に金属を埋め込むことによって金属層
を形成するものである。In the method for manufacturing a semiconductor of the present invention, a metal layer is formed by embedding a metal in a contact hole formed in an interlayer insulating film by a CVD method using the silicone ladder polymer film represented by the chemical formula (1) as a mask material. Is formed.

【００１９】[0019]

【作用】本発明では、層間絶縁膜の少なくとも最上層に
樹脂膜を用いたので、層間絶縁膜中に開けたコンタクト
孔内に選択的にタングステンなどの金属層を形成する場
合、層間絶縁膜のシリコン酸化膜や窒化膜上に直接形成
する場合と比較して選択性が大幅に向上する。従って、
シリコン酸化膜や窒化膜を層間絶縁膜として用いた場合
に選択性が失われるような形成条件下でも層間絶縁膜上
には全く成長せず、コンタクト孔にのみタングステンな
どの金属膜を埋め込むことができる。従って、電気抵抗
が低いタングステンのＣＶＤ条件を選ぶことができる。
また、層間絶縁膜上にタングステン等の金属が析出しな
いので、エッチバックする必要もない。In the present invention, since the resin film is used as at least the uppermost layer of the interlayer insulating film, when a metal layer such as tungsten is selectively formed in the contact hole formed in the interlayer insulating film, the interlayer insulating film The selectivity is significantly improved as compared with the case of forming directly on the silicon oxide film or the nitride film. Therefore,
Even if a silicon oxide film or a nitride film is used as an interlayer insulating film, no growth occurs on the interlayer insulating film even under the forming condition that selectivity is lost, and a metal film such as tungsten may be embedded only in the contact hole. it can. Therefore, it is possible to select the CVD condition of tungsten having a low electric resistance.
Further, since metal such as tungsten is not deposited on the interlayer insulating film, there is no need to etch back.

【００２０】また、シリコーンラダーポリマー膜は平坦
性が良好であるので、そのシリコーンラダーポリマー膜
の上には断線に対して耐性のある金属配線層を形成でき
る。Further, since the silicone ladder polymer film has good flatness, a metal wiring layer resistant to disconnection can be formed on the silicone ladder polymer film.

【００２１】さらに、光重合性のシリコーンラダーポリ
マー膜を用いたので、フォトレジストが不要となり、そ
の分製造工程を削減できる。Furthermore, since a photopolymerizable silicone ladder polymer film is used, a photoresist is not required, and the manufacturing process can be reduced accordingly.

【００２２】そして、マスク材として上記化学式（１）
に示したシリコーンラダーポリマー膜を用い、層間絶縁
膜を被ったので、タングステンをＣＶＤ法により形成す
るとき、いかなる条件下でも層間絶縁膜上には全く成長
せず、コンタクト孔にのみタングステンを埋め込むこと
ができる。従って、電気抵抗が低いタングステンのＣＶ
Ｄ条件を選ぶことができる。また、層間絶縁膜上にタン
グステンが析出しないので、エッチバックする必要もな
い。Then, as the mask material, the above chemical formula (1) is used.
Since the interlayer insulation film was covered with the silicone ladder polymer film shown in Fig. 3, when tungsten is formed by the CVD method, it does not grow on the interlayer insulation film under any conditions and the contact hole is filled with tungsten. You can Therefore, CV of tungsten with low electrical resistance
D condition can be selected. Further, since tungsten is not deposited on the interlayer insulating film, there is no need to etch back.

【００２３】[0023]

【実施例】実施例１．図１〜図６はそれぞれ、本発明の
第１の実施例の半導体装置、その製造方法の一例を工程
順に示す断面モデル図である。各図において、１〜３，
６〜８は従来の場合と同一のものである。５は層間絶縁
膜で、この場合はシリコン酸化膜５ａとシリコン酸化膜
５ａ上に形成された樹脂膜のポリイミド膜５ｂの二層膜
からなる。EXAMPLES Example 1. 1 to 6 are sectional model views showing a semiconductor device according to a first embodiment of the present invention and an example of a method of manufacturing the semiconductor device in the order of steps. In each figure, 1-3,
6 to 8 are the same as in the conventional case. Reference numeral 5 denotes an interlayer insulating film, which in this case is a two-layer film including a silicon oxide film 5a and a polyimide film 5b which is a resin film formed on the silicon oxide film 5a.

【００２４】次に製造方法について説明する。まず、シ
リコン酸化膜５ａを形成するところまでは従来の場合と
同様であり、半導体基板１上にシリコン酸化膜２を形成
し、この上に第１の金属配線３を作成した後、シリコン
酸化膜５ａをＣＶＤ法等によりシリコン酸化膜２及び第
１の金属配線３上に形成する。（図１）。Next, the manufacturing method will be described. First, the process up to the step of forming the silicon oxide film 5a is the same as in the conventional case. After forming the silicon oxide film 2 on the semiconductor substrate 1 and forming the first metal wiring 3 thereon, the silicon oxide film 5a is formed. 5a is formed on the silicon oxide film 2 and the first metal wiring 3 by the CVD method or the like. (Figure 1).

【００２５】次に、シリコン酸化膜５ａ上に高耐熱ポリ
マーとして電子デバイス用に市販されているポリイミド
樹脂を（日立化成(株)：ＰＩＱ，０．８μｍ）回転塗布
し、１５０℃で３０分、３５０℃で６０分間熱処理して
ポリイミド樹脂膜５ｂを形成する（図２）。次に従来と
同様にしてフォトレジスト６を塗布してコンタクト孔に
合わせてパターン形成した（図３）。そしてヒドラジン
を用いて，ポリイミド樹脂膜に所定のパタ−ンを形成し
た。それから従来と同様にしてシリコン酸化膜５ｂをエ
ッチングし，次いでレジスト６を酸素プラズマで除去す
る（図４）。この時ＰＩＱもいく分エッチングされるの
で初期の膜厚を厚くした。その後、従来と同様にしてＷ
Ｆ6 を含む原料ガスを用いたＣＶＤ法によりタングステ
ン７を形成した。このとき、いかなるＣＶＤ条件におい
ても第１の金属配線３上のみにタングステンが形成さ
れ、ポリイミド膜５ｂ上には全く成長しなかった（図
５）。さらに、従来の場合と同様に、タングステン７と
コンタクトをとるようにＡｌＳｉ合金からなる第２の金
属配線８を、スパッタリング、およびフォトリソグラフ
ィ技術で作製した（図６）。Next, a polyimide resin commercially available for electronic devices as a high heat-resistant polymer (PIQ, 0.8 μm, Hitachi Chemical Co., Ltd.) was spin-coated on the silicon oxide film 5a, and the coating was performed at 150 ° C. for 30 minutes. Heat treatment is performed at 350 ° C. for 60 minutes to form a polyimide resin film 5b (FIG. 2). Photoresist 6 was then applied in the same manner as in the prior art to form a pattern in accordance with the contact holes (FIG. 3). Then, using hydrazine, a predetermined pattern was formed on the polyimide resin film. Then, the silicon oxide film 5b is etched in a conventional manner, and then the resist 6 is removed by oxygen plasma (FIG. 4). At this time, the PIQ is also etched to some extent, so the initial film thickness was increased. After that, W
Tungsten 7 was formed by a CVD method using a source gas containing F6. At this time, under any CVD conditions, tungsten was formed only on the first metal wiring 3 and did not grow at all on the polyimide film 5b (FIG. 5). Further, similarly to the conventional case, the second metal wiring 8 made of an AlSi alloy was formed by sputtering and photolithography so as to make contact with the tungsten 7 (FIG. 6).

【００２６】このように、この実施例の半導体装置で
は、層間絶縁膜５の最上層にポリイミド膜５ｂを用いた
ので、コンタクト孔内にタングステンを埋め込む際のい
かなるＣＶＤ条件においても、層間絶縁膜上、即ちポリ
イミド膜５ｂ上にタングステン７は成長せず、コンタク
ト孔にのみタングステン７を埋め込むことができる。従
って、タングステン形成時のＣＶＤ条件の選択の自由度
が向上し、例えば電気抵抗が低いタングステンのＣＶＤ
条件を選ぶことができ、その結果安定でかつ低いコンタ
クト抵抗を示す半導体装置を得ることができる。また、
層間絶縁膜５上に金属、タングステン７が析出しないの
で、配線間ショートを引き起こすことがない。また析出
した金属、タングステン７をエッチバックする必要もな
いので、コストの低減が図れる。As described above, in the semiconductor device of this embodiment, since the polyimide film 5b is used as the uppermost layer of the interlayer insulating film 5, the interlayer insulating film is formed on the interlayer insulating film under any CVD condition when burying tungsten in the contact hole. That is, the tungsten 7 does not grow on the polyimide film 5b, and the tungsten 7 can be embedded only in the contact hole. Therefore, the degree of freedom in selecting the CVD conditions at the time of forming tungsten is improved, and for example, CVD of tungsten having low electric resistance is performed.
Conditions can be selected, and as a result, a semiconductor device that is stable and exhibits low contact resistance can be obtained. Also,
Since metal and tungsten 7 are not deposited on the interlayer insulating film 5, short circuit between wirings is not caused. Further, since it is not necessary to etch back the deposited metal and tungsten 7, the cost can be reduced.

【００２７】実施例２．ポリイミド樹脂の代わりに、フ
ッ素系樹脂（旭硝子（株）：サイトップ，０．６μｍ）
用い、層間絶縁膜の上層としてフッ素系樹脂膜を形成し
た。この樹脂膜５ｂをＣＦ4 でエッチングした以外は実
施例１と同様にして、タングステンを成膜した。この時
いかなる条件においても第１の金属配線３上にのみタン
グステンが形成され、サイトップ膜５ｂ上には全く成長
しなかった。Example 2. Fluorine resin instead of polyimide resin (Asahi Glass Co., Ltd .: CYTOP, 0.6 μm)
A fluorine resin film was formed as an upper layer of the interlayer insulating film. Tungsten was formed in the same manner as in Example 1 except that the resin film 5b was etched with CF4. At this time, under any condition, tungsten was formed only on the first metal wiring 3 and did not grow at all on the Cytop film 5b.

【００２８】実施例３．ポリイミド樹脂の代わりに、シ
クロブテン樹脂（ＤＯＷＣＨＥＭＩＣＡＬ社：ＢＣＢ，
０．６μｍ）を用い、層間絶縁膜の上層としてシクロブ
テン樹脂膜を形成した。この樹脂膜５ｂをＯ2／ＳＦ6で
エッチングした以外は実施例１と同様にして、タングス
テンを成膜した。この時いかなる条件においても第１の
金属配線３上にのみタングステンが形成され、シクロブ
テン膜５ｂ上には全く成長しなかった。Example 3. Instead of the polyimide resin, cyclobutene resin (DOWCHEMICAL: BCB,
0.6 μm) was used to form a cyclobutene resin film as an upper layer of the interlayer insulating film. Tungsten was formed in the same manner as in Example 1 except that this resin film 5b was etched with O2 / SF6. At this time, under any condition, tungsten was formed only on the first metal wiring 3 and did not grow at all on the cyclobutene film 5b.

【００２９】実施例４．ポリイミド樹脂の代わりに、層
間絶縁膜の上層として下記化学式（２）で示されるシリ
コーンラダーポリマーの硬化膜を用いた場合について説
明する。Example 4. A case where a cured film of a silicone ladder polymer represented by the following chemical formula (2) is used as the upper layer of the interlayer insulating film instead of the polyimide resin will be described.

【００３０】[0030]

【化３】 [Chemical 3]

【００３１】実施例１と同様にしてシリコン酸化膜５ａ
まで形成する（図１）。次に、シリコン酸化膜５ａ上
に、上記化学式（２）で示される重量平均分子量が１０
万であるシリコーンラダーポリマーのアニソール溶液
（５重量％の濃度に調整されている）を回転塗布し、
０．２μｍのシリコーンラダーポリマー膜を形成する。
次に、１５０℃で３０分間と３５０℃で６０分間の熱処
理を行い熱硬化させ、シリコーンラダーポリマー膜５ｂ
とする（図２）。なお、化学式（２）に示す末端に水酸
基を有するシリコーンラダーポリマーは、特開平１ー９
２２２４号公報に開示された方法によって作られたもの
である。Similar to the first embodiment, the silicon oxide film 5a is formed.
(Fig. 1). Next, on the silicon oxide film 5a, the weight average molecular weight represented by the chemical formula (2) is 10
Anisole solution of silicone ladder polymer (adjusted to a concentration of 5% by weight) is spin coated,
A 0.2 μm silicone ladder polymer film is formed.
Next, heat treatment is performed at 150 ° C. for 30 minutes and 350 ° C. for 60 minutes to thermally cure the silicone ladder polymer film 5b.
(Fig. 2). The silicone ladder polymer having a hydroxyl group at the terminal represented by the chemical formula (2) is disclosed in JP-A-1-9.
It is produced by the method disclosed in Japanese Patent No. 2224.

【００３２】次に上記実施例と同様にしてフォトレジス
ト６をコンタクト孔にあわせてパターン形成し（図
３）、従来と同様のシリコン酸化膜５ａをエッチングす
る方法で、例えば、ＣＨＦ3 と酸素の混合ガスのプラズ
マエッチングによりコンタクト孔を形成する。このとき
シリコン酸化膜５ａとシリコーンラダーポリマー膜５ｂ
との２層からなる層間絶縁膜５を１つのエッチングプロ
セスによって同時に開孔することができる（図４）。そ
の後、実施例１と同様にして、ＷＦ6 を含む原料ガスを
用いたＣＶＤ法によりタングステン７をコンタクト孔に
埋め込む。このとき、いかなるＣＶＤ条件においても第
１の金属配線３上のみにタングステン７が形成され、シ
リコーンラダーポリマー膜５ｂ上には全く成長しなかっ
た（図５）。さらに、同様に、タングステン７とコンタ
クトをとるようにＡｌＳｉ合金からなる第２の金属配線
８を、スパッタリング、およびフォトリソグラフィ技術
で作製した（図６）。[0032] Then the photoresist 6 in the same manner as above Example to form a pattern in accordance with the contact hole (Fig. 3), in conventional methods for etching the same silicon oxide film 5a, for example, CHF 3 and oxygen Contact holes are formed by plasma etching of mixed gas. At this time, the silicon oxide film 5a and the silicone ladder polymer film 5b
It is possible to simultaneously open holes in the interlayer insulating film 5 composed of two layers (1) and (2) by one etching process (FIG. 4). Then, similarly to Example 1, the contact hole is filled with tungsten 7 by the CVD method using the raw material gas containing WF 6 . At this time, under any CVD condition, tungsten 7 was formed only on the first metal wiring 3 and did not grow at all on the silicone ladder polymer film 5b (FIG. 5). Further, similarly, a second metal wiring 8 made of an AlSi alloy so as to make contact with the tungsten 7 was produced by sputtering and photolithography technique (FIG. 6).

【００３３】この実施例においては、シリコーンラダー
ポリマー膜５ｂを用いたので、上記実施例の効果に加
え、コンタクト孔を形成する時にシリコン酸化膜５ａと
同じエッチングプロセスでシリコーンラダーポリマー膜
５ｂも同時に開孔でき、製造工程が削減でき、簡略化で
きる。また、シリコーンラダーポリマー膜は、例えばポ
リイミド樹脂膜に比べ５０℃程度耐熱性が優れ、電気特
性においても絶縁性が良好で、誘電体損失の比を示すｔ
ａｎδが１桁小さく、内部応力も半分程度と優れてい
る。従って上記実施例より半導体装置としての信頼性も
優れている。なお、ｔａｎδとは印加電圧Ｅをかけたと
きに流れる交流電流Ｉのリーク電流成分Ｉ2と、変位電
流Ｉ1 （＝Ｉ−Ｉ2 ）との比である。また、シリコーン
ラダーポリマー膜５ｂは平坦性が良好であるので、この
シリコーンラダーポリマー膜５ｂの上に、断線に対して
耐性のある第２の金属配線層８を形成することができ
る。さらに、シリコーンラダーポリマー膜５ｂはシリコ
ンの熱酸化膜よりはるかに穏和な低温条件で形成するこ
とができるので、下層の第１の配線３の耐熱性の制限に
適うものである。In this embodiment, since the silicone ladder polymer film 5b is used, in addition to the effects of the above embodiment, when the contact hole is formed, the silicone ladder polymer film 5b is simultaneously opened by the same etching process as the silicon oxide film 5a. The holes can be formed, and the manufacturing process can be reduced and simplified. Further, the silicone ladder polymer film is superior in heat resistance to, for example, about 50 ° C. as compared with a polyimide resin film, has good insulating properties in electrical characteristics, and exhibits a dielectric loss ratio t.
The an δ is smaller by one digit, and the internal stress is excellent at about half. Therefore, the reliability as a semiconductor device is also superior to that of the above-mentioned embodiment. Note that tan δ is the ratio of the leakage current component I 2 of the alternating current I flowing when the applied voltage E is applied and the displacement current I 1 (= I−I 2 ). Further, since the silicone ladder polymer film 5b has good flatness, the second metal wiring layer 8 resistant to disconnection can be formed on the silicone ladder polymer film 5b. Furthermore, since the silicone ladder polymer film 5b can be formed under a much lower temperature condition than the thermal oxide film of silicon, it is suitable for limiting the heat resistance of the lower first wiring 3.

【００３４】実施例５．図７〜図１２は、それぞれ樹脂
膜として光重合性のシリコーンラダーポリマー硬化膜を
用いた場合の製造方法をを工程順に示す断面モデル図で
ある。５ｃは層間絶縁膜５の上層の樹脂膜で、光重合性
のシリコーンラダーポリマー膜である。従来例と同様に
してシリコン酸化膜５ａまでを形成する（図７）。次
に、下記化学式（３）で示される、重量平均分子量が１
０万であるシリコーンラダーポリマーのアニソール溶液
（１０．０重量％の濃度に調整され，増感剤としてビス
アジド化合物を約３％含む）を回転塗布し、１．０μｍ
の光重合性のシリコーンラダーポリマー膜５ｃを形成
し、１５０℃で３０分間の熱処理をおこなった（図
８）。その後、所定のパターンを有したマスクを通して
光を照射し、次いで有機溶剤で未露光部分のシリコ−ン
ラダーポリマーを除去する（図９）。次いで３５０℃で
熱処理を行う。Example 5. 7 to 12 are cross-sectional model views showing the manufacturing method in the order of steps when a photopolymerizable silicone ladder polymer cured film is used as the resin film. A resin film 5c is an upper layer of the interlayer insulating film 5, and is a photopolymerizable silicone ladder polymer film. Similar to the conventional example, up to the silicon oxide film 5a is formed (FIG. 7). Next, the weight average molecular weight represented by the following chemical formula (3) is 1
Anisole solution of silicone ladder polymer of 0,000 (adjusted to a concentration of 10.0% by weight and containing about 3% of a bisazide compound as a sensitizer) was spin-coated to 1.0 μm.
The photopolymerizable silicone ladder polymer film 5c was formed and heat-treated at 150 ° C. for 30 minutes (FIG. 8). Then, light is irradiated through a mask having a predetermined pattern, and then the unexposed portion of the silicone ladder polymer is removed with an organic solvent (FIG. 9). Next, heat treatment is performed at 350 ° C.

【００３５】[0035]

【化４】 [Chemical 4]

【００３６】次に従来と同様にシリコン酸化膜５ａをエ
ッチングする方法で、所定のパターンを有するシリコー
ンラダーポリマー膜５ｃをマスクとして、例えばＣＨＦ
3 と酸素の混合ガスのプラズマエッチングによりシリコ
ン酸化膜５ａにコンタクト孔を形成する（図１０）。こ
のときシリコ−ンラダ−ポリマ−膜５ｃもエッチングさ
れるが，エッチングレイトがシリコン酸化膜５ａの１／
３以下なので問題はない。その後上記実施例と同様にし
て、ＷＦ6 を含む原料ガスを用いたＣＶＤ法によりタン
グステン７を形成した。このとき、いかなるＣＶＤ条件
においても第１の金属配線３上のみにタングステン７が
形成され、シリコーンラダーポリマー膜５ｃ上には全く
成長しなかった（図１１）。さらに、同様に、第２の金
属配線８を作製し、第１と第２の金属配線３，８間をコ
ンタクト孔を介して導通させた（図１２）。Then, the same method as in the conventional method is used to etch the silicon oxide film 5a, using the silicone ladder polymer film 5c having a predetermined pattern as a mask, for example, CHF.
Contact holes are formed in the silicon oxide film 5a by plasma etching using a mixed gas of 3 and oxygen (FIG. 10). At this time, the silicon ladder polymer film 5c is also etched, but the etching rate is 1 / th that of the silicon oxide film 5a.
Since it is 3 or less, there is no problem. Then, in the same manner as in the above example, tungsten 7 was formed by the CVD method using the raw material gas containing WF 6 . At this time, under any CVD condition, tungsten 7 was formed only on the first metal wiring 3 and did not grow at all on the silicone ladder polymer film 5c (FIG. 11). Further, similarly, the second metal wiring 8 was produced, and the first and second metal wirings 3, 8 were electrically connected via the contact holes (FIG. 12).

【００３７】この実施例においては、上記実施例の場合
のようにフォトレジスト６が不要となり、その分製造工
程が削減でき、簡略化できる。In this embodiment, the photoresist 6 is not required as in the case of the above embodiment, and the manufacturing process can be reduced and the structure can be simplified accordingly.

【００３８】なお、水酸基を有する光重合性のシリコー
ンラダーポリマーは、以下の方法で合成される。例え
ば，フェニルトリクロルシラン５２．９ｇとビニルトリ
クロルシラン２４．２ｇとをメチルイソブチルケトン中
で加水分解を行う。次に発生する酸を水洗により除き中
和した後，０．２５ｇの水酸化カリュ−ムを触媒として
用い，還流下脱水縮合反応を２０時間行う。得られた反
応物を溶解再沈法で精製する。The photopolymerizable silicone ladder polymer having a hydroxyl group is synthesized by the following method. For example, 52.9 g of phenyltrichlorosilane and 24.2 g of vinyltrichlorosilane are hydrolyzed in methyl isobutyl ketone. Next, the generated acid is removed by washing with water and neutralized, and then a dehydration condensation reaction is carried out for 20 hours under reflux using 0.25 g of potassium hydroxide as a catalyst. The obtained reaction product is purified by the dissolution reprecipitation method.

【００３９】実施例６．光重合性のシリコーンラダーポ
リマーとして下記化学式（４）で示す末端に感光基を有
するものを用いた（２０．０重量％濃度に調整、増感剤
としてビスアジド化合物を約３％含む）以外は実施例５
と同様にして、ＷＦ6 を含む原料ガスを用いたＣＶＤ法
によりタングステン７を形成した。この時、いかなる条
件においても第１の金属配線３上のみにタングステンが
形成され、シリコーンラダーポリマー膜５ｃ上には全く
成長しなかった。Example 6. Other than using a photopolymerizable silicone ladder polymer having a photosensitive group at the terminal represented by the following chemical formula (4) (adjusted to a concentration of 20.0% by weight, containing about 3% of a bisazide compound as a sensitizer) Example 5
In the same manner as above, tungsten 7 was formed by the CVD method using the source gas containing WF 6 . At this time, under any condition, tungsten was formed only on the first metal wiring 3 and did not grow at all on the silicone ladder polymer film 5c.

【００４０】[0040]

【化５】 [Chemical 5]

【００４１】なお、本実施例で用いられる光重合性のシ
リコーンラダーポリマーは、例えば特公平２−１５８６
４号広報に記載されている方法で合成されたものであ
る。The photopolymerizable silicone ladder polymer used in this example is, for example, Japanese Patent Publication No. 2-1586.
It was synthesized by the method described in No. 4 Public Relations.

【００４２】実施例７．図１３は本発明の第２の実施例
の半導体装置を示す断面モデル図である。第１の実施例
では層間絶縁膜５としてシリコン酸化膜５ａとシリコー
ンラダーポリマー膜等の樹脂膜５ｂ，５ｃとの２層膜か
らなるものについて示したが、この第２の実施例では層
間絶縁膜５をシリコーンラダーポリマー膜等の樹脂膜５
ｂ，５ｃのみで形成している。Example 7. FIG. 13 is a sectional model view showing a semiconductor device according to a second embodiment of the present invention. In the first embodiment, the interlayer insulating film 5 is a two-layer film including the silicon oxide film 5a and the resin films 5b and 5c such as a silicone ladder polymer film. However, in the second embodiment, the interlayer insulating film 5 is formed. 5 is a resin film 5 such as a silicone ladder polymer film
It is formed only by b and 5c.

【００４３】以下、この第２の実施例の製造方法につい
てシリコーンラダーポリマー膜を例に説明する。第１の
金属配線３を形成するところまでは上記実施例と同様で
ある。次に、第１の金属配線３上に、上記化学式（２）
で示されるシリコーンラダーポリマー溶液（１５重量％
の濃度に調整されている）を回転塗布し、１μｍの膜を
形成し、その後、実施例４と同様の熱処理を行い、シリ
コーンラダーポリマー膜５ｂとする。The manufacturing method of the second embodiment will be described below by taking a silicone ladder polymer film as an example. The process up to the point where the first metal wiring 3 is formed is the same as in the above embodiment. Next, on the first metal wiring 3, the above chemical formula (2)
Silicone ladder polymer solution (15 wt%
Is adjusted to a concentration of 1) to form a 1 μm film, and then the same heat treatment as in Example 4 is performed to obtain the silicone ladder polymer film 5b.

【００４４】次に上記実施例と同様にしてコンタクト孔
を形成し、ＷＦ6を含む原料ガスを用いたＣＶＤ法によ
りタングステン７をコンタクト孔に埋め込んだ。このと
き上記実施例と同様、いかなるＣＶＤ条件においても第
１の金属配線３上のみにタングステン７が形成され、シ
リコーンラダーポリマー膜５ｂ上には全く成長しなかっ
た。さらに、同様に、第２の金属配線８を形成し、層間
をコンタクト孔（タングステン７）を介して導通させ
た。このような第２の実施例においても、第１の実施例
と同様の効果を示した。Next, contact holes were formed in the same manner as in the above embodiment, and tungsten 7 was buried in the contact holes by the CVD method using the raw material gas containing WF 6 . At this time, similarly to the above-mentioned embodiment, under any CVD condition, the tungsten 7 was formed only on the first metal wiring 3 and did not grow at all on the silicone ladder polymer film 5b. Further, similarly, the second metal wiring 8 was formed, and the layers were electrically connected via the contact hole (tungsten 7). Also in such a second embodiment, the same effect as that of the first embodiment was shown.

【００４５】実施例８．第１の金属配線３上に実施例５
と同様の化学式（３）で示される光重合性のシリコーン
ラダーポリマー溶液（１５重量％の濃度に調整され，増
感剤としてビスアジド化合物を約３％含む）を回転塗布
し、１．５μｍの膜を形成し、光重合性のシリコーンラ
ダーポリマー膜５ｃ単層からなる層間絶縁膜を形成し
た。次に実施例５と同様にして、シリコーンラダーポリ
マー膜５ｃに所定のパターンを形成する。そして、ＷＦ
6 を含む原料ガスを用いたＣＶＤ法によりタングステン
７をコンタクト孔に埋め込んだ。この場合も上記実施例
と同様、いかなるＣＶＤ条件においても第１の金属配線
３上のみにタングステン７が形成され、シリコーンラダ
ーポリマー膜５ｃ上には全く成長しなかった。さらに、
同様に、第２の金属配線８を形成し、層間をコンタクト
孔（タングステン７）を介して導通させた。Example 8. Example 5 on the first metal wiring 3
A photopolymerizable silicone ladder polymer solution represented by the same chemical formula (3) (adjusted to a concentration of 15% by weight and containing about 3% of a bisazide compound as a sensitizer) is spin-coated to form a 1.5 μm film. Then, an interlayer insulating film composed of a single layer of the photopolymerizable silicone ladder polymer film 5c was formed. Then, in the same manner as in Example 5, a predetermined pattern is formed on the silicone ladder polymer film 5c. And WF
Tungsten 7 was embedded in the contact hole by a CVD method using a source gas containing 6 . Also in this case, similarly to the above-mentioned embodiment, tungsten 7 was formed only on the first metal wiring 3 under any CVD condition and did not grow at all on the silicone ladder polymer film 5c. further,
Similarly, the second metal wiring 8 was formed and the layers were electrically connected via the contact hole (tungsten 7).

【００４６】実施例９．図１４（ａ）〜（ｃ）はそれぞ
れ本発明の第３の実施例に係わる半導体装置の製造方法
を工程順に示す断面モデル図である。５ｂ’は膜５ｂの
表面をタングステン７が突出るようにエッチングしたシ
リコーンラダーポリマー膜である。次に、第３の実施例
の製造方法について説明する。タングステン７をコンタ
クト孔に埋め込むところまで（図１４(ａ)）は、第１の
実施例と同様である。次にシリコーンラダーポリマー膜
５ｂを、例えばコンタクト孔を開孔するときと同じエッ
チング条件で表面をエッチングし、シリコーンラダーポ
リマー膜５ｂの膜厚を減らす（シリコーンラダーポリマ
ー膜５ｂ’）。これによりタングステン７はシリコーン
ラダーポリマー膜５ｂ’より突出した形となる（図１４
(ｂ)）。次に第２の金属配線８をスパッタリング、およ
びフォトリソグラフィ技術で作製する（図１４(ｃ)）。Example 9. 14A to 14C are cross-sectional model diagrams showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. 5b 'is a silicone ladder polymer film in which the surface of the film 5b is etched so that the tungsten 7 is projected. Next, a manufacturing method of the third embodiment will be described. The process up to the step of filling the contact hole with the tungsten 7 (FIG. 14A) is the same as in the first embodiment. Next, the surface of the silicone ladder polymer film 5b is etched, for example, under the same etching conditions as when opening the contact hole to reduce the thickness of the silicone ladder polymer film 5b (silicone ladder polymer film 5b '). As a result, the tungsten 7 has a shape protruding from the silicone ladder polymer film 5b '(FIG. 14).
(b)). Next, the second metal wiring 8 is formed by sputtering and photolithography technique (FIG. 14C).

【００４７】このように第３の実施例では、上述の第
１，第２の実施例と同様の効果があるとともに、タング
ステン７が第２の金属配線８に入り込んだ構造であるた
め、タングステン７と第２の金属配線８との接続を完全
にでき、タングステン７と第２の金属配線８との接触表
面積が増えることで抵抗が下がり、より信頼性のある配
線層を持つ半導体装置を得ることができる。As described above, the third embodiment has the same effects as those of the above-described first and second embodiments, and since the tungsten 7 has a structure in which it enters the second metal wiring 8, the tungsten 7 And the second metal wiring 8 can be completely connected to each other, and the contact surface area between the tungsten 7 and the second metal wiring 8 is increased, whereby the resistance is reduced and a semiconductor device having a more reliable wiring layer is obtained. You can

【００４８】実施例１０．図１５〜図２１はそれぞれ、
本発明の半導体装置の製造方法の一実施例を工程順に示
す断面モデル図である。各図において、従来と同一符号
は同一のものである。９はマスク材のシリコーンラダー
ポリマー膜である。Example 10. 15 to 21 respectively,
FIG. 7 is a cross-sectional model view showing an embodiment of the method for manufacturing the semiconductor device of the present invention in the order of steps. In each drawing, the same reference numerals as those used in the related art are the same. 9 is a silicone ladder polymer film as a mask material.

【００４９】従来の場合と同様にしてシリコン酸化膜４
まで形成した（図１５）。次に、上記化学式（２）で示
される、重量平均分子量が１０万であるシリコーンラダ
ーポリマーのアニソール溶液（５重量％の濃度に調整さ
れた）を回転塗布し、０．２μｍのシリコーンラダーポ
リマー膜９を形成し、１５０℃で３０分間と３５０℃で
６０分間の熱処理を行い熱硬化させた（図１６）。As in the conventional case, the silicon oxide film 4 is formed.
Formed (FIG. 15). Next, an anisole solution of a silicone ladder polymer having a weight average molecular weight of 100,000 (adjusted to a concentration of 5% by weight) represented by the above chemical formula (2) was spin-coated, and a 0.2 μm silicone ladder polymer film was formed. 9 was formed and heat-treated at 150 ° C. for 30 minutes and at 350 ° C. for 60 minutes to be thermally cured (FIG. 16).

【００５０】次に従来と同様にしてフォトレジスト６を
コンタクト孔にあわせてパターン形成し（図１７）、従
来と同様にフォトレジスト６を除去し、シリコン酸化膜
４をエッチングする方法で、たとえば、ＣＨＦ3 と酸素
の混合ガスのプラズマエッチングによりコンタクト孔を
形成する。このとき絶縁膜４とシリコーンラダーポリマ
ー膜９の２層を１つのエッチングプロセスによって同時
開孔することができる（図１８）。その後、従来と同様
にして、例えば、ＷＦ6 を含む原料ガスを用いたＣＶＤ
法によりタングステン７をシリコン酸化膜４の高さと同
じになるように形成した。このとき、いかなるＣＶＤ条
件においても第１の金属配線３上のみにタングステン７
が形成され、シリコーンラダーポリマー膜９上には全く
成長しなかった（図１９）。次に従来技術と同様にし
て、シリコン酸化膜４をエッチングする方法で、たとえ
ば、ＣＨＦ3 と酸素の混合ガスのプラズマエッチングに
よりシリコーンラダーポリマー膜９を除去した（図２
０）。さらに、従来の場合と同様に、タングステン７と
コンタクトをとるようにＡｌＳｉ合金からなる第２の金
属配線８を、スパッタリング、及びフォトリソグラフィ
技術で作製した（図２１）。Next, the photoresist 6 is patterned in accordance with the contact holes in the same manner as in the prior art (FIG. 17), the photoresist 6 is removed and the silicon oxide film 4 is etched in the same manner as in the prior art. Contact holes are formed by plasma etching with a mixed gas of CHF 3 and oxygen. At this time, two layers of the insulating film 4 and the silicone ladder polymer film 9 can be simultaneously opened by one etching process (FIG. 18). After that, as in the conventional method, for example, CVD using a source gas containing WF 6 is performed.
The tungsten 7 was formed by the same method as the height of the silicon oxide film 4. At this time, under any CVD condition, tungsten 7 is formed only on the first metal wiring 3.
Was formed and did not grow at all on the silicone ladder polymer film 9 (FIG. 19). Then, in the same manner as in the conventional technique, the silicon ladder polymer film 9 is removed by a method of etching the silicon oxide film 4, for example, by plasma etching of a mixed gas of CHF 3 and oxygen (FIG. 2).
0). Further, similarly to the conventional case, the second metal wiring 8 made of an AlSi alloy was formed by sputtering and photolithography so as to make contact with the tungsten 7 (FIG. 21).

【００５１】この実施例の製造方法においても、マスク
材としてリコーンラダーポリマー膜９を用い、シリコン
酸化膜４を被ったので、タングステン７をＣＶＤ法によ
り形成するとき、いかなる条件下でもコンタクト孔にの
みタングステンを埋め込むことができので、電気抵抗が
低いタングステンのＣＶＤ条件を選ぶことができる。ま
た、層間絶縁膜上にタングステンが析出しないので、エ
ッチバックする必要もない等、上記実施例と同様の効果
を奏する。。Also in the manufacturing method of this embodiment, since the silicon ladder film 9 is used as the mask material and the silicon oxide film 4 is covered, when the tungsten 7 is formed by the CVD method, only the contact hole is formed under any condition. Since tungsten can be embedded, it is possible to select a CVD condition for tungsten having a low electric resistance. Further, since tungsten is not deposited on the interlayer insulating film, there is no need to etch back, and the same effects as those of the above-described embodiment can be obtained. ..

【００５２】実施例１１．本発明の製造方法の他の実施
例を図２２（ａ）（ｂ）を用いて説明する。シリコン酸
化膜４上にシリコーンラダーポリマー膜８を形成した後
コンタクト孔を形成するところまでは上記実施例１０と
全く同様である。実施例１０ではタングステン７をシリ
コン酸化膜４と同じ高さになるように形成したが、この
実施例では、シリコーンラダーポリマー膜９と同じ高さ
になるように形成した。このときも、いかなるＣＶＤ条
件においても第１の金属配線３上のみにタングステン７
が形成され、シリコーンラダーポリマー膜９上には全く
成長しなかった。さらに、実施例１０と同様にシリコー
ンラダーポリマー膜９を図２２（ａ）のように除去した
後、図２２（ｂ）のように実施例１０と同様に第２の金
属配線８を形成し、層間をコンタクト孔（タングステン
７）を介して導通させた。Example 11. Another embodiment of the manufacturing method of the present invention will be described with reference to FIGS. The procedure is exactly the same as that of Example 10 above until the contact hole is formed after the silicone ladder polymer film 8 is formed on the silicon oxide film 4. In Example 10, the tungsten 7 was formed so as to have the same height as the silicon oxide film 4, but in this example, it was formed so as to have the same height as the silicone ladder polymer film 9. At this time, tungsten 7 is formed only on the first metal wiring 3 under any CVD condition.
Was formed and did not grow at all on the silicone ladder polymer film 9. Further, after removing the silicone ladder polymer film 9 as shown in FIG. 22A as in the case of Example 10, the second metal wiring 8 is formed as in Example 10 as shown in FIG. 22B. The layers were electrically connected via a contact hole (tungsten 7).

【００５３】この実施例では、タングステン７を層間絶
縁膜４より突出させて形成したので、実施例１０の効果
に加えて第２の金属配線８とタングステン７とのコンタ
クトがより確実となる効果がある。In this embodiment, since the tungsten 7 is formed so as to protrude from the interlayer insulating film 4, in addition to the effect of the tenth embodiment, there is an effect that the contact between the second metal wiring 8 and the tungsten 7 becomes more reliable. is there.

【００５４】実施例１２．本発明の実施例１２を図１５
〜図２１を参考にして説明する。図１５に示すようにシ
リコン酸化膜４を形成するまでは上記実施例の場合と全
く同様である。次に上記化学式（３）で示される、重量
平均分子量が１０万であるシリコーンラダーポリマーの
アニソール溶液（５重量％の濃度に調整された）を回転
塗布し、マスク材として０．２μｍのシリコーンラダー
ポリマー膜９を形成した。次に、１５０℃で３０分間乾
燥を行った（図１６）。次に実施例１０と同様にしてフ
ォトレジスト７をコンタクト孔にあわせてパターン形成
し（図１７）、フォトレジスト７を除去し、シリコン酸
化膜４をエッチングする方法で、例えば、ＣＨＦ3 と酸
素の混合ガスのプラズマエッチングによりコンタクト孔
を形成する。このとき絶縁膜４とシリコーンラダーポリ
マー膜９の２層を１つのエッチングプロセスによって同
時開孔することができる（図１８）。同様にして、ＷＦ
6 を含む原料ガスを用いたＣＶＤ法によりタングステン
７を層間絶縁膜４の高さと同じになるように形成した。
このとき、いかなるＣＶＤ条件においても第１の金属配
線３上のみにタングステンが形成され、シリコーンラダ
ーポリマー膜９上には全く成長しなかった（図１９）。
次に従来技術と同様にして、例えば、アニソールを用い
てウエットエッチングによりシリコーンラダーポリマー
膜９を除去した（図２０）。さらに、従来の場合と同様
に、タングステン７とコンタクトをとるようにＡｌＳｉ
合金からなる第２の金属配線８を、スパッタリング、お
よびフォトリソグラフィ技術で作製した（図２１）。Example 12. Embodiment 12 of the present invention is shown in FIG.
~ It demonstrates with reference to FIG. As shown in FIG. 15, the process up to the formation of the silicon oxide film 4 is exactly the same as that in the above embodiment. Next, an anisole solution of a silicone ladder polymer having a weight average molecular weight of 100,000 (adjusted to a concentration of 5% by weight) represented by the above chemical formula (3) was spin-coated, and a 0.2 μm silicone ladder was used as a mask material. The polymer film 9 was formed. Next, it was dried at 150 ° C. for 30 minutes (FIG. 16). Next, the photoresist 7 is patterned in conformity with the contact holes (FIG. 17) in the same manner as in Example 10, the photoresist 7 is removed, and the silicon oxide film 4 is etched by, for example, CHF 3 and oxygen. Contact holes are formed by plasma etching of mixed gas. At this time, two layers of the insulating film 4 and the silicone ladder polymer film 9 can be simultaneously opened by one etching process (FIG. 18). Similarly, WF
Tungsten 7 was formed in the same height as the interlayer insulating film 4 by the CVD method using the raw material gas containing 6 .
At this time, under any CVD condition, tungsten was formed only on the first metal wiring 3 and did not grow at all on the silicone ladder polymer film 9 (FIG. 19).
Next, the silicone ladder polymer film 9 was removed by wet etching using, for example, anisole in the same manner as in the conventional technique (FIG. 20). Further, as in the conventional case, AlSi is formed so as to make contact with the tungsten 7.
The second metal wiring 8 made of an alloy was produced by sputtering and photolithography technology (FIG. 21).

【００５５】この実施例では、シリコーンラダーポリマ
ーの回転塗布膜９として未硬化膜を用いたので、実施例
１０の効果に加えてウエットエッチングによりシリコー
ンラダーポリマー膜９を簡単に除去できる効果がある。In this embodiment, since the uncured film is used as the spin coating film 9 of the silicone ladder polymer, the silicone ladder polymer film 9 can be easily removed by wet etching in addition to the effect of the tenth embodiment.

【００５６】実施例１３．本発明の実施例１３を図１５
〜図２１を参考にして説明する。図１５に示すようにシ
リコン酸化膜４を形成するのは実施例１０の場合と全く
同様である。次に上記化学式（１）で示され末端に感光
基を有する、重量平均分子量が１０万であるシリコーン
ラダーポリマーのアニソール溶液（５重量％の濃度に調
整された）を回転塗布し、マスク材として０．２μｍの
光重合性のシリコーンラダーポリマー膜９を形成した
後、１５０℃で３０分間乾燥を行った（図１６）。次に
シリコーンラダーポリマー膜９をコンタクト孔にあわせ
てパターン形成し、実施例１０と同様に、シリコン酸化
膜４をエッチングする方法で、例えばＣＨＦ3 と酸素の
混合ガスのプラズマエッチングによりコンタクト孔を形
成した（図１８）。次に従来と同様にして、例えばＷＦ
6 を含む原料ガスを用いたＣＶＤ法によりタングステン
７をシリコン酸化膜４の高さと同じになるように形成し
た。このとき、いかなるＣＶＤ条件においても第１の金
属配線３上のみにタングステンが形成され、シリコーン
ラダーポリマー膜９上には全く成長しなかった（図１
９）。さらに、実施例１０と同様にシリコーンラダーポ
リマー膜９を図２０のように除去し、タングステン７と
コンタクトをとるように第２の金属配線８を作製した
（図２１）。Example 13 Example 13 of the present invention is shown in FIG.
~ It demonstrates with reference to FIG. The formation of the silicon oxide film 4 as shown in FIG. 15 is exactly the same as in the case of the tenth embodiment. Next, an anisole solution of a silicone ladder polymer having a photosensitive group at the terminal and represented by the above chemical formula (1) and having a weight average molecular weight of 100,000 (adjusted to a concentration of 5% by weight) was spin-coated to prepare a mask material. After forming a photopolymerizable silicone ladder polymer film 9 having a thickness of 0.2 μm, it was dried at 150 ° C. for 30 minutes (FIG. 16). Next, the silicone ladder polymer film 9 is patterned according to the contact hole, and the silicon oxide film 4 is etched in the same manner as in Example 10, for example, by plasma etching using a mixed gas of CHF 3 and oxygen to form the contact hole. (FIG. 18). Next, in the same manner as in the conventional method, for example, WF
Tungsten 7 was formed to have the same height as the silicon oxide film 4 by a CVD method using a raw material gas containing 6 . At this time, under any CVD condition, tungsten was formed only on the first metal wiring 3 and did not grow on the silicone ladder polymer film 9 (FIG. 1).
9). Further, as in Example 10, the silicone ladder polymer film 9 was removed as shown in FIG. 20, and the second metal wiring 8 was formed so as to make contact with the tungsten 7 (FIG. 21).

【００５７】この実施例では、光重合性のシリコーンラ
ダーポリマー膜を用いたので、実施例１０の効果に加え
て、フォトレジストが不要となり、製造工程を削減でき
る効果がある。In this embodiment, since the photopolymerizable silicone ladder polymer film is used, in addition to the effect of the embodiment 10, there is an effect that the photoresist is unnecessary and the manufacturing process can be reduced.

【００５８】比較例１．本発明では、マスク材として層
間絶縁膜４の最上層にシリコーンラダーポリマー膜９を
形成して用いたが、レジスト等の有機物を層間絶縁膜４
の最上層に適用した例を示し、問題点を実施例と比較し
て述べる。まず、耐熱性は本発明に用いたポリマーに比
べ、非常に劣る。従って、プロセスにおいて特にコンタ
クト孔を形成するとき大きな問題が生じる。つまり、Ｃ
ＶＤ法により第１と第２の金属配線３，８をコンタクト
させる金属層７を形成するときに、大きな問題が生じ
る。即ちＣＶＤ法によるコンタクト孔の埋め込みは約３
００℃という温度で行われるため、レジスト等の非耐熱
性の有機物では揮発や熱分解によりＣＶＤ装置のチャン
バー内やデバイス自体が汚染される。Comparative Example 1. In the present invention, the silicone ladder polymer film 9 is formed on the uppermost layer of the interlayer insulating film 4 as a mask material, but an organic substance such as a resist is used as the interlayer insulating film 4.
An example applied to the uppermost layer of is shown, and the problems will be described in comparison with the examples. First, the heat resistance is extremely inferior to the polymer used in the present invention. Therefore, a big problem arises in the process especially when forming the contact hole. That is, C
A great problem occurs when the metal layer 7 for contacting the first and second metal wirings 3 and 8 is formed by the VD method. That is, the filling of the contact hole by the CVD method is about 3
Since it is performed at a temperature of 00 ° C., non-heat-resistant organic substances such as resists contaminate the inside of the chamber of the CVD apparatus and the device itself due to volatilization and thermal decomposition.

【００５９】本発明に係わる樹脂膜としては、不純物イ
オン濃度が低く高純度であり，かつ製造プロセス上の熱
処理温度に耐える耐熱性を有していれば、どのような樹
脂でもよく、シリコ−ンラダ−ポリマ−，ポリイミド樹
脂，フッ素系樹脂，シクロブテン樹脂などが用いられ
る。As the resin film according to the present invention, any resin may be used as long as it has a low impurity ion concentration, high purity, and heat resistance to withstand the heat treatment temperature in the manufacturing process. -Polymer, polyimide resin, fluorine resin, cyclobutene resin, etc. are used.

【００６０】シリコーンラダーポリマー膜としては、上
記実施例では上記化学式（２）で示されるシリコーンラ
ダーポリマーを用いたが、上記化学式（１）に示され
る、例えばポリフェニルシルセスキオキサン、ポリフェ
ニルメチルシルセスキオキサン、ポリビニルシルセスキ
オキサン、ポリアリールシルセスキオキサン等のうちの
少なくとも１種が用いられる。As the silicone ladder polymer film, the silicone ladder polymer represented by the above chemical formula (2) was used in the above-mentioned embodiment. For example, polyphenylsilsesquioxane or polyphenylmethyl is represented by the above chemical formula (1). At least one of silsesquioxane, polyvinyl silsesquioxane, polyaryl silsesquioxane, etc. is used.

【００６１】また、光重合性のシリコーンラダーポリマ
ーとしては、上記実施例では上記化学式（３）（４）で
示されるシリコーンラダーポリマーを用いたが、上記化
学式（１）で示される、例えばポリフェニルビニルシル
セスキオキサン、ポリメチルビニルシルセスキオキサ
ン、ポリイソブチルビニルシルセスキオキサン，及びポ
リフェニルアリールシルセスキオキサン，ポリメチルア
リ−ルシルセスキオキサン，ポリイソブチルアリ−ルシ
ルセスキオキサンなどのうちの少なくとも１種が用いら
れるが、これらに限定されるものではなく、感光性でさ
えあればよい。As the photopolymerizable silicone ladder polymer, the silicone ladder polymers represented by the above chemical formulas (3) and (4) were used in the above-mentioned examples. For example, polyphenylene represented by the above chemical formula (1) was used. Of vinylsilsesquioxane, polymethylvinylsilsesquioxane, polyisobutylvinylsilsesquioxane, and polyphenylarylsilsesquioxane, polymethylarylsilsesquioxane, polyisobutylarylsilsesquioxane, etc. At least one kind is used, but it is not limited to these and may be photosensitive.

【００６２】ポリイミド樹脂膜としては、日立化成(株)
より市販されているＰＩＸ，ＰＩＱなどの樹脂が使用さ
れる。フッソ系樹脂膜としては、旭硝子(株)より市販さ
れているサイトップなどの樹脂が使用される。シクロブ
テン系の樹脂膜としては、ＤＯＷ ＣＨＥＭＩＣＡＬ社
のＢＣＢなどの樹脂膜が使用される。As the polyimide resin film, Hitachi Chemical Co., Ltd.
More commercially available resins such as PIX and PIQ are used. As the fluorine-based resin film, a resin such as CYTOP sold by Asahi Glass Co., Ltd. is used. As the cyclobutene-based resin film, a resin film such as BCB manufactured by DOW CHEMICAL is used.

【００６３】なお、上記実施例では、金属層７、即ちコ
ンタクト孔を埋め込む金属としてタングステンを用いた
場合を示したが、これに限るものではなく、モリブデ
ン、チタン、イリジウム、バナジウム、クロム、オスミ
ウム等の他の金属であってもよく、さらにこれらの合金
であってもよい。またさらにそれらの珪化物であっても
よい。In the above embodiment, the case where tungsten is used as the metal for filling the metal layer 7, that is, the contact hole is shown, but the present invention is not limited to this, and molybdenum, titanium, iridium, vanadium, chromium, osmium, etc. Other metals may be used, and alloys thereof may be used. Further, it may be a silicide thereof.

【００６４】また、上記実施例では２層の配線の場合の
例を示したが、３層以上の配線の場合にも適用できるの
はいうまでもない。In the above embodiment, the example of the wiring of two layers is shown, but it is needless to say that it is applicable to the wiring of three layers or more.

【００６５】[0065]

【発明の効果】以上のように、本発明によれば、半導体
基板上に形成される第１、第２の金属配線間に介在して
形成される層間絶縁膜の少なくとも最上層部を樹脂膜と
したので、上記第１の金属配線と第２の金属配線とをコ
ンタクトさせる金属層をＣＶＤ法により形成する際に、
いかなる条件下でも層間絶縁膜上には成長せず、層間絶
縁膜に開けたコンタクト孔にのみ金属を埋め込むことが
でき、層間絶縁膜上に金属が析出しないので、配線間シ
ョートを引き起こすことがなく、また電気抵抗が低い金
属のＣＶＤ条件を選ぶことができるので配線の抵抗が低
い高性能の半導体装置が得られる効果がある。エッチバ
ックする必要もなく、コスト低減が図れる。As described above, according to the present invention, at least the uppermost layer portion of the interlayer insulating film formed between the first and second metal wirings formed on the semiconductor substrate is covered with the resin film. Therefore, when the metal layer for contacting the first metal wiring and the second metal wiring is formed by the CVD method,
It does not grow on the interlayer insulating film under any conditions, and the metal can be embedded only in the contact hole formed in the interlayer insulating film, and the metal is not deposited on the interlayer insulating film, so that no short circuit occurs between wirings. Further, since it is possible to select a CVD condition for a metal having a low electric resistance, it is possible to obtain a high-performance semiconductor device having a low wiring resistance. Cost reduction can be achieved without the need to etch back.

【００６６】また、樹脂膜としてシリコーンラダーポリ
マーの硬化膜を用いたので、この膜は平坦性が良好であ
るので、その上に形成した第２の金属配線が断線する心
配もなく、信頼性の高い半導体装置が得られる。Further, since a cured film of a silicone ladder polymer is used as the resin film, this film has good flatness, so that there is no concern that the second metal wiring formed thereon will be broken, and the reliability can be improved. A high semiconductor device can be obtained.

【００６７】さらに、光重合性のシリコーンラダーポリ
マー膜を用いたので、フォトレジストが不要となり、製
造工程を削減できる。Furthermore, since a photopolymerizable silicone ladder polymer film is used, a photoresist is not required and the manufacturing process can be reduced.

【００６８】そして、第１と第２の金属配線をコンタク
トさせる金属層を、シリコーンラダーポリマー膜をマス
ク材としてＣＶＤ法によって金属を層間絶縁膜に開けた
孔に埋め込むことによって形成するようにしたので、第
１と第２の金属配線をコンタクトさせる金属層をＣＶＤ
法により形成するとき、コンタクト孔にのみ成長し、シ
リコーンポリマー膜上には全く成長しない。従って、配
線の抵抗が低い高性能の半導体装置を製造できる効果が
ある。また、コンタクト孔部分以外には全く金属が形成
しないので、エッチバックにより除去する必要もなく、
コストの低減が図れる。The metal layer for contacting the first and second metal wirings is formed by burying the metal in the hole formed in the interlayer insulating film by the CVD method using the silicone ladder polymer film as a mask material. , CVD a metal layer contacting the first and second metal lines
When formed by the method, it grows only in the contact hole and does not grow at all on the silicone polymer film. Therefore, there is an effect that a high-performance semiconductor device having a low wiring resistance can be manufactured. In addition, since no metal is formed except in the contact hole portion, it is not necessary to remove it by etching back,
The cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 1 is a sectional model view showing a step of an example of a semiconductor device and a method of manufacturing the same according to a first exemplary embodiment of the present invention.

【図２】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 2 is a cross-sectional model view showing a step of an example of a semiconductor device and a manufacturing method thereof according to the first embodiment of the present invention.

【図３】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 3 is a sectional model view showing a step of an example of the semiconductor device of the first embodiment of the present invention and the manufacturing method thereof.

【図４】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 4 is a cross-sectional model view showing a step of an example of the semiconductor device and the manufacturing method thereof in the first embodiment of the present invention.

【図５】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 5 is a cross-sectional model view showing a step of an example of the semiconductor device of the first embodiment of the present invention and its manufacturing method.

【図６】本発明の第１の実施例の半導体装置、その製造
方法の一例の一工程を示す断面モデル図である。FIG. 6 is a cross-sectional model view showing a step of an example of the semiconductor device of the first embodiment of the present invention and the manufacturing method thereof.

【図７】本発明の第１の実施例の半導体装置、その製造
方法の他の例の一工程を示す断面モデル図である。FIG. 7 is a sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図８】本発明の第１の実施例の半導体装置、その製造
方法の他の例の一工程を示す断面モデル図である。FIG. 8 is a sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図９】本発明の第１の実施例の半導体装置、その製造
方法の他の例の一工程を示す断面モデル図である。FIG. 9 is a cross-sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図１０】本発明の第１の実施例の半導体装置、その製
造方法の他の例の一工程を示す断面モデル図である。FIG. 10 is a sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図１１】本発明の第１の実施例の半導体装置、その製
造方法の他の例の一工程を示す断面モデル図である。FIG. 11 is a sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図１２】本発明の第１の実施例の半導体装置、その製
造方法の他の例の一工程を示す断面モデル図である。FIG. 12 is a sectional model view showing a step of another example of the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention.

【図１３】本発明の第２の実施例の半導体装置を示す断
面モデル図である。FIG. 13 is a sectional model view showing a semiconductor device according to a second embodiment of the present invention.

【図１４】本発明の第３の実施例の半導体装置、その製
造方法を工程順に示す断面モデル図である。FIG. 14 is a sectional model view showing a semiconductor device according to a third embodiment of the present invention and a manufacturing method thereof in the order of steps.

【図１５】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 15 is a sectional model view showing a step of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

【図１６】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 16 is a sectional model view showing a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図１７】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 17 is a sectional model view showing a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図１８】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 18 is a sectional model view showing a step of the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図１９】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 19 is a sectional model view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図２０】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 20 is a cross-sectional model view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図２１】本発明の一実施例の半導体装置の製造方法の
一工程を示す断面モデル図である。FIG. 21 is a sectional model view showing a step in the method of manufacturing the semiconductor device according to the embodiment of the present invention.

【図２２】本発明の他の実施例の半導体装置の製造方法
を工程順に示す断面モデル図である。FIG. 22 is a sectional model view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention in the order of steps.

【図２３】従来の半導体装置の製造方法を工程順に示す
断面モデル図である。FIG. 23 is a sectional model view showing the method of manufacturing the conventional semiconductor device in the order of steps.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ 絶縁膜であるシリコン酸化膜 ３ 第１の金属配線 ４ 層間絶縁膜 ５ 層間絶縁膜 ５ａ 層間絶縁膜を構成するシリコン酸化膜 ５ｂ 層間絶縁膜を構成する樹脂膜 ５ｃ 層間絶縁膜を構成する光重合性のシリコーンラダ
ーポリマー膜 ７ 金属層であるタングステン ８ 第２の金属配線 ９ マスク材であるシリコーンラダーポリマー膜DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film which is an insulating film 3 First metal wiring 4 Interlayer insulating film 5 Interlayer insulating film 5a Silicon oxide film 5b which constitutes the interlayer insulating film 5b Resin film 5c which constitutes the interlayer insulating film 5c Interlayer insulating film is constituted Photopolymerizable silicone ladder polymer film 7 Tungsten that is a metal layer 8 Second metal wiring 9 Silicone ladder polymer film that is a mask material

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【手続補正書】[Procedure amendment]

【提出日】平成３年１２月６日[Submission date] December 6, 1991

【手続補正１】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項２[Name of item to be corrected] Claim 2

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【化１】 [Chemical 1]

【手続補正２】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】請求項３[Name of item to be corrected] Claim 3

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【手続補正３】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００１５[Correction target item name] 0015

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【００１５】また、樹脂膜には下記化学式（１）で示さ
れるシリコーンラダーポリマーを用いる。Further, the resin film and silicone ladder polymer over represented by the following chemical formula (1).

【手続補正４】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００１７[Correction target item name] 0017

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【００１７】さらに、シリコーンラダーポリマーとして
光重合性のシリコーンラダーポリマーを用いる。Furthermore, use of the photopolymerizable silicone ladder polymer with a silicone ladder polymer over.

【手続補正５】[Procedure Amendment 5]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】００６６[Name of item to be corrected] 0066

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【００６６】また、樹脂膜としてシリコーンラダーポリ
マーを用いたので、この膜は平坦性が良好であるので、
その上に形成した第２の金属配線が断線する心配もな
く、信頼性の高い半導体装置が得られる。[0066] In addition, since a silicone ladder poly <br/> M a as a resin film, since the film has good flatness,
It is possible to obtain a highly reliable semiconductor device without fear of breaking the second metal wiring formed thereon.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小谷 秀夫 伊丹市瑞原４丁目１番地 三菱電機株式会 社エル・エス・アイ研究所内 (72)発明者 林出 吉生 伊丹市瑞原４丁目１番地 三菱電機株式会 社エル・エス・アイ研究所内 (72)発明者 堤 聡明 伊丹市瑞原４丁目１番地 三菱電機株式会 社エル・エス・アイ研究所内 (72)発明者 松浦 正純 伊丹市瑞原４丁目１番地 三菱電機株式会 社エル・エス・アイ研究所内 (72)発明者 石井 敦司 伊丹市瑞原４丁目１番地 三菱電機株式会 社エル・エス・アイ研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Otani Hideo Kotani 4-chome Mizuihara, Itami-shi El SII Research Institute (72) Inventor Yoshio Hayashi 4-chome Mizuhara Itami-shi Mitsubishi Electric (72) Inventor Satoshi Tsutsumi, 4-chome, Mizuhara, Itami-shi, Inc. (72) In-house, L-SRI Inc. (72) Masazumi Matsuura, 4-chome, Mizuhara, Itami-shi (72) (72) Inventor Atsushi Ishii, 4-chome, Mizuhara, Itami City, Mitsubishi Electric Corp. LSI Research Laboratory

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 素子が形成された半導体基板、この半導
体基板上に形成された絶縁膜、この絶縁膜上に形成され
る第１、第２の金属配線、この第１、第２の金属配線間
に介在して形成される層間絶縁膜、及びＣＶＤ法によっ
て上記層間絶縁膜に開けられたコンタクト孔中に埋め込
んで形成され、上記第１、第２の金属配線同士を電気的
に接続する金属層を備える半導体装置において，上記層
間絶縁膜の少なくとも最上層部が樹脂膜からなることを
特徴とする半導体装置。1. A semiconductor substrate having an element formed thereon, an insulating film formed on the semiconductor substrate, first and second metal wirings formed on the insulating film, and first and second metal wirings. An inter-layer insulating film interposed therebetween, and a metal that is formed by being buried in a contact hole formed in the inter-layer insulating film by a CVD method and electrically connects the first and second metal wirings to each other. A semiconductor device having layers, wherein at least the uppermost layer of the interlayer insulating film is made of a resin film. 【請求項２】 樹脂膜は下記化学式（１）で示されるシ
リコーンラダーポリマーの硬化膜であることを特徴とす
る請求項第１項記載の半導体装置。 【化１】 2. The semiconductor device according to claim 1, wherein the resin film is a cured film of a silicone ladder polymer represented by the following chemical formula (1). [Chemical 1] 【請求項３】 シリコーンラダーポリマーの硬化膜は光
重合性を有するものであることを特徴とする請求項第１
項または第２項記載の半導体装置。3. The cured film of the silicone ladder polymer has photopolymerizability.
Item 2. The semiconductor device according to Item 2. 【請求項４】 素子が形成された半導体基板に絶縁膜を
形成する工程、この絶縁膜上に第１の金属配線を形成す
る工程、この第１の金属配線上に層間絶縁膜を形成する
工程、この層間絶縁膜に開けられたコンタクト孔にＣＶ
Ｄ法により金属を埋め込み上記第１の金属配線と電気的
に接続する金属層を形成する工程、及び上記金属層と電
気的に接続する第２の金属配線を形成する工程を施す半
導体装置の製造方法において、上記化学式（１）で示さ
れるシリコーンラダーポリマー膜をマスク材としてＣＶ
Ｄ法によって上記金属を上記孔に埋め込むようにしたこ
とを特徴とする半導体装置の製造方法。4. A step of forming an insulating film on a semiconductor substrate having an element formed thereon, a step of forming a first metal wiring on the insulating film, and a step of forming an interlayer insulating film on the first metal wiring. , CV in the contact hole formed in this interlayer insulating film.
Manufacture of a semiconductor device including a step of filling a metal by the D method to form a metal layer electrically connected to the first metal wiring and a step of forming a second metal wiring electrically connected to the metal layer In the method, the silicone ladder polymer film represented by the chemical formula (1) is used as a mask material for CV.
A method of manufacturing a semiconductor device, wherein the metal is embedded in the hole by the D method.
JP3245673A 1991-06-06 1991-09-25 Semiconductor device and manufacture thereof Pending JPH0574963A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3245673A JPH0574963A (en) 1991-06-06 1991-09-25 Semiconductor device and manufacture thereof
DE4218495A DE4218495A1 (en) 1991-06-06 1992-06-04 Semiconductor device suitable for LSI - has 2nd metal wiring layer formed on metal film electrically connected to photoresist, selectively coated on 1st metal wiring above insulating layer
KR1019920009752A KR930001312A (en) 1991-06-06 1992-06-05 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP16395691 1991-06-06
JP16563191 1991-07-05
JP3-163956 1991-07-16
JP3-175417 1991-07-16
JP3-165631 1991-07-16
JP17541791 1991-07-16
JP3245673A JPH0574963A (en) 1991-06-06 1991-09-25 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0574963A true JPH0574963A (en) 1993-03-26

Family

ID=27473897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3245673A Pending JPH0574963A (en) 1991-06-06 1991-09-25 Semiconductor device and manufacture thereof

Country Status (3)

Country Link
JP (1) JPH0574963A (en)
KR (1) KR930001312A (en)
DE (1) DE4218495A1 (en)

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US6690084B1 (en) 1997-09-26 2004-02-10 Sanyo Electric Co., Ltd. Semiconductor device including insulation film and fabrication method thereof
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US6917110B2 (en) 2001-12-07 2005-07-12 Sanyo Electric Co., Ltd. Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer
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Also Published As

Publication number Publication date
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DE4218495A1 (en) 1992-12-10

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