JP2002170883A - Method for fabricating wiring structure for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fabrication method by which a fine wiring structure is formable without using dry etching or ashing process of a wiring trench for a multiple layer fine wiring in a semiconductor device, at the same time the simplification of wiring process, the improvement of wiring reliability, and cost reduction are achieved. SOLUTION: A desirable wiring trench is formed by ultra violet lithography using insulation film comprising essentially of polysilazane as an interlayer insulation film 404 with ultraviolet ray photoactivity. A desirable developing property is obtainable by carrying out simultaneously humidifying heating process by steam. The wiring trench becomes a fixed wiring 408 by being filled with Cu film 407 and carrying out CMP. An anti reflection and protection film 405 is used as a topcoat for ensuring the stability of the photoactive insulation film in air, and for suppressing multiple interferences in exposure. The used protection film 405 is removed at the same time, or before or later with development.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a method of manufacturing the same, and more particularly, to forming a wiring groove or a via hole in an interlayer insulating film and depositing a conductive film thereon.
Chemical mechanical polishing (CMP)
In addition, the present invention relates to a wiring structure using a so-called Damascene method, in which an excess conductive film is removed by a method such as an ining method, and a conductive film is buried in a wiring groove or a via hole, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, aluminum (Al) or Al alloy is used as a wiring material in an integrated circuit (IC), and a silicon oxide film (SiO 2) is used as an insulating film between wirings and between wiring layers.
₂ ) has been widely used. However, with the progress of miniaturization of large-scale integrated circuits (LSI), copper (Cu) is used as a wiring material in order to reduce wiring resistance in order to suppress and reduce signal transmission delay in wiring, and to reduce wiring resistance. In order to reduce capacitance, a silicon oxide film containing an organic substance having a low dielectric constant or vacancies has been used as an insulating film between wirings and between wiring layers. However, in the case of using a wiring containing Cu as a main component, diffusion of Cu in a silicon (Si) semiconductor layer or an insulating film such as SiO ₂ is faster than that of Al. In order to prevent the intrusion of Cu into the device portion and the deterioration of the withstand voltage between the wirings and to secure the reliability, it is necessary to form a barrier film around the Cu wiring to prevent the diffusion of the Cu.

In the formation of the wiring structure using Cu, simplification of the process and reduction of the process cost are required, and practical use of a dual damascene method and proposal of a photosensitive material have been made. ing. Hereinafter, a conventional wiring structure in which a lower surface and side surfaces of a Cu film are covered with a conductor film serving as a Cu diffusion prevention (barrier) film and a method of manufacturing the same will be described.

[Prior Art 1] A conventional method of manufacturing a wiring structure using a damascene method generally used now will be described with reference to FIG. FIG. 1 is a sectional view showing the steps of manufacturing the wiring structure in the order of steps.

A silicon oxide film 1 is formed on a silicon substrate 101.
02, a SiON film 103 and a silicon oxide film 104 are sequentially deposited (FIG. 1A), and a resist pattern 10 is formed thereon.
5 is formed [FIG. 1 (b)]. Then, the silicon oxide film 104 is etched by anisotropic etching using the resist pattern 105 as a mask.
5 is removed to form a wiring groove [FIG. 1 (c)].

Next, a Cu film 107 is formed on the entire surface after forming a barrier film 106 made of a conductor here (FIG. 1D). Excess Cu film 107 other than in the wiring groove or the via hole is removed by chemical mechanical polishing (CMP), and the excess barrier film 106 is similarly removed [FIG.
(E)]. Thereafter, a barrier film 108 made of an insulator is formed, so that the lower surface and the side surfaces of the barrier film 108 are conductors.
6, a Cu wiring structure whose upper surface is covered with the barrier film 108 made of an insulator is formed [FIG. 1 (f)]. The barrier film made of this conductor has a high Cu diffusion preventing ability,
Titanium (T) having a high melting point is used for reasons such as adhesion to the underlying insulator and the Cu wiring portion and thermal stability in the process.
i) a metal such as tantalum (Ta) or tungsten (W) and a nitride of the metal, or a ternary or quaternary nitride obtained by adding Si or the like to them, or a laminate of them Can be On the other hand, the insulating barrier film on the upper surface also has a high Cu diffusion preventing ability,
Silicon (Si) nitride (SiN) or carbide (SiC) or the like is used for reasons such as adhesion to a base insulating material and a Cu wiring portion and thermal stability in a process.

[Prior Art 2] Regarding a method of manufacturing a wiring structure using a dual damascene method generally used at present,
This will be described with reference to FIG. As shown in FIG. 2A, a silicon nitride film 201, a silicon oxide film 202, a SiON film 203,
A silicon oxide film 204 is sequentially deposited (FIG. 2B), and a resist pattern 205 corresponding to a via hole is formed thereon (FIG. 2C). And the resist pattern 20
Silicon oxide film 202, SiON film 203, silicon oxide film 204 by anisotropic etching using mask 5 as a mask.
Are sequentially etched, and the via hole 212 is formed by removing the resist pattern 205 [FIG.
(D)].

Next, a resist pattern (trench pattern) 206 corresponding to the wiring groove is formed on the via hole 212 (FIG. 2E), and the trench pattern 206 is used as a mask to correspond to the wiring groove 213 by anisotropic etching. The silicon oxide film 204 is removed. After removing the resist pattern 206, the via holes 21 are etched.
Then, the silicon nitride film 201 at the bottom of the substrate 2 is removed, thereby forming a via hole and a wiring groove in which Cu is exposed at the bottom [FIG. 2 (f)].

Next, a barrier film 207 made of a conductor is formed on the entire surface, and a Cu film 208 is formed [FIG.
(G)]. The surplus Cu film 208 other than in the wiring groove or the via hole is removed by CMP, the surplus barrier film 208 is similarly removed, and then a barrier film 209 made of an insulator is formed. C whose upper surface is covered with a barrier layer which is an insulating film by a barrier layer which is a conductor
The u wiring 211 is formed [FIG. 2 (h)].

[Prior Art 3] It has also been proposed to use a photosensitive material as an insulating film. With reference to FIG. 3, a description will be given of a currently proposed method of manufacturing a wiring structure in which a photosensitive material is applied to a damascene method.

First, a silicon oxide film 302 is deposited on a silicon substrate 301 (FIG. 3A), and then a photosensitive material is applied and baked to form a photosensitive insulating film 304.
Is formed [FIG. 3 (b)]. As the photosensitive insulating film 304, a material obtained by adding a positive photosensitive material to a base material using polyimide, polyamic acid, benzocyclobutene, polyoxybenzol (PBO) or the like as a substrate is used. Here, for example, as a positive photosensitive resin based on PBO, CRC83 manufactured by Sumitomo Bakelite Co., Ltd. is used.
The case where 00 (product name) is used will be described. As shown in FIG. 3C, in order to form a desired wiring groove, the photosensitive insulating film 304 is exposed to ultraviolet light to form a latent image. Here, on the photomask, a light-shielding film made of a metal film such as chromium (Cr) is formed at a predetermined position on a transparent substrate made of synthetic quartz or the like, and a wiring pattern is formed from the light-shielding portion and the transmitting portion. I have. Here, since a positive photosensitive resin is used, the photomask pattern is constituted by a transmission portion. Subsequently, a wiring groove made of a photosensitive resin is formed by performing development [FIG. 3D]. For the development, an alkaline aqueous solution developer is used. Next, in order to cure the resin layer in which the wiring groove is formed, the resin layer is heated at 150 ° C. for 30 minutes in a nitrogen atmosphere, and subsequently heated at a temperature of 310 ° C. to 320 ° C. for 30 minutes.

Thereafter, as shown in FIG. 3E, a barrier film 306 made of a conductor is formed on the resin layer 305 which has been cured and has lost the photosensitivity, and then a Cu film 307 is formed. 3 (f)]. Excess Cu film 307 other than in the wiring groove or the via hole is removed by CMP, and the excess barrier film 306 is similarly removed to form a damascene wiring (FIG. 3G).

A proposal for a wiring structure having a damascene-structured copper wiring using a photosensitive interlayer material is disclosed in, for example, JP-A-2000-138219.

[0014]

The above-mentioned conventional method has the following problems.

In the prior art 1, the dielectric constant of the interlayer film is required to be reduced, and the number of steps is increased, and the number of manufacturing apparatuses is increased, leading to an increase in cost.

When the prior art 2 is applied to a process of forming a damascene wiring in a low dielectric constant film, a wiring groove or a via hole for forming a wiring in the low dielectric constant film is formed by photolithography using a resist. It is formed using a processing technique using lithography and etching. However, etching and ashing (after etching) of a low dielectric constant film have many processing problems, and forming a fine wiring pattern requires many steps. In addition, the number of manufacturing apparatuses increases, leading to an increase in cost.

[0017] On the other hand, in the prior art 3, especially in JP-A-200
The technology disclosed in Japanese Patent Application No. 0-138219 uses an organic photosensitive material as an insulating film, thereby making the etching and ashing steps unnecessary. However, the organic photosensitive material described in the above-mentioned publication is firstly low in heat resistance, so that it cannot be applied as an interlayer insulating film when practical multilayer wiring is used, particularly when the wiring material is Cu. Was. Secondly, in those disclosed in these publications, a combination of a Cu barrier film and a photosensitive material is not assumed, so that in fine wiring, diffusion of Cu occurs between wirings, and wiring reliability is reduced. It is easily expected. Third, since patterning is performed by photolithography directly irradiating ultraviolet rays, it has been difficult to form a fine pattern. In particular, as shown in FIG. 11, a silicon oxide film 1102 and a SiON film 11 are formed on a silicon substrate 1101.
03. When the photosensitive interlayer film 1104 is sequentially deposited and exposed using ultraviolet rays, since the inorganic barrier film is interposed, the multiple interference due to reflection actually occurs on the groove side wall formed from the photosensitive interlayer film 1104. Occurs, and the standing wave is transferred to the groove side wall shape as it is. Therefore, there are problems in embedding the wiring material, wiring performance, and wiring reliability.

Japanese Patent Application Laid-Open No. 2000-181069 proposes the usefulness of using polysilazane as a photosensitive interlayer film. However, in the technology disclosed in this publication, similar to the above, actual multilayer wiring formation such as improvement of the reflection effect at the time of lithography, improvement of atmospheric stability of exposure conditions, improvement of heat resistance after firing, improvement of throughput, etc. It was not enough to apply to the process. In the photosensitive interlayer material disclosed in this publication, the Si—N bond of polysilazane is cleaved by light irradiation, and changes into silanol (Si—OH bond) by reaction with moisture in the atmosphere, and the silanol is converted into a developing solution. A pattern is formed by dissolving in As a specific problem, firstly, it is desirable to selectively promote the silanolation reaction in the exposed area, but it is difficult to effectively promote the solubility by the immersion treatment, and it is difficult to obtain good development characteristics. It was not easy to find the means and conditions for that. Secondly, it is desirable that the silanolation reaction of the exposed portion progresses during the humidification process. However, since the unexposed portion is silanolized by the moisture in the atmosphere during the atmospheric time, it is impossible to perform patterning of a desired size. Was. Third
However, simply heating the unexposed portion left unreacted Si-N bonds in the film, resulting in deterioration of the film quality, specifically, an increase in dielectric constant and a decrease in heat resistance. Fourth, in particular, in order to apply to a multilayer wiring using Cu as a wiring material, it is necessary to construct a practical multilayer wiring through process.

FIG. 12 shows the Fourier transform infrared (FT-IR) absorption spectrum of the polysilazane film used here. By leaving the film in the air (after leaving it for 60 minutes), even the unexposed portion can be obtained. It has been confirmed that the silanolation reaction proceeds.

Accordingly, an object of the present invention is to provide a wiring structure for forming a wiring such as a multilayer wiring by a damascene method using a photosensitive low dielectric constant material, and a method for manufacturing the same.

[0021]

A wiring structure according to the present invention is a wiring structure on a substrate on which a semiconductor element is formed. The wiring structure includes an insulating film formed on the substrate, a wiring groove formed on the insulating film, and a wiring groove formed on the insulating film. A wiring and a connection plug formed by filling a via hole with a metal wiring material containing copper as a main component, and the insulating film is formed of a material having photosensitivity to ultraviolet light. Here, the insulating film formed of a material having ultraviolet light sensitivity is an insulating film made of a substrate containing polysilazane as a main component.

In this wiring structure, it is possible to form a multilayer wiring in which a plurality of insulating films are stacked. In this case, it is preferable that a barrier insulating film is interposed between adjacent insulating films. In the case where a film composed of a substrate containing polysilazane as a main component is used as the insulating film, a film formed of at least one material selected from the group consisting of SiN, SiC, and SiCN is used as the barrier insulating film. Preferably, it is used.

The method of manufacturing a wiring structure according to the present invention basically comprises the steps of forming an insulating film having ultraviolet light sensitivity on a substrate on which a semiconductor element is formed and a lower wiring is formed thereon; A step of irradiating a predetermined region of the insulating film with ultraviolet light to expose the insulating film, and removing the exposed portion by developing the insulating film, thereby removing at least one or more of a wiring groove, a via hole, and a contact hole. And a developing step for opening the insulating film.

In the method of manufacturing a wiring structure according to the present invention, the insulating film is typically made of a substrate containing polysilazane as a main component. Further, according to the present invention, the metal wiring material is filled in the portion opened in the developing step.

In the present invention, in addition to the basic steps, (1) the insulating film is heated at a predetermined temperature between the step of forming an insulating film having ultraviolet light sensitivity and the step of exposing. Step, (2) between the step of exposing and the step of developing,
A step of simultaneously humidifying and heating the insulating film at a predetermined humidity and temperature to promote the solubility of the exposed portion; and (3) a predetermined temperature between the step of exposing and the step of simultaneously humidifying and heating. , One or more steps of heating the insulating film.

Further, according to the present invention, immediately after the step of forming an insulating film having photosensitivity to ultraviolet light, a protection function having a protection function for leaving in the air and a reflection (multiple interference) function for stabilizing the exposure, etc. It is preferable to form a film on the insulating film and remove the protective film at least before filling the metal wiring material. As the protective film, a water-soluble polymer film is preferably used.

Further, in the manufacturing method of the present invention, after the developing step, a step of irradiating ultraviolet rays, and a step of simultaneously humidifying and heating the insulating film at a predetermined humidity and temperature following the step of irradiating ultraviolet rays, It is preferable that a step of performing a curing treatment by heating is provided to reduce the photosensitivity, cure the insulating film, improve the heat resistance of the insulating film, and reduce the dielectric constant.

When the method for manufacturing a wiring structure of the present invention is applied to a multilayer wiring, after the step of filling the metal wiring material, an insulating barrier film is formed on the exposed surface of the insulating film and on the exposed surface of the metal wiring material. Preferably, it is deposited. As the inorganic barrier film, if a film using polysilazane as a substrate is used for the insulating film, at least one selected from the group consisting of SiN, SiC, and SiCN is preferable. BCB is also effective as an organic barrier film. Further, when the inorganic barrier film is exposed at the bottom of the wiring groove and / or the bottom of the via hole opened in the developing step, it is preferable to remove the inorganic barrier film by reactive ion etching or sputtering.

When an insulating barrier film is not used, a metal having a high melting point is selectively formed on Cu, for example, a Cu alloy (alloy with silicon, tantalum, titanium, tungsten, etc.) or a compound thereof. To prevent Cu diffusion.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) First, as shown in FIG. 4A, a wiring material W plug 403 is formed in an interlayer insulating film 402 on a semiconductor substrate 401 on which semiconductor elements are formed. After that, an interlayer insulating film 404 serving as a wiring interlayer film is deposited [FIG. 4B]. At this time, the interlayer film 401 is formed, for example, by CVD (Chemical Vapor Deposition).
n) is an SiO ₂ insulating film formed by the method n. The interlayer insulating film 404 has ultraviolet sensitivity and a relative dielectric constant of 3.
This is a film made of a material of 0 or less, for example, a substrate composed mainly of polysilazane, to which a photoacid generator and the like are added. For example, a polysilazane product manufactured by Clariant Japan KK can be mentioned. In particular, it is a polysilazane composition containing polymethylsilazane or phenylsilazane and a photoacid generator.
-181069.

The polysilazane or polysilazane composition used in the present invention may be one using polysilazane alone, a copolymer of polysilazane and another polymer, or a mixture of polysilazane and another compound. The general formula of polysilazane used is as shown in the following formula.

[0033]

Embedded image

(In the above formula, R ¹ , R ² , and R ³ each independently represent a hydrogen atom, an alkyl group, an alkenyl group, a cycloalkyl group, an aryl group, and a part other than these groups that is directly bonded to silicon or hydrogen. A group that is carbon, an alkylsilyl group,
Represents an alkylamino group. At this time, the interlayer insulating film 404 is deposited by a spin coating method of applying a solution to a rotating substrate, and the applied film thickness of the interlayer insulating film 404 is controlled by adjusting the number of rotations and the viscosity of the solution. It is possible.

Next, as shown in FIG. 4C, the surface of the photosensitive material before exposure is coated with a protective film 405 having a protective function and an antireflection function. However, this protective film 4
05 needs to be removed before the humidification heat treatment, before or after the development, or simultaneously with the development. By measuring the infrared absorption spectrum, it was confirmed that the silanolation reaction proceeds in the unexposed area when the protective film 405 is not used, whereas the reaction can be suppressed when the protective film 405 is used. I have. As the protective film (coating material) used here, a combination with the interlayer insulating film 404 is important. That is, first, the applied polysilazane (interlayer insulating film 404) and the antireflection / protective film 4
05 to prevent intermixing.
Has a protective function and an anti-reflection function at the same time, and thirdly, it has been completely removed at or before the stage of immersion in a developing solution and does not adversely affect the photosensitive material.
is necessary. As a material constituting such a protective film, for example, a water-soluble polymer film has been found to be suitable, and a water-soluble polymer (cellulose polymer, acrylic acid polymer, methacrylic acid polymer, N-vinylpyrrolidone) has been found. A mixture of a polymer, a vinyl alcohol polymer, a derivative thereof and a copolymer of any combination thereof) and a water-soluble fluororesin is preferably used.

It has also been confirmed that these films fulfill a sufficient protective function against moisture in the atmosphere at a film thickness of 10 nm or more. On the other hand, regarding the anti-reflection effect, there is an optimum thickness of the protective film 405. Depending on the exposure wavelength and the refractive index n of the protective film 405, it can be derived by the equations (1) and (2). Here, m is an integer of 0 or more.

Film thickness of protective film = exposure wavelength × (2m + 1) / 4n (1) Refractive index n of protective film = (refractive index of interlayer insulating film after application) ^1/2 (2) For example, by ArF (193 nm) In the case of exposure, assuming that the refractive index of the interlayer insulating film 404 immediately after application is 2.0, the thickness of the protective film 405 of 34 nm is optimal for antireflection.

Therefore, by using the protective film 405,
It is possible to achieve both the improvement of the stability of standing in the atmosphere during the withdrawal and the antireflection function in the exposure, and to achieve the fine patterning of the wiring groove.

After the application of the protective film 405, edge / back rinsing is performed using, for example, PGMEA / PGME (propylene glycol monomethyl ether acetate / propylene glycol monomethyl ether). Next, in order to evaporate the solvent, it is desirable to perform a heat treatment in the range of 40 ° C to 150 ° C. If the temperature is too low, the adhesion to the substrate is insufficient, and if the temperature is too high, the photosensitivity is lost. Therefore, the temperature range of the heat treatment needs to be adjusted according to the type and concentration of the photoacid generator added. There is.

Next, as shown in FIG.
That is, patterning by ultraviolet lithography,
Preferably, KrF (248 nm), ArF (193n)
m), patterning is performed using an excimer laser such as F ₂ (152 nm) or a light source such as a high-pressure mercury lamp.
The amount of exposure greatly depends on the type of ultraviolet light used and the type and amount of the photoacid generator, but is from 0.1 mJ / cm ² to 1000 mJ.
J / cm ² is good. Thereafter, simultaneous humidification and heating are performed to obtain desired development characteristics.

The condition of the simultaneous humidifying and heating treatment depends on the film thickness, the solvent, the exposure dose, the wavelength of the ultraviolet ray, and the like.
% To 100%, and the temperature is preferably in the range of room temperature to 80 ° C. In particular, 45% to 95%, 30C to 80C
The following conditions are preferred. In addition, when simultaneous processing of heating and humidification is not performed, or when processing conditions are inappropriate, a result is obtained in which film peeling is likely to occur in a fine wiring pattern having a narrow pitch, particularly a 0.6 μm pitch or less. I have.

It is also effective to perform a post exposure bake (PEB) treatment at a temperature in the range of 80 ° C. to 150 ° C. for about 1 minute to 5 minutes before the humidifying heat treatment after the exposure to improve the multiple interference effect in the film. is there.

Next, the exposed portion is developed, and a wiring groove is formed in the interlayer insulating film (photosensitive insulating film) 404 as shown in FIG. At this time, the developer is an alkaline aqueous solution,
For example, TMAH (tetramethylammonium hydroxide) or the like is used.

Next, the entire surface of the wafer is irradiated with ultraviolet light for 1 minute to
Perform for about 5 minutes to eliminate the photosensitive properties. After the ultraviolet irradiation, the humidifying heat treatment is performed again. The conditions at this time need to be set in an atmosphere with a humidity in the range of 40% to 90% and a temperature in the range of room temperature to 80 ° C. This humidification heat treatment makes it possible to eliminate Si—N bonds in the unexposed portions. If the treatment is not performed under these conditions, the heat resistance of the finally obtained film deteriorates and the relative dielectric constant decreases. A rise occurs. Thereafter, as a curing treatment, heating is performed at a temperature of 300 ° C to 400 ° C for 30 minutes. Preferably, heating is performed at 400 ° C. for 30 minutes, which is the same condition as the Cu annealing treatment in the subsequent step.

FIG. 13 is a graph showing the degassing amount when the finally obtained film is heated for each humidifying heat treatment condition after exposure. The degassing amount was indicated by the total spectrum intensity in mass spectrometry. FIG. 14 is a graph showing the relationship between the relative dielectric constant of the finally obtained film and the outgassing amount when the film is heated to 400 ° C. As can be seen from these figures, the characteristics of the finally obtained film,
In particular, the humidification heat treatment conditions are important because they greatly affect heat resistance and relative permittivity.

On the other hand, if the entire surface of the wafer is not irradiated with ultraviolet rays, the heat resistance of the film obtained after the heat treatment is deteriorated. This result will be described with reference to the desorption gas spectrum of FIG. FIG. 15 is a graph showing the relationship between the heating temperature and the amount of degassing, where the amount of degassing when the finally obtained film is heated is represented by the total spectrum intensity in mass spectrometry. When the ultraviolet irradiation treatment is not performed, a large amount of desorbed gas is generated at around 300 ° C. Therefore, it can be seen that the ultraviolet irradiation treatment is a very effective method for improving the heat resistance of the film.

If misalignment occurs between the underlying W plug and the formed groove pattern, the entire surface of the wafer is irradiated with the ultraviolet rays for about 1 to 4 minutes, and then subjected to a humidifying heat treatment. Alkaline aqueous solution, for example, TM
By dissolving in AH or the like, the misalignment pattern can be easily removed and the interlayer insulating film 404 having photosensitivity to ultraviolet light can be formed again.

Next, as shown in FIG. 4 (f), a conductive barrier film 406 is formed on the entire surface, and then a Cu seed film is deposited by sputtering, and this is used as an electrode for electrolytic plating. Is deposited to form a Cu film 407. At this time, as the conductive barrier film 406, Cu
For example, a metal such as Ti, Ta, W or the like and a nitride or silicide thereof or a laminate thereof are preferably used, and a laminate of Ta / TaN is preferred. The thickness of the formed film is preferably 5 nm to 40 nm. The thickness of the Cu seed film is 50 nm to 200 nm.
The range of nm is preferred. Thereafter, crystallization annealing of the Cu film is performed in a temperature range of 200 ° C. to 400 ° C. for 10 to 30 minutes. In particular, heating at 400 ° C. for about 30 minutes is optimal, because the crystallinity of Cu is promoted.

Here, when no barrier film is used, N
By irradiating a gas plasma containing nitrogen such as H ₃ ,
It is also possible to improve the diffusion resistance of Cu by nitriding the groove side wall.

Subsequently, as shown in FIG. 4G, the excess Cu film 407 and the excess barrier film 406 other than in the wiring groove and the via hole are removed by chemical mechanical polishing (CMP), and the Cu wiring 408 is removed. To form And FIG.
As shown in (h), an insulating barrier film 40 is formed thereon.
9, for example, a film of SiC, SiCN, SiN or the like is formed.
At this time, the thickness of the insulating barrier film 409 is not less than 5 nm and not more than 50 nm.
nm or less. This is because if it is too thin, the diffusion barrier property of Cu is insufficient, and if it is too thick, a load is imposed on the etching at the time of increasing the inter-wiring capacitance and opening the via hole. According to the above manufacturing method, a fine and good low dielectric constant pattern can be formed from a photosensitive material, and a high-performance multilayer wiring can be manufactured with a practical throughput. Improving the reliability of wiring by performing surface treatment of Cu and the photosensitive insulating film by plasma such as NH ₃ or He immediately before forming these insulating barrier films is also an effective means. .

The above is an application of the present invention to a method called a single damascene (Single Damascene) method in which a single-layer upper-layer wiring is formed by embedding and polishing on a wiring portion. Further, the present invention provides a so-called dual damascene (D) in which after forming an upper wiring layer and a via hole layer connected to the lower layer, a wiring material is buried in both and polished.
ual Damascene) method can be similarly applied. Hereinafter, an embodiment applied to a dual damascene method will be described.

(Embodiment 2) FIGS. 5A and 5B sequentially explain steps when a method similar to that of FIG. 4 is applied to a dual damascene method. Typically, the heating and humidifying conditions for the polysilazane are preferably the same as those described in the first embodiment.

First, for example, in the same procedure as in the first embodiment, as shown in FIG. 5A, an interlayer insulating film 502 is formed on a semiconductor substrate 501 on which semiconductor elements are formed.
After the wiring material W plug 503 is formed on the lower interlayer insulating film 504, the wiring material 50 is formed on the lower interlayer insulating film 504.
5 is formed. The lower interlayer insulating film 504 is formed of an insulating film having ultraviolet light sensitivity, and is formed of a wiring material 505.
Is composed of Cu and a conductive Ta / TaN laminated barrier film. Further thereon, a SiCN film 506 is formed as an inorganic barrier film. In the lower wiring structure shown in FIG. 5A, the material is not limited to the material shown here. For example, the interlayer insulating films 502 and 504 are made of SiO.sub.2.
₂ , HSQ, MSQ and organic polymers containing aromatics may be used. As the wiring material 505, Ag, Al,
Ni, Co, W, Si, Ti, Ta and their alloys or compounds may be used.
Instead of the iCN film 506, SiC, SiN, or the like may be used.

Next, an interlayer insulating film 507 is deposited by using a spin coating method. Here, as the interlayer insulating film 507,
A material having ultraviolet light sensitivity and a relative dielectric constant of 3.0 or less is used. For example, the material is made of a substrate containing polysilazane as a main component, to which a photoacid generator and the like are added.
Polysilazane manufactured by Clariant Japan KK can be used.

Next, as shown in FIG. 5C, before the exposure,
A protective film 508 having a protective function and an antireflection function is coated on the surface of the photosensitive material (the interlayer insulating film 507). Here, when considering the material of the protective film 508, it is important to consider a combination with the interlayer insulating film 507. For example, a water-soluble polymer film is appropriate. By using such a protective film 508, it is possible to achieve both the improvement in the stability of standing in the air during the withdrawal and the antireflection function in the exposure, and to achieve the fine patterning of the wiring groove.

After the application of the protective film 508, edge / back rinsing is performed using, for example, PGMEA / PGME. Next, in order to evaporate the solvent, heat treatment is performed in the range of 60 ° C to 120 ° C. In this heat treatment, if the temperature is lower than 60 ° C., the adhesion to the base is insufficient, and if the temperature is too high, the photosensitivity is lost. Therefore, the heat treatment is adjusted according to the type and concentration of the photoacid generator added. There is a need. Before exposure,
PEB treatment at 80 ° C to 15 to improve the multiple interference effect in the film
It is also effective to carry out for about 1 minute to 5 minutes in a temperature range of 0 ° C.

Next, as shown in FIG.
That is, patterning by ultraviolet lithography
Preferably, KrF (248 nm), ArF (193n)
m), F _Two(152 nm) and other high-pressure excimer lasers
Perform patterning using a light source such as a mercury lamp
Then, in order to obtain desired development characteristics, simultaneous humidification and heating are performed.
Work.

The conditions for the simultaneous humidifying and heating treatment depend on the film thickness, solvent, exposure dose, wavelength of ultraviolet rays, etc.
% To 100%, and the temperature is preferably in the range of room temperature to 80 ° C. In particular, 45% to 95%, 30C to 80C
The following conditions are preferred. It has been confirmed that when no treatment is performed under these conditions, film peeling occurs in a fine wiring pattern having a pitch of 0.6 μm or less.

Further, it is also effective to perform a PEB (post exposure bake) treatment at a temperature range of 80 ° C. to 150 ° C. for about 1 minute to 5 minutes before the humidifying heat treatment after the exposure to improve the multiple interference effect in the film. is there.

Next, the exposed portion is developed to form a via hole pattern 509 in the photosensitive insulating film as shown in FIG. As a developer at this time, an alkali aqueous developer,
For example, TMAH is used.

Next, the entire surface of the wafer is irradiated with ultraviolet rays for about 1 to 5 minutes to eliminate the photosensitive characteristics. After the ultraviolet irradiation, the humidifying heat treatment is performed again. The condition at this time is
It is necessary to perform the treatment in an atmosphere with a humidity in the range of 40% to 90% and a temperature in the range of room temperature to 80 ° C. If the treatment is not performed under these conditions, the heat resistance of the finally obtained film deteriorates,
And an increase in the relative dielectric constant. Then, as a curing process,
Heat at a temperature of 300 ° C to 400 ° C for 30 minutes. 400 ° C., 30 which is the same condition as the annealing process of Cu in the subsequent process.
Minutes of heating.

If misalignment occurs between the underlying wiring pattern and the formed via hole pattern, the entire surface of the wafer is irradiated with ultraviolet light for about 1 to 5 minutes.
After performing the humidifying heat treatment, an alkaline aqueous solution, for example,
By dissolving in TMAH or the like, the misalignment pattern can be easily removed and the interlayer insulating film 507 having photosensitivity to ultraviolet light can be formed again. At the same time as the development, or before and after the development, the protective film 50 may be used.
8 is removed.

Next, as shown in FIG. 5F, an interlayer insulating film (photosensitive insulating film) 510 is applied again on the via hole pattern 509 formed by losing the photosensitivity by spin coating or the like. After the coating, edge back rinse is performed. As the interlayer insulating film 510, the same one as the interlayer insulating film 507 can be used. Next, heat treatment is performed in the above-mentioned temperature range, and subsequently, an anti-reflection / protective film 511 is applied. Then, wiring groove patterning is performed by ultraviolet lithography. At this time, via hole pattern 5
No. 09 is already unaffected by the exposure processing since the photosensitive characteristics have already been lost.

Next, the exposed portion is developed to form a wiring groove pattern on the photosensitive insulating film as shown in FIG. As a developing solution at this time, an alkali aqueous developing solution, for example, TMAH is used.
No. 9 is not affected at all by the development processing since the curing processing has already been performed.

Next, as shown in FIG. 5H, a SiCN film 5 serving as an inorganic barrier film on the bottom of the via hole is formed by a reactive ion etching method or a sputtering method.
06 is removed. The etching conditions used at this time are preferably those having a high selectivity with respect to the interlayer insulating film (photosensitive insulating film) 510, for example, CHF ₃ under a low bias.
Etching using a / Ar gas or a CH ₂ F ₂ / Ar gas system is performed.

Next, as shown in FIG. 5 (i), after a conductive barrier film 512 is formed on the entire surface, a Cu seed film is deposited by a sputtering method, and this is used as an electrode to form an electrolytic plating method. Is deposited to form a Cu film 513. At this time, as the conductive barrier film 512, a metal such as Ti, Ta, W or the like, which can prevent the diffusion of Cu, a nitride or silicide thereof, or a laminate of them is preferably used. The film thickness is 5 nm to 40 n
m is preferred.

Subsequently, as shown in FIG.
Excess Cu other than in the wiring groove and via hole by the method
The film 513 and the excess barrier film 512 are removed, and a Cu wiring is formed. Then, as shown in FIG. 5H, an insulating barrier film 514, for example, SiC, SiCN,
A film such as SiN is formed. At this time, the insulating barrier film 5
It is desirable that the thickness of 14 be 5 nm or more and 50 nm or less.

(Embodiment 3) In Embodiment 3, an example in which a photosensitive insulating film is used and a conventional photoresist process and an etching process are combined to form a wiring structure will be described with reference to FIG.

First, according to the procedure described in the first embodiment, for example, as shown in FIG. 6A, a wiring material W plug 603 was formed on an interlayer insulating film 602 on a semiconductor substrate 601 on which a semiconductor element was formed. Later, the lower interlayer insulating film 60
4 is formed, a wiring groove formed in the lower interlayer insulating film 604 is filled with a wiring material 605, and a SiCN film 606 as an inorganic barrier film is formed thereon. Here, the lower interlayer insulating film 604 is formed of an insulating film having ultraviolet light sensitivity, and the wiring material 605 is made of Cu and conductive Ta /
It is made of a TaN laminated barrier film. The material constituting the lower wiring structure shown in FIG. 6A is not limited to the material shown here, but may be, for example, the interlayer insulating films 602 and 60.
4 can be made of an organic polymer containing SiO ₂ , HSQ, MSQ, or an aromatic material, and the wiring member 605 is made of Ag, Al, Ni, Co, W, Si, Ti, Ta, or an alloy thereof. A compound or the like can be used, and SiC, SiN, SiCN, or the like can be used for the inorganic barrier film.

Next, an interlayer insulating film 607 is deposited by using a spin coating method. Here, as the interlayer insulating film 607,
A material having ultraviolet light sensitivity and a relative dielectric constant of 3.0 or less is used. For example, the material is made of a substrate containing polysilazane as a main component, to which a photoacid generator and the like are added.
Polysilazane manufactured by Clariant Japan KK can be used.

Next, as shown in FIG. 6C, before exposure,
A protective film 608 having a protective function and an antireflection function is coated on the surface of the photosensitive material (the interlayer insulating film 607). Here, when considering the material of the protective film 608, it is important to consider a combination with the interlayer insulating film 607. For example, a water-soluble polymer film has been found to be appropriate as the protective film 608, and it has been confirmed that a film thickness of 10 nm or more fulfills a sufficient protective function against atmospheric moisture. By using such a protective film 608, it is possible to achieve both the improvement in stability of standing in the air during the withdrawal and the antireflection function in the exposure, and to achieve the fine patterning of the wiring groove.

After the application of the protective film 608, edge / back rinsing is performed using, for example, PGMEA / PGME. Next, in order to evaporate the solvent, heat treatment is performed in a range of 40 ° C to 150 ° C. In this heat treatment, the adhesion to the base is insufficient at a low temperature, and the photosensitivity is lost if the temperature is too high. Therefore, the heat treatment needs to be adjusted according to the type and concentration of the photoacid generator added. .

Next, as shown in FIG.
That is, patterning by ultraviolet lithography
Preferably, KrF (248 nm), ArF (193n)
m), F _Two(152 nm) and other high-pressure excimer lasers
Perform patterning using a light source such as a mercury lamp
Then, in order to obtain desired development characteristics, simultaneous humidification and heating are performed.
Work.

The conditions for the simultaneous humidifying and heating treatment depend on the film thickness, the solvent, the exposure dose, the wavelength of the ultraviolet light, and the like.
% To 100%, and the temperature must be in the range of room temperature to 80 ° C. In particular, conditions of 45% to 95% and 30 ° C to 80 ° C are preferable. It has been confirmed that when no treatment is performed under these conditions, film peeling occurs in a fine wiring pattern having a pitch of 0.6 μm or less.

It is also effective to perform the PEB treatment in the temperature range of 80 ° C. to 150 ° C. for about 1 minute to 5 minutes before the humidifying heat treatment after the exposure to improve the multiple interference effect in the film.

Next, the exposed portion is developed to form a via hole 609 in the photosensitive insulating film as shown in FIG. At this time, an alkali-water-soluble developer such as TMAH is used as the developer.

Next, the entire surface of the wafer is irradiated with ultraviolet light for 1 minute to
Perform for about 5 minutes to eliminate the photosensitive properties. Thereafter, the humidifying heat treatment is again performed at a humidity of 40% to 90% and a temperature of room temperature to 80%.
It is necessary to perform in an atmosphere in the range of ° C. If the treatment is not performed under these conditions, the heat resistance of the finally obtained film deteriorates and the relative dielectric constant increases. Then, after ultraviolet irradiation, it is heated at a temperature of 300 to 400 ° C. for 30 minutes as a curing treatment. Preferably, heating is performed at 400 ° C. for 30 minutes, which is the same condition as the Cu annealing treatment in the subsequent step.

If misalignment occurs between the underlying wiring pattern and the formed via hole pattern, the entire surface of the wafer is irradiated with ultraviolet rays for about 1 to 5 minutes.
After performing the humidifying heat treatment, an alkaline aqueous solution such as T
By dissolving in MAH or the like, the misalignment pattern can be easily removed, and the interlayer insulating film 607 having photosensitivity to ultraviolet light can be formed again. At the same time as the development, or before and after the development, the protective film 608 is formed.
Is removed.

Next, a photoresist is applied on the insulating film 607 including the formed via hole 609 and the photosensitivity has been lost, and a wiring groove pattern is exposed and developed, and a desired wiring groove pattern is formed into a photoresist pattern 610. It is formed [FIG. 6 (f)]. Next, the photoresist pattern 6
Using the mask 10 as a mask, the photosensitive insulating film and the resist are simultaneously etched to form a groove pattern in the photosensitive insulating film [FIG. 6 (g)]. Then, as shown in FIG. 6H, the inorganic barrier film exposed at the bottom of the via hole is removed by a reactive ion etching method, a sputtering method, or the like.
It is desirable that the etching gas used at this time has a high selectivity with respect to the interlayer insulating film (photosensitive insulating film) 607. In addition, although described as a photoresist here, it is also possible to use a photosensitive insulating film as a photoresist and perform etching by a similar method.

Next, a metal wiring is buried on the entire surface in the same manner as in the second embodiment to form a Cu wiring 611 [FIG. 6 (i)]. Then, as shown in FIG. 6J, an insulating barrier film 612 is formed thereon to form a wiring structure.

In the third embodiment, a photoresist step and a groove etching step are added as compared with the second embodiment. On the contrary, a wiring groove pattern is formed so as to overlap with a via pattern formed in advance. The structure can secure the reliability of the wiring against exposure misalignment.

[0082]

The present invention will be described in more detail with reference to the following examples.

(Embodiment 1) As shown in FIG. 7A, after a wiring material W plug 703 is formed on an interlayer insulating film 702 on a semiconductor substrate 701 on which a semiconductor element is formed,
An interlayer insulating film 704 serving as a wiring interlayer film was deposited [FIG.
(B)]. Subsequently, an interlayer insulating film 704 having ultraviolet sensitivity and a relative dielectric constant of 3.0 or less was deposited to a thickness of 0.3 μm. Here, as the interlayer insulating film 704, polysilazane (trade name: PS, manufactured by Clariant Japan KK)
-MSZ) was used. At this time, the interlayer insulating film 7 is formed by a spin coating method of applying a solution to the rotating substrate.
04 was applied and deposited. After application, PGMEA / PGM
Edge back rinse was performed using E.

Next, in order to evaporate the solvent, heating at 80 ° C., which is a condition for maintaining the photosensitive characteristics and ensuring good adhesion, was performed for 1 minute. Subsequently, before exposure, a water-soluble antireflection / protective film 705 containing a fluorine-based polymer as a main component is formed on the surface of the photosensitive material (interlayer insulating film 704).
Was coated with a thickness of 43 nm to ensure atmospheric stability [(FIG. 7 (c)]. As exposure processing, patterning was performed by irradiating a KrF excimer laser at 28 mJ / cm ² , and then multiple interference in the film was performed. PE for improved effect
After heating at 130 ° C. for 1 minute as a B (post exposure bake) treatment, simultaneous humidifying and heating treatment at 80% and 60 ° C. was performed for 1 minute (FIG. 7D).

Next, the exposed portion is developed using TMAH,
At the same time, the anti-reflection and protection film 705 was removed. After that, the entire surface of the wafer is irradiated with ultraviolet light by a high-pressure mercury lamp for 4 minutes,
Photosensitivity was lost. After that, a simultaneous humidifying and heating treatment at 80% and 60 ° C. was performed again for 1 minute, and then a curing treatment was performed by heating at a temperature of 400 ° C. for 30 minutes to obtain a wiring groove pattern [FIG. . At this time, the decrease in the film thickness in the curing treatment was 10% or less only in the film thickness direction. In addition, since a protective film having an anti-reflection effect is used, the stability in the atmosphere is maintained for 24 hours or more, and there is no adverse effect on the groove side wall due to multiple interference.

Next, as shown in FIG. 7F, a conductive TaN / Ta laminated barrier film 706 is formed on the entire surface for a total of four times.
After forming a 0 nm film, a Cu seed film is
00 nm, and using this as an electrode by electrolytic plating
A u film is deposited to a thickness of 600 nm, and a Cu film 707 having a total of 700 nm is deposited.
Was deposited. Then, after crystallization annealing of the Cu film was performed at 400 ° C. for 20 minutes, excess Cu other than in the wiring groove was removed by CMP to form a Cu wiring 708 [FIG.
(G)]. The CMP was performed using a polishing solution (slurry) in which hydrogen peroxide (H ₂ O ₂ ) was mixed with an abrasive mainly composed of silica (SiO ₂ ). In this Cu CMP, an interlayer insulating film (photosensitive insulating film) 704 and a barrier film 7 are formed.
06 and an interlayer insulating film (photosensitive insulating film) 704
It was confirmed that peeling or the like did not occur at any of the interfaces between the substrate and the interlayer insulating film (SiO ₂ film) 702. Then, as shown in FIG. 7H, a 25 nm-thick SiCN film 710 was formed thereon as an insulating barrier film to form a wiring structure.

In this process, adjacent 10 mm long wire pairs are formed at an interval of 0.20 μm and annealed at 400 ° C. for 10 hours.
It was confirmed that sufficient insulation resistance of about ^-9 A / cm ² was secured. It was also confirmed that the capacitance between wirings was reduced by about 30% as compared with the case where SiO ₂ was used as the interlayer film.

(Embodiment 2) In Embodiment 1, a single-layer upper wiring is formed by embedding and polishing on a lower wiring portion.
That is, this is an example of a method called a single damascene method.Next, after forming an upper wiring layer and a via hole layer connected to a lower layer, a wiring material is buried in both, and polishing is performed. An example to which the present invention is applied will be described.

As shown in FIG. 8A, a wiring material W plug 803 is formed on an SiO ₂ film 802 as an interlayer insulating film on a semiconductor substrate 801 on which a semiconductor element is formed.
A lower interlayer insulating film 804 is deposited, and the lower interlayer insulating film 804 is deposited.
A wiring material 805 was provided in the inside, and a lower layer wiring was formed. The wiring member 805 was formed of Cu and a conductive Ta / TaN laminated barrier film. On top of that, as an inorganic barrier film, SiC
An N film 806 was formed with a thickness of 25 nm.

Next, as shown in FIG. 8B, a polysilazane (trade name: PS-M) manufactured by Clariant Japan Co., Ltd., which is photosensitive to ultraviolet light and has a relative dielectric constant of 2.7.
An interlayer insulating film 807 made of SZ) was applied to a thickness of 0.7 μm by spin coating. After coating, edge back rinse was performed using PGMEA / PGME.

Next, in order to evaporate the solvent, heating at 60 ° C., which is a condition for maintaining the photosensitive characteristics and ensuring good adhesion, was performed for 1 minute. Next, the surface of the polysilazane (interlayer insulating film 807) was coated with a water-soluble antireflection / protective film 808 with a thickness of 43 nm to ensure atmospheric stability [FIG. 8 (c)]. Then, as exposure processing,
Patterning was performed by irradiating with a KrF excimer laser at 40 mJ / cm ² , and then simultaneous humidification and heating at 80% at 60 ° C. was performed for 3 minutes (FIG. 8D).

Next, the exposed portion was developed using TMAH. Next, the entire surface of the wafer was irradiated with ultraviolet rays for 4 minutes to eliminate the photosensitive characteristics, and then subjected to simultaneous humidification and heating at 80% and 60 ° C. for 3 minutes. A curing treatment of heating at a temperature of 400 ° C. for 30 minutes was performed [FIG. 8 (e)].

Next, the formed via hole pattern 80
9 and the interlayer insulating film 807 from which the photosensitivity has disappeared, a photosensitive polysilazane is applied again as an interlayer insulating film 810 by a spin coating method, and then the anti-reflection and protection film 81 is applied.
1 was applied. Here, the same photosensitive polysilazane as that used for the interlayer insulating film 807 was used. After the application, edge / back rinsing was performed in the same manner as described above [FIG. 8 (f)]. Further, heat treatment was performed in the above-mentioned temperature range.

Next, wiring groove patterning by ultraviolet lithography was performed as an exposure process. At this time, since the via hole pattern 809 has already lost the photosensitive characteristics, it is not affected by the exposure processing at all. For example, Kr
Patterning was performed by irradiating an F excimer laser at 28 mJ / cm ² , and then simultaneous humidification and heating at 80% at 60 ° C. was performed for 1 minute. After that, the exposed portion is developed, and FIG.
As shown in (g), a photosensitive insulating film (interlayer insulating film 80) is formed.
7, 810), wiring grooves and via holes were formed. At this time, an alkaline water-soluble developer TMAH was used as a developer. The via-hole pattern 809 was not affected by the development processing at all because the curing processing was already performed.

Next, the SiCN film 806 on the bottom surface of the via hole was selectively removed by a reactive ion etching method, specifically, a reactive ion etching using a CHF ₃ / Ar-based gas [FIG. 8 (h)]. . Next, as shown in FIG. 8I, a conductive TaN / Ta laminated barrier film 812 is formed in a total thickness of 40 nm, and then a Cu seed film is deposited to a thickness of 100 nm by a sputtering method. Was deposited, and a Cu film 813 was deposited in a total of 700 nm. Then, after performing crystallization annealing of the Cu film at 400 ° C. for 20 minutes, excess Cu other than in the wiring groove or the via hole is removed by CMP [FIG. 8 (j)].
CMP is a polishing solution (slurry) obtained by mixing hydrogen peroxide (H ₂ O ₂ ) with an abrasive mainly composed of silica (SiO ₂ ).
This was performed using At this time, it was confirmed that peeling did not occur at any of the photosensitive insulating film / TaN interface and the photosensitive insulating film / SiO ₂ film interface in the Cu CMP. Then, as shown in FIG. 8K, a 25 nm-thick SiCN film 714 was formed thereon as an insulating barrier film to form a wiring structure.

In this process, adjacent 10 mm long wire pairs are formed at an interval of 0.20 μm, and even if annealed at 400 ° C. for 10 hours, the leak current between the wires becomes 10 mm.
It was confirmed that sufficient insulation resistance of about ^-9 A / cm ² was secured.

(Example 3) In Example 2, a photosensitive insulating film to be an upper wiring interlayer film was formed on a via hole formed by a photosensitive low dielectric constant film, and a via hole connecting to an upper wiring layer and a lower layer was formed. This is a method of forming and then embedding a wiring material in both to polish. In Example 3, a photosensitive interlayer insulating film of a via hole portion and an upper wiring portion is deposited, and a via pattern is formed by ultraviolet lithography. ,
A method of forming a wiring groove pattern using a photoresist and etching will be described.

As shown in FIG. 9A, a wiring material W plug 903 is formed on an SiO ₂ film 902 as an interlayer insulating film on a semiconductor substrate 901 on which a semiconductor element is formed.
A lower interlayer insulating film 904 is deposited, and the lower interlayer insulating film 904 is deposited.
A wiring material 905 was provided in the inside, and a lower layer wiring was formed. The wiring material 905 was formed of Cu and a conductive Ta / TaN laminated barrier film. On top of that, SiC is used as an inorganic barrier film.
An N film 906 was formed with a thickness of 25 nm.

Next, as shown in FIG. 9B, a polysilazane (trade name: PS-M) manufactured by Clariant Japan Co., Ltd., which is photosensitive to ultraviolet light and has a relative dielectric constant of 2.7.
An interlayer insulating film 907 made of SZ) was applied to a thickness of 1.0 μm by spin coating. Next, the interlayer insulating film 9
07, a water-soluble anti-reflection / protective film 908 was
Coating with a thickness of nm ensures atmospheric stability [Fig.
(C)]. After coating, apply edge back rinse to PGME
Performed using A / PGME.

Next, in order to evaporate the solvent, heating at 40 ° C., which is a condition for maintaining the photosensitive characteristics and ensuring good adhesion, was performed for 1 minute. Subsequently, as exposure processing, patterning is performed by irradiating a KrF excimer laser at 28 mJ / cm ² , and thereafter, 80%, 40 ° C.
Humidification heating simultaneous processing was performed for 3 minutes [FIG. 9 (d)].

Next, the exposed portion was developed using TMAH. The entire surface of the wafer was irradiated with ultraviolet rays for 4 minutes to eliminate the photosensitive property, and the humidifying and heating simultaneous treatment was performed at 40 ° C. at 80%, and then the curing treatment was performed by heating at 400 ° C. for 30 minutes [FIG. (E)].

Next, the formed via hole pattern 90
9 and a photoresist is applied on the interlayer insulating film 907 having lost the photosensitivity, and a wiring groove pattern is exposed and developed.
A desired wiring groove pattern was formed by a photoresist [FIG. 9 (f)]. Next, using the photoresist pattern 910 as a mask, the interlayer insulating film 907 was etched to form a groove pattern in the interlayer insulating film 907. At this time, the depth of the groove pattern formed by this etching was set to be shallower than the already formed via hole pattern 909, so that the groove pattern itself did not reach the SiCN film 906 which was an inorganic barrier film.

Subsequently, as shown in FIG. 9G, the inorganic barrier film (SiCN film 90) exposed at the bottom of the via hole is formed.
6) is a reactive ion etching method, specifically CHF ₃ /
It was removed by reactive ion etching using an Ar-based gas. Thereafter, as shown in FIG.
After forming the aN / Ta laminated barrier film 911 in a total thickness of 40 nm, a Cu seed film was deposited in a thickness of 100 nm by a sputtering method, and Cu was deposited by an electrolytic plating method using the Cu seed film as an electrode to deposit a Cu film 912 in a total thickness of 700 nm. Then 4
After crystallization annealing of the Cu film at 00 ° C. for 20 minutes,
Excess Cu other than in the via hole and the wiring groove was removed by CMP [FIG. 9 (i)]. CMP is made of silica (S
Hydrogen peroxide (H ₂ O ₂ ) is used as an abrasive mainly composed of iO ₂ ).
Was carried out using a polishing solution (slurry) in which was mixed. At this time, in this Cu CMP, the photosensitive insulating film / TaN
It was confirmed that peeling did not occur at any of the interface and the photosensitive insulating film / SiO ₂ film interface. Then, as shown in FIG. 9 (j), a 25 nm-thick SiCN film 913 was formed thereon as an insulating barrier film to form a wiring structure.

In this process, even if adjacent 10 mm long wiring pairs are formed at an interval of 0.20 μm and annealed at 400 ° C. for 10 hours, the leakage current between the wirings is 10 μm.
It was confirmed that sufficient insulation resistance of about ^-9 A / cm ² was secured. In the third embodiment, the use of a photoresist and a groove etching process are added as compared with the second embodiment. On the contrary, since the wiring groove pattern is formed so as to overlap the via pattern formed in advance, the exposure A strong structure against misalignment can be obtained.

In Examples 1 to 3 described above, the Cu
Although the electrolytic plating method was used as the film forming method, the present invention is not limited to this. For example, a Cu film can be formed by MOCVD (organic metal CVD) or spin coating. The range in which the photosensitive insulating film is used is W
The present invention is not limited to the plug and the Cu wiring, but may be applied as a so-called interlayer film of a contact hole.

FIG. 10 is a sectional view showing a case where an LSI multilayer wiring is formed by using the wiring structure manufacturing method of the present invention. A silicon oxide film 1001 is formed on a semiconductor substrate 1000 on which a semiconductor element such as a MOS (metal-oxide-semiconductor) transistor is formed, and an electrode of the semiconductor element formed on the semiconductor substrate 1000 is formed on the silicon oxide film 1001. Is provided so as to penetrate. An SiON film 1103 is formed on the silicon oxide film 1001, and a multilayer wiring structure in which a photosensitive insulating film 1104 is stacked in multiple layers based on the present invention is provided thereon. In the multilayer wiring structure, a wiring groove and a via hole are formed in the photosensitive insulating film 1104, and the inside of the wiring groove and the via hole is filled with a Cu film 1106. A conductive barrier film 1105 is formed at the interface between the Cu film 1106 and the bottom and side surfaces of the wiring groove or via hole.

[0107]

As described above, according to the present invention, when a wiring structure using a low dielectric constant interlayer film is manufactured, by using an interlayer insulating film having UV-sensitive characteristics, the dryness of the wiring groove can be improved. There is an effect that a fine wiring structure can be formed without using etching or ashing. In addition, by constructing a wiring structure in which Cu as a wiring material and an interlayer insulating film having an ultraviolet light-sensitive property and a practical manufacturing method thereof are constructed, the wiring performance is improved, the wiring process is simplified, and the cost is reduced. Can be achieved at the same time.

[Brief description of the drawings]

FIGS. 1A to 1F are cross-sectional views sequentially showing an example of a conventional manufacturing process of a wiring structure.

FIGS. 2A to 2H are cross-sectional views sequentially illustrating another example of a conventional manufacturing process of a wiring structure.

FIGS. 3A to 3G are cross-sectional views sequentially illustrating still another example of a conventional wiring structure manufacturing process.

FIGS. 4A to 4H are cross-sectional views sequentially illustrating a manufacturing process of a wiring structure according to the first embodiment of the present invention.

5 (a) to 5 (j) are cross-sectional views sequentially showing manufacturing steps of a wiring structure according to a second embodiment of the present invention.

FIGS. 6A to 6J are cross-sectional views sequentially showing a manufacturing process of a wiring structure according to a third embodiment of the present invention.

FIGS. 7A to 7H are cross-sectional views sequentially showing manufacturing steps of a wiring structure in the first embodiment.

FIGS. 8A to 8J are cross-sectional views sequentially showing the steps of manufacturing the wiring structure in the second embodiment.

FIGS. 9A to 9J are cross-sectional views sequentially illustrating the steps of manufacturing the wiring structure in the third embodiment.

FIG. 10 is a cross-sectional view of a multilayer wiring structure when the present invention is applied to a multilayer wiring of an LSI.

FIG. 11 is a cross-sectional view showing a wiring structure when an antireflection protective film is not used.

FIG. 12 is a graph showing an infrared absorption spectrum of a polysilazane film used as a photosensitive insulating film.

FIG. 13 is a graph showing degassing characteristics.

FIG. 14 is a graph showing the relationship between the outgas amount and the relative permittivity.

FIG. 15 is a graph showing degassing characteristics.

[Explanation of symbols]

401,501,601,701,801,901
Semiconductor substrate 402, 404, 502, 504, 507, 510, 6
02,604,607,702,704,804,80
7,810,904,907 Interlayer insulating film 403,503,603,703,803,903
Wiring material W plug 405, 508, 511, 608, 705, 808, 9
08 Protective film 406, 409, 512, 514, 612, 706, 8
12,911 barrier film 407,513,707,813,912 Cu film 408,611,708 Cu wiring 505,605,805,905 Wiring material 506,606,710,806,906,913
SiCN film 509, 809, 909 Via hole pattern 609 Via hole 610, 910 Photoresist pattern 802, 902 SiO ₂ film

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 7, 2002 (2002.2.7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Manufacturing <br/> method for producing a wiring structure in a semiconductor device [Title of the Invention]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a wiring structure, and more particularly, after forming wiring grooves and via holes in the interlayer insulating film and a conductive film is deposited thereon, chemical mechanical polishing (CMP; Chemical Mechanical Polishin
g) method or the like to remove excess conductive film, embedding a conductive film on the inner wiring grooves and via holes, to a so-called Damascene (Damascene) Method A method for manufacturing a wiring structure using.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

[0020] The present invention, in order to solve the above problems, and an object thereof is to provide a method for manufacturing a wiring structure for forming the wiring of a multilayer wiring by a damascene method using a photosensitive low dielectric constant material.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Deleted

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Deleted

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

[0023]

According to the method of manufacturing a wiring structure of the present invention, an insulating film having ultraviolet light sensitivity is basically formed on a substrate on which a semiconductor element is formed and a lower wiring is formed thereon. Forming a film, irradiating a predetermined region of the insulating film with ultraviolet light, exposing the insulating film, and removing the exposed portion by developing the insulating film, thereby removing the wiring groove, the via hole, and the contact hole. Developing at least one or more of them in the insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/88 K 21/90 B (72) Inventor Taku Ogura 5-7-1 Shiba 5-chome, Minato-ku, Tokyo NEC Corporation (72) Yoshihiro Hayashi 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation Tatsuro Nagahara 2-28-8 Honkomagome, Bunkyo-ku, Tokyo Bunkyo Green Court Center Office 9F Clariant Japan K.K. (72) Inventor Hideki Matsuo 2-28-8 Honkomagome Bunkyo-ku, Tokyo Bunkyo Green Court Center Office 9F Clariant Japan K.K. HH06 HH07 HH08 HH11 HH14 HH15 HH18 HH19 HH21 HH27 HH28 HH30 HH32 HH33 HH34 JJ01 JJ11 JJ18 JJ19 JJ21 JJ27 JJ28 JJ30 JJ32 JJ33 JJ34 KK01 KK04 KK05 KK06 KK07 KK08 KK11 KK14 KK15 KK18 KK19 KK21 KK27 KK28 KK30 KK32 KK33 KK34 MM01 MM02 MM12 MM13 NN06 NN07 PP11 PP15 PP26 PP27 PP33 QQ04 QQ09 QQ13 QQ14 QQ37 QQ48 QQ54 QQ72 QQ73 QQ74 RR01 RR04 RR06 RR08 RR21 RR24 RR27 SS11 SS22 TT04 XX01 XX03 XX15 XX24 XX33 XX34 5F058 AB06 AC03 AC07 AF04 AG01 AG09 AH02 BD04 BD10 BD18 BD19 BE01 BF46 BH01 BH17 BJ02

Claims (23)

[Claims] 1. A wiring structure on a substrate on which a semiconductor element is formed, comprising: an insulating film formed on the substrate; and a metal containing copper as a main component in wiring grooves and via holes formed in the insulating film. A wiring structure, comprising: a wiring and a connection plug formed by filling a wiring material, wherein the insulating film is formed of a material having ultraviolet sensitivity. 2. A wiring structure on a substrate on which a semiconductor element is formed, comprising: a plurality of insulating films stacked on the substrate; and a wiring groove and a via hole formed in each of the insulating films mainly containing copper. And a connection plug formed by filling a metal wiring agent, wherein at least one of the plurality of insulating films is formed of a material having ultraviolet sensitivity. 3. The wiring structure according to claim 2, wherein a barrier insulating film is interposed between adjacent insulating films. 4. The barrier insulating film is made of SiN, SiC, Si
4. The wiring structure according to claim 3, wherein the wiring structure is formed of at least one selected from the group consisting of CN. 5. The wiring structure according to claim 1, wherein the insulating film formed of a material having photosensitivity to ultraviolet light comprises a substrate containing polysilazane as a main component. 6. A step of forming an insulating film having ultraviolet light sensitivity on a substrate on which a semiconductor element is formed and a lower wiring is formed thereon, and irradiating a predetermined region of the insulating film with ultraviolet light; A step of exposing the insulating film, a developing step of removing the exposed portion by developing the insulating film, thereby opening at least one or more of a wiring groove, a via hole, and a contact hole in the insulating film; A method for manufacturing a wiring structure having: 7. The wiring structure according to claim 6, further comprising a step of heating the insulating film at a predetermined temperature between the step of forming the insulating film having ultraviolet light sensitivity and the step of exposing. Production method. 8. The method of manufacturing a wiring structure according to claim 6, further comprising a step of simultaneously humidifying and heating the insulating film at a predetermined humidity and temperature between the exposing step and the developing step. 9. The method according to claim 8, further comprising a step of heating the insulating film at a predetermined temperature between the step of exposing and the step of simultaneously performing humidification and heating. 10. The method of manufacturing a wiring structure according to claim 6, further comprising a step of filling a metal wiring material in a portion opened in the developing step. 11. A step of forming a protective film having a protective function and an anti-reflection function on the insulating film immediately after the step of forming an insulating film having ultraviolet light sensitivity, and a step of filling a metal wiring material. The method for manufacturing a wiring structure according to claim 10, further comprising: a step of removing the protective film before performing. 12. The method according to claim 11, wherein the protective film comprises a water-soluble polymer film. 13. A step of performing ultraviolet irradiation after the developing step, a step of performing humidifying heat treatment following the step of performing ultraviolet irradiation, and a step of performing a curing treatment by heating subsequent to the humidifying heat treatment step. The method for manufacturing a wiring structure according to claim 6, comprising: 14. The method of manufacturing a wiring structure according to claim 13, further comprising, after the step of performing the curing treatment, a step of filling a metal wiring material in a portion opened in the developing step. 15. Immediately after the step of forming an insulating film having photosensitivity to ultraviolet light, a step of forming a protective film having a protective function and an antireflection function on the insulating film and a step of performing ultraviolet irradiation are performed. The method of manufacturing a wiring structure according to claim 13, further comprising: removing the protective film by the following. 16. The method according to claim 15, wherein the protective film is formed of a water-soluble polymer film. 17. The method according to claim 10, further comprising, after the step of filling the metal wiring material, a step of depositing an inorganic barrier film on the exposed surface of the insulating film and the exposed surface of the metal wiring material. 2. The method for manufacturing a wiring structure according to claim 1. 18. An inorganic barrier film comprising: SiN, SiC, S
The method for manufacturing a wiring structure according to claim 17, wherein the wiring structure is formed by at least one member selected from the group consisting of iCN. 19. When the inorganic barrier film is exposed at the bottom of the wiring groove and / or the bottom of the via hole opened in the developing step, the inorganic barrier film is removed by reactive ion etching or sputtering. A method for manufacturing a multilayer wiring according to any one of claims 6 to 18. 20. The method for manufacturing a wiring structure according to claim 6, wherein the insulating film is made of a substrate containing polysilazane as a main component. 21. The developing step, wherein at least one via hole is opened, and after the developing step, before the step of filling a metal wiring material, the photosensitive layer has ultraviolet sensitivity on the opened via hole. Depositing a second insulating film, irradiating a predetermined region with ultraviolet light to the second insulating film to expose the second insulating film, and developing the second insulating film. 15. The method of manufacturing a wiring structure according to claim 10, further comprising: removing an exposed portion to simultaneously form a desired wiring groove and a via hole. 22. The method according to claim 21, wherein the insulating film and the second insulating film are made of a substrate containing polysilazane as a main component. 23. When misalignment occurs between a portion opened in the developing step and a lower wiring, after performing ultraviolet irradiation and humidifying heat treatment on the entire surface of the semiconductor substrate, the developing solution used in the developing step is removed. 3. A pattern can be formed again by dissolving in the same solution.
3. The method for manufacturing a multilayer wiring according to any one of 2.