CN114446782A - Method for manufacturing storage capacitor - Google Patents

Method for manufacturing storage capacitor Download PDF

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Publication number
CN114446782A
CN114446782A CN202210103068.7A CN202210103068A CN114446782A CN 114446782 A CN114446782 A CN 114446782A CN 202210103068 A CN202210103068 A CN 202210103068A CN 114446782 A CN114446782 A CN 114446782A
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CN
China
Prior art keywords
mask layer
layer
groove
forming
mask
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Pending
Application number
CN202210103068.7A
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Chinese (zh)
Inventor
黄子伦
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Suzhou Juqian Semiconductor Co ltd
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Suzhou Juqian Semiconductor Co ltd
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Priority to CN202210103068.7A priority Critical patent/CN114446782A/en
Publication of CN114446782A publication Critical patent/CN114446782A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

Abstract

The invention provides a manufacturing method of a storage capacitor, which comprises the following steps: providing a semiconductor substrate; forming a first mask layer; etching the first mask layer to form a first groove; forming a second mask layer positioned at the bottom and the side wall of the first groove and above the first mask layer so as to form a second groove; removing the second mask layer, the first mask layer and the second mask layer positioned at the bottom of the second groove above the first mask layer; sequentially forming a third mask layer, a fourth mask layer and a fifth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and the fourth mask layer to form a third groove; etching the semiconductor substrate by taking the third mask layer, the fourth mask layer and the fifth mask layer as barrier layers, and forming a fourth groove in the semiconductor substrate; removing the third mask layer, the fourth mask layer and the fifth mask layer; the dielectric layer and the conductive layer are formed, and the method can reduce the process complexity and the production cost.

Description

Method for manufacturing storage capacitor
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a storage capacitor.
Background
The unit cell of the storage capacitor generally includes a storage capacitor and a MOS transistor. The increase in the storage density thereof requires more memory cells to be integrated per unit area and more information to be stored per unit memory cell. With the improvement of the integration level and the performance requirement of the semiconductor technology, the area of the chip is continuously reduced, the number of required photoetching steps is increased in order to integrate more storage units on a unit area, the requirement on the photoetching process is higher and higher, the process complexity is correspondingly increased, and the production cost is increased.
Therefore, there is a need to provide a new manufacturing method of a storage capacitor to improve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a manufacturing method of a storage capacitor, which is used for reducing the requirement on the photoetching precision of a photoetching machine on the premise of ensuring the performance of the storage capacitor, thereby reducing the process complexity and the production cost.
To achieve the above object, a method for manufacturing a storage capacitor of the present invention includes:
providing a semiconductor substrate; forming a first mask layer on the semiconductor substrate; etching the first mask layer to form a first groove; forming a second mask layer positioned at the bottom and the side wall of the first groove and above the first mask layer to form a second groove, wherein the groove width and the groove depth of the second groove are both smaller than those of the first groove; removing the second mask layer above the first mask layer, the first mask layer and the second mask layer positioned at the bottom of the second groove; sequentially forming a third mask layer positioned on the residual second mask layer, a fourth mask layer positioned on the third mask layer and a fifth mask layer positioned on the fourth mask layer; grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed; removing the second mask layer and the fourth mask layer to form a third groove; etching the semiconductor substrate by taking the third mask layer, the fourth mask layer and the fifth mask layer around the third groove as barrier layers, and forming a fourth groove in the semiconductor substrate; removing the third mask layer, the fourth mask layer and the fifth mask layer which are used as barrier layers above the fourth trench; and forming a dielectric layer and a conductive layer on the fourth groove.
Optionally, forming a dielectric layer and a conductive layer on the fourth trench includes:
forming an insulating layer on the side wall of the fourth groove, the bottom of the fourth groove and the semiconductor substrate; forming a first dielectric layer on the insulating layer; forming a first conductive layer on the first dielectric layer; forming a second dielectric layer on the first conductive layer; and forming a second conductive layer on the second dielectric layer.
Optionally, the method further comprises: forming a third dielectric layer on the second conductive layer, and carrying out planarization treatment; and etching the third dielectric layer to form a through hole so as to expose the first conductive layer and the second conductive layer.
Optionally, the method further comprises: and filling a third conducting layer in the through hole, and etching the third conducting layer to complete metal interconnection.
Optionally, the first mask layer, the second mask layer, the third mask layer, the fourth mask layer and the fifth mask layer are made of silicon nitride.
Optionally, the material of the insulating layer is at least one of materials with a dielectric constant greater than 3.9.
Optionally, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.
Optionally, the material of the conductive layer is copper, aluminum or tungsten.
The manufacturing method of the storage capacitor provided by the invention has the beneficial effects that: the manufacturing method can finish the etching with higher photoetching precision under the production condition of using common photoresist, and the finally manufactured groove has narrower groove width, thereby being beneficial to increasing the surface area of the capacitor and improving the capacity of the storage capacitor, reducing the requirement on the photoetching precision of a photoetching machine on the premise of ensuring the performance of the storage capacitor, and further reducing the process complexity and the production cost.
Drawings
FIG. 1 is a flow chart of a method of manufacturing a storage capacitor according to the present invention;
FIG. 2 is a schematic illustration of an intermediate structure of some embodiments of the present invention;
FIG. 3 is a schematic illustration of an intermediate structure of yet further embodiments of the present invention;
FIGS. 4A-4J are schematic illustrations of intermediate structures in further embodiments of the invention;
fig. 4K is a schematic diagram of a storage capacitor structure according to the present invention.
Reference numbers in the figures:
01 a first trench; 02 a second groove; 03 a third groove; 04 a fourth trench; 05 through holes; 100 a semiconductor substrate;
201 a first mask layer; 202 a second mask layer; 203 a third mask layer; 204 a fourth mask layer; 205 a fifth mask layer;
301 an insulating layer; 302 a first dielectric layer; 303 a first conductive layer; 304 a second dielectric layer; 305 a second conductive layer; 306 a third dielectric layer; 307 a third conductive layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
Fig. 1 is a schematic flow chart of a manufacturing method of a storage capacitor, and fig. 2 is a schematic block diagram of a stepwise intermediate structure of each process preparation stage in this example.
Referring to fig. 1, a method for manufacturing a storage capacitor according to an embodiment of the present invention includes the following steps:
s101, a semiconductor substrate 100 is provided.
Exemplarily, as shown in (a) of fig. 2, the semiconductor substrate 100 may be an N-type or P-type silicon substrate. The material of the semiconductor substrate 100 includes one or more combinations of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the semiconductor substrate 100 may also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate.
S102, forming a first mask layer 201 on the semiconductor substrate 100.
Illustratively, as shown in fig. 2 (a), the first mask layer 201 may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.
S103, etching the first mask layer 201 to form a first groove 01.
Illustratively, as shown in fig. 2 (b), the first trench 01 may be formed as shown by coating a photoresist on the first mask layer 201 and then performing a patterned etching. The photoresist used for this step may be a relatively inexpensive photoresist.
And S104, forming a second mask layer 202 on the bottom and the side wall of the first groove 01 and above the first mask layer 201 to form a second groove 02, wherein the groove width and the groove depth of the second groove 02 are both smaller than those of the first groove 01.
Illustratively, as shown in (c) of fig. 2, the second trench 02 may be formed by removing the photoresist coated on the first mask layer 201 and then depositing a layer of polysilicon, which may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride. The photoresist used for this step can still be a relatively inexpensive photoresist.
S105, removing the second mask layer 202 above the first mask layer, the first mask layer 201, and the second mask layer 202 located at the bottom of the second trench 02.
Illustratively, after an etching process is performed to remove the second mask layer 202 above the first mask layer 201 and the second mask layer 202 located at the bottom of the second trench 02, the structure of the remaining first mask layer 201 and the second mask layer 202 is shown in fig. 2 (d). After that, the remaining first mask layer 201 is removed by further etching, and the structure of the remaining second mask layer 202 is shown in (e) of fig. 2.
S106, sequentially forming a third mask layer 203 on the remaining second mask layer 202, a fourth mask layer 204 on the third mask layer 203, and a fifth mask layer 205 on the fourth mask layer 204.
Exemplarily, as shown in (a) of fig. 3, a third mask layer 203 is formed on a semiconductor substrate, and then, further, as shown in (b) of fig. 3, a fourth mask layer 204 is formed on a surface of the third mask layer 203; then, as shown in (c) of fig. 3, a fifth mask layer 205 is formed on the surface of the fourth mask layer 204. The third mask layer 203, the fourth mask layer 204, or the fifth mask layer 205 may be polysilicon, which may be any one or more of silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.
S107, the fourth mask layer 204 and the fifth mask layer 205 are ground and thinned to expose the second mask layer 202.
Illustratively, the intermediate structure shown in fig. 3 (c) is ground down to expose the second mask layer 202, as shown in fig. 3 (d).
S108, the second mask layer 202 and the fourth mask layer 203 are removed, and a third trench 03 is formed.
Illustratively, the third trench 03 as shown in (e) of fig. 3 is formed by removing all of the second mask layer 202 and a portion of the fourth mask layer 203 as shown in (d) of fig. 3 by wet etching or dry etching.
S109, etching the semiconductor substrate 100 by using the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 around the third trench 03 as a barrier layer, and forming a fourth trench 04 in the semiconductor substrate 100.
Illustratively, the third trench 03 shown in (e) of fig. 3 is patterned and etched with the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 around the third trench 03 as a barrier layer, so as to etch a portion of the semiconductor substrate 100, thereby forming a fourth trench 04 in the semiconductor substrate 100, as shown in (f) of fig. 3. As can be seen from the figure, the groove width of the fourth trench 04 is narrower, which helps to increase the surface area of the capacitor and increase the capacity of the storage capacitor.
S110, removing the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 as a blocking layer above the fourth trench.
Illustratively, the intermediate structure after removing the third mask layer 203, the fourth mask layer 204, and the fifth mask layer 205 as the barrier layer over the fourth trench is shown in (g) of fig. 3.
And S111, forming a dielectric layer and a conductive layer on the fourth groove.
This step is described in further detail below with particular reference to the various processes in fig. 4.
As shown in fig. 4A, an insulating layer 301 is formed on the sidewalls of the fourth trench 04, the bottom of the fourth trench 04, and the semiconductor substrate 100, and the insulating layer is made of at least one material having a dielectric constant greater than 3.9. Optionally, the material of the insulating layer includes at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium dioxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide. Then, as shown in fig. 4B, a first dielectric layer 302 is formed on the insulating layer; as shown in fig. 4C, a first conductive layer 303 is formed on the first dielectric layer 302; as shown in fig. 4D, a second dielectric layer 304 is formed on the first conductive layer 303; as shown in fig. 4E (a), a second conductive layer 305 is formed on the second dielectric layer 302, and then a photolithography window is formed by adding a photomask, so as to etch away the edge portion of the second conductive layer 305, thereby forming an intermediate structure as shown in fig. 4E (b). As shown in fig. 4F, a third dielectric layer 306 is formed on the second conductive layer 305. As shown in fig. 4G, the via hole shown in fig. 4G is further etched to expose the first conductive layer 303 by etching the third dielectric layer 306 to expose the second conductive layer 305 and the second dielectric layer 304 at a time, so as to form a via hole 05, as shown in fig. 4H. The via is filled with a third conductive layer 307, as shown in fig. 4I. As shown in fig. 4J and fig. 4K, the third conductive layer 307 is etched by applying photoresist and patterning to complete metal interconnection. As can be seen from fig. 4K, the above-mentioned manufacturing method can complete the self-aligned boundary, and expand the two second trenches 02 shown in fig. 2 (c) into nine fourth trenches 04 in fig. 4A, thereby realizing the fabrication of the multiple sidewall pattern.
In this embodiment, the second conductive layer 305 is a first plate of a capacitor, and the second conductive layer 305 is isolated and insulated from the first conductive layer 303 by a second dielectric layer 304. The first conductive layer 303 and the third conductive layer 307 are electrically connected to form a second plate of the storage capacitor, and the third dielectric layer 306 and the second dielectric layer 304 form an interpole dielectric of the storage capacitor.
In one possible embodiment, the first conductive layer 303, the second conductive layer 305, or the third conductive layer 307 is made of copper, aluminum, or tungsten.
In this embodiment, the manufacturing method can complete the etching with higher lithography precision under the production condition of using the common photoresist, and the finally manufactured trench has a narrower trench width, which is helpful for increasing the surface area of the capacitor and improving the capacity of the storage capacitor, and reduces the requirement on the lithography precision of the lithography machine on the premise of ensuring the performance of the storage capacitor, thereby reducing the process complexity and the production cost.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (8)

1. A method of manufacturing a storage capacitor, comprising:
providing a semiconductor substrate;
forming a first mask layer on the semiconductor substrate;
etching the first mask layer to form a first groove;
forming a second mask layer positioned at the bottom and the side wall of the first groove and above the first mask layer to form a second groove, wherein the groove width and the groove depth of the second groove are both smaller than those of the first groove;
removing the second mask layer above the first mask layer, the first mask layer and the second mask layer positioned at the bottom of the second groove;
sequentially forming a third mask layer on the remaining second mask layer, a fourth mask layer on the third mask layer and a fifth mask layer on the fourth mask layer;
grinding and thinning the fourth mask layer and the fifth mask layer until the second mask layer is exposed;
removing the second mask layer and the fourth mask layer to form a third groove;
etching the semiconductor substrate by taking the third mask layer, the fourth mask layer and the fifth mask layer around the third groove as barrier layers, and forming a fourth groove in the semiconductor substrate;
removing the third mask layer, the fourth mask layer and the fifth mask layer which are used as barrier layers above the fourth trench;
and forming a dielectric layer and a conductive layer on the fourth groove.
2. The method of claim 1, wherein forming a dielectric layer and a conductive layer over the fourth trench comprises:
forming an insulating layer on the side wall of the fourth groove, the bottom of the fourth groove and the semiconductor substrate;
forming a first dielectric layer on the insulating layer;
forming a first conductive layer on the first dielectric layer;
forming a second dielectric layer on the first conductive layer;
and forming a second conductive layer on the second dielectric layer.
3. The method of claim 2, further comprising:
forming a third dielectric layer on the second conductive layer, and carrying out planarization treatment;
and etching the third dielectric layer to form a through hole so as to expose the first conductive layer and the second conductive layer.
4. The method of claim 3, further comprising:
and filling a third conducting layer in the through hole, and etching the third conducting layer to complete metal interconnection.
5. The method of any of claims 1 to 4, further comprising:
the first mask layer, the second mask layer, the third mask layer, the fourth mask layer and the fifth mask layer are all made of silicon nitride.
6. The method of any of claims 2 to 4, further comprising:
the material of the insulating layer is at least one of materials with dielectric constants larger than 3.9.
7. The method of any of claims 2 to 4, wherein the material of the insulating layer comprises at least one of zirconium dioxide, aluminum oxide, silicon nitride, hafnium oxide, yttrium oxide, silicon dioxide, tantalum pentoxide, lanthanum oxide, and titanium dioxide.
8. The method according to any of claims 2 to 4, wherein the material of the conductive layer is copper, aluminum or tungsten.
CN202210103068.7A 2022-01-27 2022-01-27 Method for manufacturing storage capacitor Pending CN114446782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210103068.7A CN114446782A (en) 2022-01-27 2022-01-27 Method for manufacturing storage capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210103068.7A CN114446782A (en) 2022-01-27 2022-01-27 Method for manufacturing storage capacitor

Publications (1)

Publication Number Publication Date
CN114446782A true CN114446782A (en) 2022-05-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN114446782A (en)

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