CN115148736A

CN115148736A - Semiconductor device and method for fabricating the same

Info

Publication number: CN115148736A
Application number: CN202210657973.7A
Authority: CN
Inventors: 童宇诚; 张钦福
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2022-06-10
Filing date: 2022-06-10
Publication date: 2022-10-04

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The storage node pad and the support structure are arranged on the substrate, and the support structure comprises a first support layer and a second support layer. The capacitor structure is disposed on the substrate and includes a plurality of capacitors. Each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer in sequence, wherein each bottom electrode layer is provided with two parts extending upwards, one of the two parts comprises a first thickness extending between each storage node bonding pad and the first supporting layer and a second thickness extending between the first supporting layer and the second supporting layer, and the first thickness is larger than the second thickness. Therefore, the structural reliability of the storage node can be improved, and the function and the efficiency of the semiconductor device are optimized.

Description

Semiconductor device and method for fabricating the same

Technical Field

The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to a semiconductor memory device and a method of fabricating the same.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For a Dynamic Random Access Memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of a capacitor structure, under the current mainstream development trend, it has gradually replaced a DRAM with a planar gate structure.

Generally, a dram having a recessed gate structure is formed by an array region formed by a large number of memory cells (memory cells) in which information is stored, and each memory cell may be composed of a transistor device and a capacitor device connected in series to receive voltage information from a Word Line (WL) and a Bit Line (BL). In response to product requirements, the density of memory cells in the array region needs to be continuously increased, which results in increasing difficulty and complexity in the related fabrication process and design. Therefore, further improvements are needed in the art or structure to effectively improve the performance and reliability of the related memory device.

Disclosure of Invention

An objective of the present invention is to provide a semiconductor device, in which the bottom electrode layer of a storage node has a uniform thickness and has a structure with a thin top and a thick bottom, so that the bottom electrode layer and/or a capacitor dielectric layer can be effectively prevented from generating a seal to affect the structure and function of the storage node; furthermore, the uniform thickness of the bottom electrode layer can additionally avoid the tip effect and the unstable behavior caused by over-discharge. Therefore, the semiconductor device can improve the structural reliability of the storage node, thereby optimizing the function and the efficiency of the storage node.

To achieve the above objectives, an embodiment of the present invention provides a method for fabricating a semiconductor device, which achieves the effect of enlarging the opening of a storage node by thinning a bottom electrode layer on the upper half portion, so as to prevent the structure and function of the storage node from being affected by a seal generated during the deposition of the bottom electrode layer and/or a capacitor dielectric layer. Thus, even under the premise that the density of the memory cells is continuously improved, the memory node with both structural reliability and device efficiency can be formed.

According to an embodiment of the present invention, a semiconductor device includes a substrate, a storage node pad, a support structure, and a capacitor structure. The storage node bonding pad and the supporting structure are arranged on the substrate, and the supporting structure comprises a first supporting layer and a second supporting layer which are sequentially arranged from bottom to top. The capacitor structure is arranged on the substrate and comprises a plurality of capacitors which are respectively contacted with the storage node bonding pads, and each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are sequentially stacked from bottom to top. Each bottom electrode layer has two parts, one of the two parts respectively comprises a first thickness extending between each storage node bonding pad and the first support layer and a second thickness extending between the first support layer and the second support layer, and the first thickness is larger than the second thickness.

According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes the following steps. Firstly, a substrate is provided, and a storage node bonding pad and a support structure are formed on the substrate, wherein the support structure comprises a first support layer and a second support layer which are sequentially arranged from bottom to top. And then, a capacitor structure is arranged on the substrate, the capacitor structure comprises a plurality of capacitors which are respectively contacted with the storage node bonding pads, and each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are sequentially stacked from bottom to top. Each bottom electrode layer has two parts, one of the two parts comprises a first thickness extending between each storage node bonding pad and the first supporting layer and a second thickness extending between the first supporting layer and the second supporting layer, and the first thickness is larger than the second thickness.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 8 are schematic views illustrating steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, wherein:

FIG. 1 is a cross-sectional view of a semiconductor device after forming a support layer structure according to the present invention;

FIG. 2 is a schematic cross-sectional view of a semiconductor device of the present invention after forming an electrode material layer;

FIG. 3 is a schematic cross-sectional view of a semiconductor device after a first etching process;

FIG. 4 is a schematic cross-sectional view of a semiconductor device after a second etching process;

FIG. 5 is a schematic cross-sectional view of a semiconductor device after a third etching process;

FIG. 6 is a schematic cross-sectional view of a semiconductor device after a thinning process;

FIG. 7 is a cross-sectional view of the semiconductor device of the present invention after the first supporting layer is completely removed; and

fig. 8 is a schematic cross-sectional view of a semiconductor device of the present invention after forming a capacitor structure.

Fig. 9 to 10 are schematic views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein:

fig. 9 is a schematic cross-sectional view of a semiconductor device after a thinning process is performed; and

fig. 10 is a schematic cross-sectional view of a semiconductor device after a capacitor structure is formed.

FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

Wherein the reference numerals are as follows:

100. 300, 500 semiconductor device

101. Insulating region

110. Substrate

130. Dielectric layer

131. Oxide layer

133. Nitride layer

135. Oxide layer

140. Spacer structure

141. First spacer

143. Second spacer

145. Third spacer

150. Contact point

160. Bit line

160a bit line contact

161. Semiconductor layer

163. Barrier layer

165. Conductive layer

167. Cover layer

170. Dielectric layer

180. Storage node pad

190. Supporting layer structure

191. First layer of support material

192. Opening of the container

193. Second support material layer

195. A third support material layer

197. A fourth supporting material layer

200. Layer of electrode material

210. 210a initial bottom electrode layer

211. Section 213

220. Mask pattern

230. 230a bottom electrode layer

231. Section 233

231a, 233a first segment

231b, 233b second fragment

231c third fragment

232. Concave part

240. Capacitor dielectric layer

250. Top electrode layer

260. Capacitor structure

260a capacitor

290. Support structure

291. A first support layer

293. A second supporting layer

330. 330a bottom electrode layer

331. 333 parts

331a, 333a first segment

331b, 333b second fragment

340. Capacitor dielectric layer

350. Top electrode layer

360. Capacitor structure

360a capacitor

390. Support structure

391. A first support layer

393. A second supporting layer

490. Support structure

491. A first support layer

Thickness of T1

T2 first thickness

T3 second thickness

T4 third thickness

P1 first etching manufacturing process

P2 second etching manufacturing process

P3 third etching process

P4 thinning manufacturing process

Detailed Description

In order to make the invention more comprehensible to those skilled in the art, preferred embodiments accompanied with figures are described in detail below. It is to be understood that the embodiments described below may be implemented in various other forms of implementation, which may be substituted, recombined, or mixed with other features of various embodiments without departing from the spirit of the present invention.

Referring to fig. 1 to 9, steps of a method for manufacturing a semiconductor device 100 according to a first embodiment of the invention are shown. First, as shown in fig. 1, a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., siC, siGe, etc.), or a silicon-on-insulator (SOI) substrate, is provided, at least one insulating region 101, such as a Shallow Trench Isolation (STI), is formed in the substrate 110, and a plurality of active areas (AA, not shown) are defined on the substrate 100. In an embodiment, the insulating region 101 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 100 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but not limited thereto.

In addition, a plurality of buried gates (not shown) may be formed in the substrate 110, for example, the buried gates extend parallel to each other along a direction (e.g., x-direction, not shown) and cross the active region to serve as buried word lines (BWLs, not shown) of the semiconductor device 100. A plurality of bit lines 160 and a plurality of contacts 150 are formed over the substrate 110, extending in another direction (e.g., y-direction, not shown) perpendicular to the one direction, and are alternately arranged. Although the overall extension directions of the active region, the buried gate, and the bit line 160 are not specifically shown in the drawings of the present embodiment, it should be easily understood by those skilled in the art that the bit line 160 should be perpendicular to the buried gate and cross the active region and the buried gate from a top view.

In detail, each bit line 160 is formed on the substrate 110 separately from each other and includes a semiconductor layer (e.g., including polysilicon) 161, a barrier layer 163 (e.g., including titanium and/or titanium nitride), a conductive layer 165 (e.g., including low-resistivity metal such as tungsten, aluminum or copper), and a cap layer 167 (e.g., including silicon oxide, silicon nitride or silicon oxynitride), which are stacked in sequence, but not limited thereto. It should be noted that, in principle, all the bitlines 160 are formed on the dielectric layer 130 over the substrate 110 in parallel, wherein the dielectric layer 130 preferably has a composite layer structure, such as, but not limited to, an oxide-nitride-oxide (ONO) structure including an oxide layer 131, a nitride layer 133 and an oxide layer 135. In addition, each bit line 160 extends across a plurality of active regions 101, wherein the bit line 160 crossing each active region 101 may further extend into each active region 101 by a Bit Line Contact (BLC) 160a correspondingly formed thereunder. Note that bit line contacts 160a are formed integrally with semiconductor layer 161 of bit lines 160 and directly contact underlying substrate 110 (each active region 101). On the other hand, the contacts 150 are also formed on the substrate 110 separately from each other and further extend into the active regions 101, so that the contacts 150 can be used as Storage Node Contacts (SNC) of the semiconductor device 300 to directly contact the underlying substrate 110 (including the active regions and the insulating regions 101). In one embodiment, the contacts 150 comprise a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and the contacts 150 and the bit lines 160 are insulated from each other by the spacer structures 140. In one embodiment, the spacer structure 140 may selectively have a single-layer structure or a multi-layer structure as shown in fig. 1, which includes, for example, but not limited to, a first spacer 141 (e.g., comprising silicon nitride), a second spacer 143 (e.g., comprising silicon oxide), and a third spacer 145 (e.g., comprising silicon nitride) sequentially stacked on the sidewalls of each bit line 160.

Referring to fig. 1, a plurality of storage node pads (SN pads) 180 are formed in the dielectric layer 170 on the substrate 110, and are located above the contacts 150 and the bit lines 160 and respectively opposite to the contacts 150. In one embodiment, the storage node pad 180 is also made of a low-resistance metal material such as aluminum, titanium, copper or tungsten, for example, but not limited to, a metal material different from the contact 150. In another embodiment, the storage node pads may also be selected to be integrally formed with the contacts 150 and may comprise the same material. Subsequently, the capacitor structure 260 may be formed over the storage node pad 180 to directly contact and electrically connect to the storage node pad 180 below. In one embodiment, the process for fabricating the capacitor structure 260 includes, but is not limited to, the following steps. First, a support layer structure 190, for example, comprising at least one oxide layer and at least one nitride layer stacked alternately, is formed on the dielectric layer 170 over the substrate 110. In the present embodiment, the support layer structure 190 includes, for example, a first support material layer 191 (e.g., including silicon oxide), a second support material layer 193 (e.g., including silicon nitride or silicon carbonitride), a third support material layer 195 (e.g., including silicon oxide), and a fourth support material layer 197 (e.g., including silicon nitride or silicon carbonitride, etc., but not limited thereto) stacked sequentially from bottom to top, preferably, the oxide layer (e.g., including the first support material layer 191 and the third support material layer 195) may have a relatively large thickness, e.g., about 5 times to 10 times or more of the thickness of the nitride layer (the second support material layer 193 or the fourth support material layer 197), and the thickness of the nitride layer disposed away from the substrate 110 is preferably larger than the thickness of the nitride layer disposed adjacent to the substrate, as shown in fig. 1, but not limited thereto, the thickness of the support layer structure 190 may be about 1600 angstroms (angstroms) to about 2000 angstroms, but not limited thereto, it should be understood by those skilled in the art that the specific stacking number of the oxide layer (such as the first support material layer 191 or the third support material layer 195) and the nitride layer (such as the second support material layer 193 or the fourth support material layer 197) is not limited thereto, and may be adjusted according to actual requirements, such as 3 layers, 4 layers or other numbers, etc., then, a plurality of openings 192 are formed in the support layer structure 190, sequentially penetrate through the fourth support material layer 197, the third support material layer 195, the second support material layer 193 and the first support material layer 191, and corresponding to each storage node pad 180 located therebelow, a top surface of each storage node pad 180 may be exposed from each of the openings 192, respectively, as shown in fig. 1.

Next, as shown in fig. 2, a deposition process is performed on the substrate 110 to form an electrode material layer 200. In detail, the electrode material layer 200 is, for example, formed conformally on the supporting layer structure 190, and sequentially covers the top surface of the fourth supporting material layer 197, the surface of each opening 192, and the top surface of each storage node pad 180, wherein the electrode material layer 200 includes, for example, a low-resistance metal material such as aluminum, titanium, copper, or tungsten, but not limited thereto.

Then, as shown in fig. 3, a first etching process P1, such as a dry etching process, is performed to remove the electrode material layer 200 covering the top surface of the fourth supporting material layer 197, thereby forming a plurality of initial bottom electrode layers 210. The initial bottom electrode layers 210 are formed in the openings 192, respectively, and uniformly cover the top surfaces of the storage node pads 180 and the surfaces of the openings 192, so as to have a uniform thickness T1. In addition, each of the initial bottom electrode layers 210 covers two opposite sidewalls of each of the openings 192 at the same time, so that two portions 211 having the same height in the direction perpendicular to the substrate 110 can be formed. Thus, each of the initial bottom electrode layers 210 may have a left-right symmetric structure, such as a U-shaped structure as shown in fig. 3, but not limited thereto.

As shown in fig. 4, a plurality of mask patterns 220 are formed on the supporting layer structure 190, covering a portion of the fourth supporting material layer 197 and a portion of the opening 192, and a second etching process P2, such as another dry etching process, is performed through the mask patterns 220. In detail, each mask pattern 220 is sequentially formed on the supporting layer structure 190 in a manner of simultaneously covering any one of the openings 192 and the two adjacent openings 192 on the left and right sides of the opening 192 and exposing the other of the openings 192 and the portion of the fourth supporting material layer 197. Thus, by performing the second etching process P2 through the mask pattern 220, the other portion of the fourth supporting material layer 197 exposed by the mask pattern 220, the portions 211 at both sides thereof, and the third supporting material layer 195 below the other portion thereof can be removed, so that the initial bottom electrode layer 210a in each of the other portion openings 192 not covered by the mask pattern 220 can have a portion 213 with a relatively short height (e.g., a height lower than the top surface of the fourth supporting material layer 197) and a portion 211 with a relatively long height, and the entire initial bottom electrode layer 210 in each of the portion openings 192 covered by the mask pattern 220 can have an asymmetric U-shaped structure, and the initial bottom electrode layer 210 in each of the portion openings 192 covered by the mask pattern 220 has two portions 211 with relatively long heights and equal to each other, so that the initial bottom electrode layer still has a left-right symmetric U-shaped structure, as shown in fig. 4. Then, the mask pattern 220 is completely removed.

As shown in fig. 5, a third etching process P3, such as an isotropic wet etching process, is performed to completely remove the third support material layer 195 of the support layer structure 190. In detail, the isotropic wet etching process includes introducing an etchant such as tetramethylammonium hydroxide (TMAH), and removing the remaining third supporting material layer 195 from both sides of the space formed by removing the other portion of the fourth supporting material layer 197 and the third supporting material layer 195 therebelow, but not limited to the etchant. Thus, the two opposite sidewalls of the upper half of the portion 213 of the initial bottom electrode layer 210a can be completely exposed, and the single sidewall of the upper half of the portion 211 of the initial bottom electrode layer 210a can be only partially exposed due to the portion connected to the fourth supporting material layer 197, as shown in fig. 5. On the other hand, the two opposite sidewalls of the other portion 211 of the initial bottom electrode layer 210 on the upper half are also only partially exposed due to the partial connection to the fourth supporting material layer 197. It should be noted that, in the present embodiment, a portion of the initial bottom electrode layer 210a and another portion of the two

portions

211 and 213 of the initial bottom electrode layer 210 higher than the top surface of the second supporting material layer 193, or a portion between the fourth supporting material layer 197 and the second supporting material layer 193 are defined as the upper half; the lower portion of the two

portions

211 and 213 of the initial bottom electrode layer 210 and the other portion of the initial bottom electrode layer 210 below the top surface of the second support material layer 193 or between the second support material layer 193 and the substrate 110 is defined as the lower half, but not limited thereto. In addition, a portion of the initial bottom electrode layer 210a and another portion of the initial bottom electrode layer 210 211 are exposed from two opposite sidewalls of the lower half, and the other sidewall is covered by the second supporting material layer 193 and the first supporting material layer 191, as shown in fig. 5.

After removing the remaining third layer of support material 195, a thinning process P4, such as an isotropic wet etching process, is performed to partially remove the sidewalls exposed by portions of the initial bottom electrode layer 210a and

portions

211, 213 of the initial bottom electrode layer 210, as shown in fig. 6. That is, the etchant of the other isotropic wet etching process partially etches part of the initial bottom electrode layer 210a, another part of the

portions

211 and 213 of the initial bottom electrode layer 210 on the two opposite sidewalls of the upper half and on the single sidewall of the lower half, and the initial bottom electrode layer 210a and another part of the initial bottom electrode layer 210 cover the horizontal portion of each storage node pad 180 to form the thinned bottom electrode layers 230 and 230a, as shown in fig. 6. In other words, the

portions

231, 233 may have different thicknesses due to the presence or absence of the stacked layers of the contact support layer structure 190 on the sidewalls of both sides, which may result in exposure to the etchant.

In detail, the thinned bottom electrode layer 230a still has two

portions

231 and 233 with different heights, wherein the lower portions of the

portions

231 and 233 are both thinned from the original thickness T1 to the first thickness T2 by only one side contacting the etchant, thereby forming first segments 231a and 233a with uniform overall thickness; the upper half portions of the

portions

231 and 233 may be further thinned to a second thickness T3 due to both sides contacting the etchant, thereby forming second segments 231b and 233b having uniform overall thicknesses, respectively, wherein the second thickness T3 of the second segments 231b and 233b is smaller than the first thickness T2 of the first segments 231a and 233 a. On the other hand, the bottom electrode layer 230 of the other part after thinning still has two parts 231 with the same height, wherein the lower half of the part 231 is thinned to the first thickness T2 because only one side contacts the etchant, so as to form a first segment 231a with uniform thickness; the upper half of the portion 231 is also bilaterally contacted with the etchant and is further thinned to a second thickness T3, forming a second segment 231b having a uniform thickness as a whole. It is noted that due to the difference in the degree to which the upper and lower halves of

portions

231 and 233 are thinned, a recess 232 is also formed in the upper half of

portions

231 and 233, which has an overall uniform thickness in a horizontal direction parallel to the surface of substrate 110, as shown in fig. 6. The bottom and top surfaces of the recess 233 are aligned with the top surface of the second supporting material layer 193 and the bottom surface of the fourth supporting material layer 197, respectively. In addition, it should be noted that the upper half of the portion 231 is partially connected to the fourth supporting material layer 197 and is shielded by the fourth supporting material layer 197, so that the upper half of the portion connected to the fourth supporting material layer 197 is also only in single-side contact with the etchant and can have the third thickness T4, thereby forming the third segment 231c with uniform thickness. The third thickness T4 is the same as the first thickness T2, but not limited thereto, and in other embodiments, the third thickness T4 may be greater than the first thickness T2. In other words, the portion 231 is composed of a first segment 231a (first thickness T2 extending from the top surface of each storage node pad 180 to the top surface of the second support material layer 193), a second segment 231b (second thickness T3 extending from the top surface of each second support material layer 193 to the bottom surface of the fourth support material layer 197), and a third segment 231c (third thickness T4 extending from the bottom surface to the top surface of each fourth support material layer 197), which are sequentially stacked, and the portion 233 is composed of a first segment 233a (first thickness T2 extending from the top surface of each storage node pad 180 to the top surface of the second support material layer 193) and a second segment 233b (second thickness T3 extending from the top surface of each second support material layer 193 to beyond the bottom surface of the fourth support material layer 197), which are sequentially stacked, so that the portion 231 may have a relatively large height as a whole with the recess 232 between the third segment 231c and the first segment 231a, while the portion 233 has a relatively small height as a whole with the recess 232 located on the second segment 231b, as shown in fig. 6. Thus, the bottom electrode layer 230a has two

portions

231 and 233 with different heights and thicknesses, thereby forming an asymmetric U-shaped structure as a whole; the bottom electrode layer 230 has two parts 231 with the same height, so that the whole structure is a symmetrical U-shaped structure.

Then, as shown in fig. 7, at least two etching processes are sequentially performed, for example, a dry etching process and an isotropic wet etching process are performed, the second supporting material layer 193 and the first supporting material layer 191 under the other portion of the fourth supporting material layer 197 are removed, and then an etchant such as tetramethylammonium hydroxide is introduced, and the remaining first supporting material layer 191 is continuously removed from both sides of the space formed by removing the second supporting material layer 193 and the first supporting material layer 191, but not limited to the etchant. Thus, the remaining second supporting material layer 193 and the remaining fourth supporting material layer 197 form a first supporting layer 291 and a second supporting layer 293 sequentially from bottom to top, and the first supporting layer 291 and the second supporting layer 293 are disposed at least on one side of each of the bottom electrode layers 230 and 230a to form the supporting structure 290 of the capacitor structure 260. Preferably, the thickness of the second support layer 293 positioned away from the substrate 110 may be greater than the thickness of the first support layer 291 positioned adjacent to the substrate 110, as shown in fig. 7, but not limited thereto.

Subsequently, as shown in fig. 8, a capacitor dielectric layer 240 and a top electrode layer 250 are sequentially formed on each of the bottom electrode layers 230 and 230a, the capacitor dielectric layer 240 conformally covers the bottom electrode layers 230 and 230a and the first supporting layer 291, and the top electrode layer 250 fills the remaining space of each opening 192 and further covers the second supporting layer 293. Wherein a portion of the capacitor dielectric layer 240 and a portion of the top electrode layer 250 may further compriseFilling between the second support layer 293 and the first support layer 291, and filling between the first support layer 291 and the dielectric layer 170. In one embodiment, the capacitor dielectric layer 240 comprises a high-k dielectric material selected from hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO) ₂ ) Titanium oxide (TiO) ₂ ) And zirconia-alumina-zirconia (ZAZ), preferably including zirconia-alumina-zirconia; the top electrode layer 250 comprises a low-resistance metal material such as aluminum, titanium, copper or tungsten, preferably titanium, but not limited thereto.

Thus, the fabrication process of the capacitor structure 260 is completed. The capacitor structure 260 includes a bottom electrode layer 230, a bottom electrode layer 230a, a capacitor dielectric layer 240 and a top electrode layer 250 stacked in sequence, so as to form a plurality of capacitors 260a extending vertically as a Storage Node (SN) of the semiconductor device 100, wherein the storage node can be electrically connected to a transistor element (not shown) of the semiconductor device 100 through a storage node pad 180 and a storage node plug (i.e., a contact 150), so that the capacitor structure 260 and the storage node plug disposed on the substrate 110 can have a good contact relationship. Thus, the semiconductor device 100 of the present embodiment can form a Dynamic Random Access Memory (DRAM) device, in which at least one transistor element and at least one capacitor 260a form a minimum unit cell (memory cell) in a DRAM array to receive voltage information from the bit line 160 and the buried word line.

According to the manufacturing method of the present embodiment, the semiconductor device 100 of the first embodiment of the invention first utilizes the etching process P2 (as shown in fig. 4) to remove the fourth supporting material layer 197 at a specific position, the initial bottom electrode layer 210 at two sides thereof and the third supporting material layer 195 below the initial bottom electrode layer, and then after completely removing the third supporting material layer 195, the thinning process P4 (as shown in fig. 6) is additionally performed, so that all the bottom electrode layers 230 and 230a can be thinned. It should be noted that, the lower half portions of all the bottom electrode layers 230, 230a are only single-side thinned to form the first segments 231a, 233a with the first thickness, and the upper half portions of the bottom electrode layers 230, 230a are at least partially double-side thinned to form the second segments 231b, 233b with the second thickness T3, so that each

bottom electrode layer

230, 230a can respectively present a structure with a thin top and a thick bottom, thereby achieving the effect of enlarging the aperture at the top of each opening 192. In addition, in the present embodiment, the portion 231 of the bottom electrode layer 230a is formed by sequentially stacking a first segment 231a (a first thickness T2, extending between each storage node pad 180 and the first support layer 291) between the first support layer 291 and the substrate 110, a second segment 231b (a second thickness T3, extending between the first support layer 291 and the second support layer 293) between the second support layer 293 and the first support layer 291, and a third segment 231c (a third thickness T4, extending between the bottom surface and the top surface of the second support layer 293) at the sidewall of the second support layer 293, and the portion 233 is formed by sequentially stacking a first segment 233a (a first thickness T2) between the first support layer 291 and the substrate 110, and a second segment 233b (a second thickness T3) between the first support layer 291 and the second support layer 293. Thus, the bottom electrode layer 230a has two

parts

231 and 233 with different heights and thicknesses, so that the whole structure is asymmetric U-shaped; the bottom electrode layer 230 of the other portion has two portions 231 with the same height, so that the whole structure is a symmetrical U-shaped structure, but not limited thereto. In this operation, even though the density of memory cells in the semiconductor device 100 is continuously increased, the problem that the two

portions

231 and 233 merge and even close the opening 192 due to the too narrow aperture at the top of each opening 192 during the deposition of the bottom electrode layers 230 and 230a can be avoided, and the similar problem during the subsequent deposition of the capacitor dielectric layer can be avoided. In addition, the thinned bottom electrode layers 230 and 230a have uniform thickness, thereby avoiding the tip effect and preventing over-discharge from inducing unstable behavior. Thus, the method of fabricating the semiconductor device 100 according to the first embodiment of the present invention can effectively improve the structural reliability of the storage node, thereby optimizing the function and performance of the storage node.

In addition, it should be readily apparent to those skilled in the art that other aspects of the semiconductor device and the method for fabricating the same may be formed without limitation to the above embodiments so as to meet the requirements of practical products. For example, in another embodiment, the first etching process P1 may be omitted, and the electrode material layer 200 covering the top surface of the fourth supporting material layer 197 may be removed in a subsequent etching process (e.g., the second etching process P2 shown in fig. 4 or the third etching process P3 shown in fig. 5). Further embodiments or variations of the method of the semiconductor device of the present invention are described below. For simplicity, the following description mainly refers to the differences between the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 9 to 10, steps of a method for fabricating a semiconductor device 300 according to a second embodiment of the invention are schematically illustrated. The formation steps of the front end of the semiconductor device 300 in this embodiment are substantially the same as the formation steps of the front end of the semiconductor device 100 in the first embodiment, as shown in fig. 1 to 4, and are not repeated herein. The main difference between this embodiment and the first embodiment is that after the semiconductor structure shown in fig. 4 is formed, i.e., after the fourth supporting material layer 197 of the another portion, the portions 211 on both sides thereof, and the third supporting material layer 195 below the another portion are removed, but before the remaining third supporting material layer 195 is removed, a thinning process P4 is performed.

In detail, as shown in fig. 9, after the second etching process P2 is performed and the mask pattern 220 is completely removed, the sidewall exposed by a portion of the initial bottom electrode layer 210a and

portions

211 and 213 of the other portion of the initial bottom electrode layer 210 is thinned by the thinning process P4. It should be noted that after the second etching process P2 is performed, only one side wall of the partial initial bottom electrode layer 210a and two

parts

211, 213 of the other partial initial bottom electrode layer 210 are completely exposed in the two opposite side walls of the lower half, and the other side wall is covered by the first support material layer 191 and the second support material layer 193, in other words, the part 213 of the partial initial bottom electrode layer 210a and the two opposite side walls of the upper half can be completely exposed, and the part 211 of the partial initial bottom electrode layer 210a and the two opposite side walls of the upper half have only one side wall completely exposed, and the other side wall is covered by the third support material layer 195 (refer to fig. 4 of the first embodiment). Thus, the thinning process P4 of the present embodiment, for example, is an isotropic wet etching process, wherein a portion 213 of the initial bottom electrode layer 210a is partially etched on the two opposite sidewalls of the upper half, a portion 211 of the initial bottom electrode layer 210 of the other portion is partially etched on the single-sided sidewall of the upper half, a portion of the initial bottom electrode layer 210a,

portions

211 and 213 of the initial bottom electrode layer 210 of the other portion are partially etched on the single-sided sidewall of the lower half, and the initial bottom electrode layer 210a and the initial bottom electrode layer 210 of the other portion cover the horizontal portion of each storage node pad 180, so as to form thinned bottom electrode layers 330 and 330a, as shown in fig. 9.

As shown in fig. 9, the thinned bottom electrode layer 330a still has two

portions

331 and 333 with different heights and thicknesses, and the whole structure is an asymmetric U-shaped structure. Both the first segments 331a, 333a of the

portions

331 and 333 are only in single-sided contact with the etchant, so as to be thinned from the original thickness T1 to the first thickness T2, and the second segment 331b of the portion 331 is also only in single-sided contact with the etchant and has the same first thickness T2 as the first segments 331a, 333 a. On the other hand, the second segment 333b of the portion 333 may be further thinned to a second thickness T3 due to both sides being exposed to the etchant, the second thickness T3 being smaller than the first thickness T2. In addition, the bottom electrode layer 330 of the other part after thinning still has two parts 331 with the same height, and the whole body presents a symmetrical U-shaped structure, wherein the first part 331a and the second part 331b of the part 331 are only contacted with the etchant unilaterally and are thinned to the first thickness T2. Therefore, the recess 232 in the first embodiment is not formed on the portion 331, so that the thickness can be consistent; while the portion 333 still forms a recess 332 on the second segment 333b, as shown in fig. 9. Then, at least two etching processes are sequentially performed, such as a dry etching process and an isotropic wet etching process, the second supporting material layer 193 and the first supporting material layer 191 under the other portion of the fourth supporting material layer 197 are removed, and then an etchant such as tetramethylammonium hydroxide is introduced, and the remaining third supporting material layer 195 and the remaining first supporting material layer 191 are continuously removed from the space formed by removing the second supporting material layer 193 and the first supporting material layer 191 to both sides, but not limited to the etchant.

Thus, the remaining second supporting material layer 193 and the remaining fourth supporting material layer 197 form a first supporting layer 391 and a second supporting layer 393 sequentially arranged from bottom to top, and the first supporting layer 391 and the second supporting layer 393 are only arranged on one side of each of the bottom electrode layers 330 and 330a to form the supporting structure 390 of the capacitor structure 360 together. Preferably, the thickness of the second support layer 393 positioned away from the substrate 110 may be greater than the thickness of the first support layer 391 positioned adjacent to the substrate, as shown in fig. 10, but not limited thereto.

Subsequently, as shown in fig. 10, a capacitor dielectric layer 340 and a top electrode layer 350 are sequentially formed on each of the bottom electrode layers 330 and 330a, the capacitor dielectric layer 340 commonly covers the bottom electrode layers 330 and 330a and the first supporting layer 391, and the top electrode layer 350 fills the remaining space of each opening 192 and further covers the remaining second supporting layer 393. A portion of the capacitor dielectric layer 340 and a portion of the top electrode layer 350 may further be filled between the second support layer 393 and the first support layer 391, and between the first support layer 391 and the dielectric layer 170. In one embodiment, the materials of the capacitor dielectric layer 340 and/or the top electrode layer 350 are the same as the materials of the capacitor dielectric layer 240 and/or the top electrode layer 250 of the first embodiment, and are not repeated herein.

Thus, the fabrication process of the capacitor structure 360 is completed. The capacitor structure 360 includes a bottom electrode layer 330, a bottom electrode layer 330a, a capacitor dielectric layer 340 and a top electrode layer 350 stacked in sequence, and a plurality of capacitors 360a extending vertically are formed as storage nodes of the semiconductor device 300, which can be electrically connected to transistor elements (not shown) of the semiconductor device 300 through the storage node pads 180 and storage node plugs (i.e., contacts 150), so that the capacitor structure 360 and the storage node plugs disposed on the substrate 110 can have a good contact relationship. Thus, the semiconductor device 300 of the present embodiment can also form a dynamic random access memory device.

According to the manufacturing method of the present embodiment, the semiconductor device 300 according to the second embodiment of the present invention is followed by the etching process P2 and then the thinning process P4 (as shown in fig. 9) to thin all the bottom electrode layers 330, 330a. In the embodiment, the lower half portions of all the bottom electrode layers 330 and 330a are only single-side thinned to form the first segments 331a and 333a with the first thickness T2 being relatively larger, and in part of the bottom electrode layer 330a, the upper half portion of the portion 331 is also only single-side thinned to form the second segment 331b with the first thickness T2 being relatively larger, and the upper half portion of the portion 333 is double-side thinned to form the second segment 333b with the second thickness T3 being relatively smaller, so that one portion 333 of part of the bottom electrode layer 330a can have a structure with a thin top and a thick bottom, thereby achieving the effect of enlarging the aperture at the top of each opening 192 to facilitate the subsequent deposition process, and producing significant benefits for improving the integration level. In addition, when the bottom electrode layer 330a has an asymmetric U-shaped structure, the aperture of the top of each opening 192 can be enlarged more effectively. It should be noted that, when the thinning process P4 of the present embodiment is performed, the remaining third supporting material layer 195 still covers the second section 331b of the portion 331, and herein, the first section 331a and the second section 331b of the portion 331 will be similarly only in single-edge contact with the etchant, and have the first thickness T2 that is uniform throughout without forming the recess 232 of the first embodiment. In this operation, the semiconductor device 300 of the present embodiment can also avoid the problem of merging the two

portions

331 and 333 and even closing the opening 192 due to the too narrow aperture at the top of each opening 192 during the deposition of the bottom electrode layers 330 and 330a on the premise of continuously increasing the density of the memory cells, and meanwhile, only a portion of the bottom electrode layer 330a has an asymmetric U-shaped structure to further avoid affecting the overall capacitance and structural stability. Thus, the method of fabricating the semiconductor device 300 according to the second embodiment of the present invention can also effectively improve the structural reliability of the storage node, thereby optimizing the function and performance of the storage node.

Referring to fig. 11, a cross-sectional view of a semiconductor device 500 according to a third embodiment of the present invention is shown. The structure of the semiconductor device 500 in this embodiment is substantially the same as the structure of the semiconductor device 100 in the first embodiment, as shown in fig. 8, and is not repeated herein. The main difference between this embodiment and the foregoing first embodiment is that the thickness of the first support layer 491 disposed adjacent to the substrate 110 may also be no less than the thickness of the second support layer 293 disposed away from the substrate 110.

In detail, the supporting structure 490 of the present embodiment includes a first supporting layer 491 and a second supporting layer 293 sequentially disposed from bottom to top on at least one side of each of the bottom electrode layers 230 and 230a to support the capacitor structure 260. The thickness of the first supporting layer 491 is equal to that of the second supporting layer 293, for example, so that the first segment 231a (with the first thickness T2) of the portion 231 can further extend from the top surface of each storage node pad 180 to exceed the bottom surface of the first supporting layer 491, as shown in fig. 11, but not limited thereto.

In general, the present invention performs a bottom electrode layer thinning process at a stage of at least partially removing the supporting layer structure from the oxide layer on the upper portion thereof, so as to thin the upper portion of at least one side portion of the bottom electrode layer to a relatively small thickness. Therefore, the partial bottom electrode layer can be in a structure with a thin top and a thick bottom, and the effect of enlarging the capacitor opening is further achieved. Under the operation, the invention can effectively improve the structural reliability of the storage node and optimize the function and the efficiency of the semiconductor device on the premise of continuously improving the density of the storage unit and gradually improving the complexity of the manufacturing process.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor memory device, characterized by comprising:

a substrate;

a plurality of storage node pads disposed on the substrate;

the supporting structure is arranged on the substrate and comprises a first supporting layer and a second supporting layer which are sequentially arranged from bottom to top; and

the capacitor structure is arranged on the substrate and comprises a plurality of capacitors which are respectively contacted with the storage node bonding pads, each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer which are sequentially stacked from bottom to top, each bottom electrode layer comprises two parts extending upwards, one of the two parts respectively comprises a first thickness extending between the storage node bonding pad and the first supporting layer and a second thickness extending between the first supporting layer and the second supporting layer, and the first thickness is larger than the second thickness.

2. The semiconductor memory device according to claim 1, wherein the second thickness extends to be flush with a bottom surface of the second support layer.

3. The semiconductor memory device of claim 2, wherein said one of said two portions further comprises a third thickness extending between said bottom and top surfaces of said second support layer.

4. The semiconductor memory device according to claim 3, wherein the third thickness is the same as the first thickness.

5. The semiconductor memory device according to claim 3, wherein the third thickness is greater than the first thickness.

6. The semiconductor memory device according to claim 3, wherein the two portions have different heights in a direction perpendicular to the substrate.

7. The semiconductor memory device of claim 1, wherein the second thickness extends beyond a bottom surface of the second support layer.

8. The semiconductor memory device according to claim 1, wherein the first thickness extends to a top surface of the first support layer.

9. The semiconductor memory device according to claim 1, wherein the first thickness extends beyond a bottom surface of the first support layer.

10. The semiconductor memory device according to claim 1, wherein the two portions are asymmetrical to each other.

11. The semiconductor memory device according to claim 1, wherein the two portions are symmetrical to each other.

12. A method of fabricating a semiconductor memory device, comprising:

providing a substrate;

forming a plurality of storage node pads on the substrate;

forming a support structure on the substrate, wherein the support structure comprises a first support layer and a second support layer which are sequentially arranged from bottom to top; and

and a capacitor structure on the substrate, the capacitor structure including a plurality of capacitors contacting the storage node pads, each capacitor including a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer stacked in sequence from bottom to top, wherein each bottom electrode layer has two portions extending upward, one of the two portions includes a first thickness extending between each storage node pad and the first support layer and a second thickness extending between the first support layer and the second support layer, and the first thickness is greater than the second thickness.

13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the forming of the support structure further comprises:

forming a first supporting material layer, a second supporting material layer, a third supporting material layer and a fourth supporting material layer which are stacked in sequence on the substrate;

forming a plurality of openings, wherein the openings penetrate through the fourth supporting material layer, the third supporting material layer, the second supporting material layer and the first supporting material layer;

forming a plurality of mask patterns on the fourth support material layer;

removing a portion of the fourth layer of support material and a portion of the third layer of support material through the mask pattern;

removing the mask pattern and the remaining third support material layer;

removing portions of the second layer of support material; and

and completely removing the first support material layer to form the support structure.

14. The method for manufacturing a semiconductor memory device according to claim 13, further comprising:

forming an electrode material layer covering the surface of each opening; and

performing an etching manufacturing process, partially removing the electrode material layer, and forming a plurality of initial bottom electrode layers; and

and thinning the initial bottom electrode layer to form the bottom electrode layer.

15. The method of claim 14, wherein the thinning process is performed after removing the remaining third layer of support material.

16. The method of claim 15, wherein the one of the two portions further comprises a third thickness extending between the bottom and top surfaces of the second support layer, the third thickness being the same as the first thickness.

17. The method of claim 14, wherein the thinning process is performed before removing the remaining third layer of support material.

18. The method of manufacturing a semiconductor memory device according to claim 17, the two portions having different heights in a direction perpendicular to the substrate.

19. The method of claim 14, wherein the portion of the second layer of support material and the portion of the first layer of support material are removed after the thinning process.

20. The method for manufacturing a semiconductor memory device according to claim 14, further comprising:

after the thinning process, the capacitor dielectric layer and the top electrode layer are formed on the bottom electrode layer.