CN110211924B - Method for manufacturing wafer structure - Google Patents
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- CN110211924B CN110211924B CN201910537572.6A CN201910537572A CN110211924B CN 110211924 B CN110211924 B CN 110211924B CN 201910537572 A CN201910537572 A CN 201910537572A CN 110211924 B CN110211924 B CN 110211924B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
Abstract
The application provides a manufacturing method of a wafer structure, after a first wafer and a second wafer are bonded, etching can be carried out from a first substrate of the first wafer to form a silicon through hole, then deposition of an insulating layer is carried out, the thickness of the insulating layer at the opening corner of the silicon through hole is larger than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole, then anisotropic etching of the insulating layer is carried out until the insulating layer on the bottom surface of the silicon through hole is removed, and then filling of the silicon through hole is carried out. The insulating layer in the through silicon via plays a role in isolating and protecting a device, the thickness of the insulating layer at the opening corner of the through silicon via is larger than the thickness of the insulating layer on the side wall and the bottom surface of the through silicon via, and in the subsequent process of removing the insulating layer on the bottom surface of the through silicon via, even if the insulating layer at the opening corner of the through silicon via is lost, the thickness of the insulating layer is not too thin, so that the reliability of the insulating layer in the through silicon via is improved, and the influence of the forming process of the through silicon via on the yield and the performance of the device is.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a method for manufacturing a wafer structure.
Background
With the continuous development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology is widely used, which utilizes wafer level packaging technology to bond wafers with different functions together in a stacked manner, and has the advantages of high performance, low cost and high integration.
In one implementation of the wafer level packaging technology, after two wafers are bonded, vertical interconnection between the wafers is realized Through a Through Silicon Via (TSV), and the TSV is a deep hole process, which is complex and difficult in process, and the reliability of the process affects the yield and performance of the device.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide a method for manufacturing a wafer structure, which improves the reliability of an insulating layer in a through silicon via and reduces the influence of a through silicon via forming process on the yield and performance of a device.
In order to achieve the purpose, the technical scheme is as follows:
the embodiment of the application provides a manufacturing method of a wafer structure, which comprises the following steps:
providing a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer, the front surface of the first wafer is bonded to the front surface of the second wafer, the first wafer comprises a first substrate, a first dielectric layer on the first substrate and a first interconnection layer in the first dielectric layer, and the second wafer comprises a second substrate, a second dielectric layer on the second substrate and a second interconnection layer in the second dielectric layer;
etching from the first substrate to form through silicon vias, wherein the through silicon vias comprise first through silicon vias on the first interconnection layer and/or second through silicon vias on the second interconnection layer;
depositing an insulating layer, wherein the thickness of the insulating layer at the opening corner of the silicon through hole is larger than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole;
carrying out anisotropic etching on the insulating layer until the insulating layer on the bottom surface of the silicon through hole is removed;
and filling the through silicon via.
Optionally, if the first through silicon via does not penetrate to the first interconnect layer, after the removing the insulating layer on the bottom surface of the through silicon via and before the filling of the through silicon via, the method further includes:
continuing etching from the first through silicon via until a first interconnection layer below the first through silicon via is exposed;
if the second through silicon via does not penetrate to the second interconnect layer, after the removing the insulating layer on the bottom surface of the through silicon via and before the filling of the through silicon via, the method further includes:
and continuing etching from the second silicon through hole until the second interconnection layer below the second silicon through hole is exposed.
Optionally, the through silicon vias include the first through silicon via and the second through silicon via, and the etching from the first substrate to form the through silicon via includes:
etching the first substrate on the first interconnection layer and reserving a first dielectric layer with partial thickness to form a first silicon through hole on the first interconnection layer;
and etching the first substrate on the second interconnection layer and reserving a second dielectric layer with partial thickness to form a second silicon through hole on the second interconnection layer.
Optionally, the thickness of the insulating layer on the bottom surface of the through silicon via is greater than the thickness of the insulating layer on the sidewall of the through silicon via.
Optionally, a ratio of a thickness of the insulating layer at the corner of the opening of the through silicon via to a thickness of the insulating layer on the sidewall of the through silicon via ranges from (1.5) to (2.5), and a ratio of a thickness of the insulating layer on the bottom surface of the through silicon via to a thickness of the insulating layer on the sidewall of the through silicon via ranges from (1.2) to (2).
Optionally, the depth range of the through silicon via is 2-4 μm, and the ratio of the thickness of the insulating layer at the opening corner of the through silicon via, the thickness of the insulating layer on the side wall of the through silicon via, and the thickness of the insulating layer on the bottom surface of the through silicon via is 2:1: 1.7; the depth range of the silicon through hole is 6-8 mu m, and the ratio of the thickness of the insulating layer at the opening corner of the silicon through hole, the thickness of the insulating layer on the side wall of the silicon through hole and the thickness of the insulating layer on the bottom surface of the silicon through hole is 2:1: 1.2.
Optionally, after performing the anisotropic etching on the insulating layer, an included angle between an outer edge of the insulating layer on the sidewall of the through silicon via and the sidewall of the through silicon via ranges from 0 ° to 5 °.
Optionally, the insulating layer is a single-layer structure.
Optionally, the insulating layer is a multilayer structure, and a thickness of at least one layer of the multilayer structure at a corner of the opening of the through silicon via is greater than thicknesses of a sidewall and a bottom surface of the through silicon via.
Optionally, at least one layer of the multilayer structure is a skin layer of the multilayer structure, and the other layers of the multilayer structure have a substantially uniform thickness.
The embodiment of the application provides a manufacturing method of a wafer structure, after a first wafer and a second wafer are bonded, etching can be carried out from a first substrate of the first wafer to form a silicon through hole, then deposition of an insulating layer is carried out, the thickness of the insulating layer at the opening corner of the silicon through hole is larger than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole, then anisotropic etching of the insulating layer is carried out until the insulating layer on the bottom surface of the silicon through hole is removed, and then filling of the silicon through hole is carried out. The insulating layer in the through silicon via plays the effect of keeping apart and protection to the device, and the insulating layer thickness of the opening corner of through silicon via is greater than the thickness of the insulating layer on lateral wall and the bottom surface of through silicon via, has strengthened the protection of through silicon via opening corner, avoids in the in-process of follow-up insulating layer of getting rid of on the through silicon via bottom surface, to the too much loss of insulating layer of the opening corner of through silicon via, need not to increase the technology complexity and reduce the through silicon via opening time the while, has improved the reliability of insulating layer in the through silicon via, reduces the formation technology of through silicon via to the influence of device yield and performance.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart illustrating a method of fabricating a wafer structure according to an embodiment of the present disclosure;
fig. 2-10 illustrate schematic cross-sectional views of devices during formation of a wafer structure according to a fabrication method of an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, after bonding two wafers, vertical interconnection between the wafers may be achieved through a through silicon via. For example, after the first wafer and the second wafer are bonded, etching may be performed from the substrate of the first wafer to form a through silicon via exposing the interconnect layers in the first wafer and the second wafer, and the through silicon via may be filled with a metal material, so that vertical interconnection between the interconnect layers in the first wafer and the second wafer is achieved through the metal material in the through silicon via, or electrical connection between the first wafer or the second wafer and an external circuit is achieved.
The through silicon via is usually deep, the forming process is complex and difficult, the reliability of the process often affects the yield and performance of the device, for example, before the through silicon via is filled with metal materials, an insulating layer can be formed on the side wall, so that the isolation protection effect is achieved, the reliability of the device is improved, and meanwhile, the maximum breakdown voltage of the device can be affected by the thickness of the insulating layer at the opening corner of the through silicon via.
However, the inventor of the present invention finds, through research, that in the existing through silicon via process, the deposited insulating layer is uniform, and when the insulating layer at the bottom of the through silicon via is removed by etching, the insulating layer at the corner of the through silicon via opening is greatly worn, so that the insulating layer at the corner of the through silicon via opening is too thin to perform a good isolation protection function, and the performance of the device is affected.
Based on the above technical problem, an embodiment of the present application provides a method for manufacturing a wafer structure, where after a first wafer and a second wafer are bonded, etching may be performed from a first substrate of the first wafer to form a through silicon via, then depositing an insulating layer to make the thickness of the insulating layer at an opening corner of the through silicon via larger than the thickness of the insulating layer on a sidewall and a bottom surface of the through silicon via, then performing anisotropic etching on the insulating layer until the insulating layer on the bottom surface of the through silicon via is removed, and then filling the through silicon via. The insulating layer in the through silicon via plays the effect of keeping apart and protection to the device, and the insulating layer thickness of the opening corner of through silicon via is greater than the thickness of the insulating layer on lateral wall and the bottom surface of through silicon via, has strengthened the protection of through silicon via opening corner, avoids in the in-process of follow-up insulating layer of getting rid of on the through silicon via bottom surface, to the too much loss of insulating layer of the opening corner of through silicon via, need not to increase the technology complexity and reduce the through silicon via opening time the while, has improved the reliability of insulating layer in the through silicon via, reduces the formation technology of through silicon via to the influence of device yield and performance.
For better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the flowchart 1 and fig. 2 to 10.
Referring to fig. 1, a flow chart of a method for manufacturing a wafer structure according to an embodiment of the present application is shown, the method including the following steps:
s101, a wafer bonding structure is provided, the wafer bonding structure includes a first wafer 100 and a second wafer 200, as shown in fig. 2.
In the embodiment of the present application, the first wafer 100 and the second wafer 200 have completed all processes before bonding, and each wafer may have formed thereon a desired device structure and an interconnect layer 130/230 for electrically connecting the device structure, wherein the device structure may be covered by a dielectric layer 120/220, the dielectric layer 120/220 may be a stacked structure and may include an interlayer dielectric layer, an intermetal dielectric layer, a bonding layer, and the like, the interconnect layer 130/230 is formed in the dielectric layer 120/220, the device structure may be a MOS device, a memory device, and/or other passive devices, the memory device may include a non-volatile memory, such as a floating gate field effect transistor, such as a NOR flash memory, a NAND flash memory, or a ferroelectric memory, a phase change memory, and the like, the device structure may be a planar device or a stereo device, the stereoscopic device may be, for example, a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like. The interconnect layer 130/230 may include contact plugs, vias, metal layers, etc., the interconnect layer 130/230 may include one or more layers, and the interconnect layer 130/230 may be a metal material, such as tungsten, aluminum, copper, etc.
In the present embodiment, the device structures on the first wafer 100 and the second wafer 200 may be different, for example, different types of devices or the same type of devices with different operating voltages; the device structures on the same wafer may be the same or different.
For convenience of description, the substrate of the first wafer 100 is referred to as a first substrate 110, the substrate of the second wafer 200 is referred to as a second substrate 210, a surface of the first substrate 110 on which the device structure is formed is a front surface of the first wafer 100, a surface of the second substrate 210 on which the device structure is formed is a front surface of the second wafer 200, a surface opposite to the surface of the first substrate 110 on which the device is formed is a back surface of the first wafer 100, and a surface opposite to the surface of the second substrate 210 on which the device structure is formed is a back surface of the second wafer 200.
The front surfaces of the first wafer 100 and the second wafer 200 may be formed with a material layer for bonding, and the bonding material layer may be an adhesive layer of a dielectric material, such as silicon oxide, silicon nitride, etc., according to different designs and bonding manners, and the bonding between the two wafers is achieved by molecular force between the adhesive layers, and may also be performed by hybrid bonding (hybird bonding), where the front surfaces of the two wafers are formed with an adhesive layer of a dielectric material and a metal bonding hole, and the hybrid bonding between the two wafers is achieved after aligning the bonding holes. The front surfaces of the first wafer 100 and the second wafer 200 are bonded together, the bonded surfaces are bonding surfaces 300 of the two wafers, and the bonding surfaces 300 may be formed by an adhesive layer of a dielectric material or formed by an adhesive layer of a dielectric material and a bonding hole of a metal material according to different bonding modes.
In the embodiment of the present disclosure, the first protective layer 140 may be further formed on the first dielectric layer 120, the second protective layer 240 may be further formed on the second dielectric layer 220, and the first protective layer 140 and the second protective layer 240 may be SiN films. A third dielectric layer and a third interconnect layer in the third dielectric layer (not shown) may also be formed on the first dielectric layer 120, and a fourth dielectric layer and a fourth interconnect layer in the fourth dielectric layer (not shown) may also be formed on the second dielectric layer 220.
S102, etching is performed from the first substrate 110 of the first wafer 100 to form a through silicon via 150/250, as shown in fig. 3.
In this embodiment, the first wafer 100 may serve as an upper wafer in a bonding structure, an etching process may be performed from the first substrate 110 in the first wafer 100 to form a through silicon via 150/250, a through silicon via 150/250 may be formed on the first interconnect layer 130, or may be formed on the second interconnect layer 230, for convenience of description, the through silicon via formed on the first interconnect layer 130 is referred to as a first through silicon via 150, and the through silicon via formed on the second interconnect layer 230 is referred to as a second through silicon via 250.
In particular, whether the through silicon vias include one or both of the first through silicon via 150 and the second through silicon via 250 may be determined according to the bonding manner of the first wafer 100 and the second wafer 200. Specifically, if the first wafer 100 and the second wafer 200 are already interconnected during bonding, and the through silicon vias serve to connect the first wafer 100 and the second wafer 200 with an external circuit, only one of the first through silicon vias 150 and the second through silicon vias 250 needs to be formed, and certainly, two of the first through silicon vias 150 and the second through silicon vias 250 may be formed according to actual needs; if the first wafer 100 and the second wafer 200 are not interconnected during bonding or only partially interconnected, the through-silicon vias serve not only to connect the first wafer 100 and the second wafer 200 to external circuits, but also to interconnect the first wafer 100 and the second wafer 200, and the first through-silicon vias 150 and the second through-silicon vias 250 need to be formed.
Note that, in the embodiment of the present application, the through silicon via 150/250 is a via penetrating at least the first substrate 110. In a specific application, the first through silicon via 150 may penetrate through to the first interconnect layer 130, that is, the bottom of the first through silicon via 150 is the first interconnect layer 130; the first through silicon via 150 may not penetrate to the first interconnect layer 130, that is, the bottom of the first through silicon via 150 is the first dielectric layer 120, and the first dielectric layer 120 may protect the first interconnect layer 130 thereunder in other etching processes. Similarly, the second through silicon via 250 may penetrate to the second interconnect layer 230; the second through silicon via 250 may not penetrate through to the second interconnect layer 230, that is, the bottom of the second through silicon via 250 is the second dielectric layer 220, the fourth dielectric layer or the second protection layer 240, and the second dielectric layer 220, the fourth dielectric layer or the second protection layer 240 may protect the second interconnect layer 230 thereunder in other etching processes.
When the through-silicon vias include the first through-silicon via 150 and the second through-silicon via 250, the first through-silicon via 150 on the first interconnection layer 130 may be formed by etching from the first substrate 110, and then the second through-silicon via 250 on the second interconnection layer 230 may be formed by etching from the second interconnection layer 230 on the first substrate 110; or first, etching is performed on the first interconnection layer 130 and the second interconnection layer 230 from the first substrate 110 to form a first through silicon via 150 on the first interconnection layer 130 and a third through silicon via on the second interconnection layer 230, wherein the depths of the first through silicon via 150 and the third through silicon via are the same, and then etching is performed from the third through silicon via to deepen the third through silicon via, so as to form a second through silicon via 250 on the second interconnection layer 230; it is also possible to etch the second interconnection layer 230 from the first substrate 110 to form the second through-silicon-via 250 on the second interconnection layer 230, and then etch the first interconnection layer 130 from the first substrate 110 to form the first through-silicon-via 150 on the first interconnection layer 130.
In specific implementation, when the first substrate 110 is etched on the first interconnection layer 130, a part of the thickness of the first dielectric layer 120 may be remained, so that a part of the first dielectric layer 120 remains at the bottom of the first through-silicon via 150 on the first interconnection layer 130, and the first dielectric layer 120 at the bottom of the first through-silicon via 150 may play a role in protecting the first interconnection layer 130 therebelow when the second through-silicon via 250 is formed by subsequent etching; when the second substrate 210 is etched on the second interconnection layer 230, a part of the thickness of the second dielectric layer 220, the thickness of the fourth dielectric layer, or the thickness of the second protective layer 240 may also be remained, so that a part of the thickness of the second dielectric layer 220, the thickness of the fourth dielectric layer, or the thickness of the second protective layer 240 remains at the bottom of the second through-silicon via 250 on the second interconnection layer 230, and the second dielectric layer 220, the thickness of the fourth dielectric layer, or the thickness of the second protective layer 240 at the bottom of the second through-silicon via 250 may play a role in protecting the second interconnection layer 230 therebelow when the second through-silicon via 250 is formed by subsequent etching.
S103, an insulating layer 160 is deposited, and the thickness of the insulating layer 160 at the corner of the opening of the through silicon via 150/250 is greater than the thickness of the insulating layer 160 on the sidewall and bottom of the through silicon via 150/250, as shown in FIGS. 4 and 5.
After the formation of the through silicon via 150/250, an insulating material may be deposited such that an insulating layer 160 may be formed in the through silicon via 150/250, as shown with reference to fig. 4, the insulating layer 160 serving as an insulating barrier between subsequently formed fill material and the substrate in the wafer, thereby improving the reliability and performance of the device. The insulating layer 160 may have a single-layer structure, such as silicon nitride, silicon oxide, or silicon oxynitride, or may have a multilayer structure, such as a stack of silicon nitride, silicon oxide, or silicon oxynitride.
In the embodiment of the present application, the thickness of the insulating layer 160 at the corner of the opening of the through silicon via 150/250 is greater than the thickness of the insulating layer 160 on the sidewall and bottom of the through silicon via 150/250, where the thickness of the insulating layer 160 refers to the deposition thickness of the insulating layer 160 and can be represented by the closest distance between the surface of the insulating layer 160 and the underlying substrate or dielectric layer. Referring to fig. 4, there is a raised structure of insulating layer 160 at the open corners of through silicon via 150/250.
The Deposition manner of the insulating layer 160 may be Chemical Vapor Deposition (CVD), the thickness of the formed insulating layer 160 on the sidewall is not uniform, the special morphology of the insulating layer may be controlled by controlling the Deposition parameters of the CVD, and a Deposition process with poor step coverage may be adopted, so that the Deposition speed of the insulating layer 160 is faster, the step coverage is poor, and the thickness of the obtained insulating layer at different positions is not uniform. Specifically, the thickness of the insulating layer 160 on the upper surface of the first substrate 110 is larger, the thickness of the insulating layer 160 is larger at the position where the through-silicon via 150/250 is close to the opening, the thickness of the insulating layer 160 is smaller at the position where the through-silicon via 150/250 is close to the bottom, the thickness of the insulating layer 160 at the bottom of the through-silicon via 150/250 is also smaller, and the thickness of the insulating layer 160 at the corner of the opening of the through-silicon via 150/250 is larger, as shown with reference to fig. 4.
The insulating layer 160 at the corner of the opening of the through silicon via 150/250 may be an arc-shaped protrusion and thus have a greater thickness and a smaller diameter at the opening of the through silicon via 150/250. at a later stage in the deposition process of the insulating layer 160, the insulating layer 160 at the corner of the opening of the through silicon via 150/250 blocks the insulating layer material from entering the interior of the through silicon via 150/250, resulting in a further reduction in the thickness of the insulating layer 160 at locations in the through silicon via 150/250 away from the opening. In the embodiment, when the insulating layer 160 has a single-layer structure, the thickness of the insulating layer 160 at the opening corner of the tsv 150/250 is greater than the thickness of the sidewall and the bottom of the tsv 150/250, and the thickness of the insulating layer 160 at the bottom of the tsv 150/250 is generally smaller.
When the insulating layer 160 is a multi-layer structure, at least one layer of the multi-layer structure has a thickness at the opening corner of the tsv 150/250 greater than the thickness of the sidewall and the bottom of the tsv 150/250, so as to ensure that the thickness of the entire insulating layer 160 at the opening corner of the tsv 150/250 is greater than the thickness of the sidewall and the bottom of the tsv 150/250, and the other layers may have a substantially uniform thickness, so as to ensure that the insulating layer 160 has a desired thickness on the bottom of the tsv 150/250.
For example, at least one layer of the multilayer structure may be a skin layer of the multilayer structure, the other layers than the skin layer having a substantially uniform thickness. Referring to fig. 5, the insulating layer 160 includes a first insulating layer 161 and a second insulating layer 162, wherein the first insulating layer 161 may be silicon oxide and the second insulating layer 162 may be silicon nitride, so that the first insulating layer 161 may have a substantially uniform thickness, the thickness of the second insulating layer 162 at the opening corner of the tsv 150/250 is greater than the thickness of the sidewall and the bottom of the tsv 150/250, and the thickness of the insulating layer 160 formed by the first insulating layer 161 and the second insulating layer 162 at the opening corner is greater than the thickness of the sidewall and the bottom of the tsv 150/250.
In the embodiments of the present application, the thickness of the insulating layer on the bottom surface of the through silicon via 150/250 may be greater than the thickness of the insulating layer on the sidewalls of the through silicon via. In some applications, the ratio of the thickness of insulating layer 160 at the open corner of through-silicon via 150/250 to the thickness of the insulating layer on the sidewall of through-silicon via 150/250 may range from (1.5-2.5); the ratio of the thickness of the insulating layer on the bottom surface of the through-silicon-via to the thickness of the insulating layer on the sidewall of the through-silicon-via is in the range of (1.2-2). In one specific embodiment, the ratio of the thickness of the insulating layer on the sidewalls of the through silicon via 150/250 may be 1.8, 2, or 2.2, and accordingly, the ratio of the thickness of the insulating layer on the bottom surface of the through silicon via to the thickness of the insulating layer on the sidewalls of the through silicon via may be 1.5, 1.7, or 2.
In a particular application, the thickness of the insulating layer on the bottom surface of the through-silicon via 150/250 is related to the depth of the through-silicon via 150/250, and generally speaking, the greater the depth of the through-silicon via 150/250, the smaller the thickness of the insulating layer formed on the bottom surface of the through-silicon via 150/250. In some applications, when the depth of the through silicon via is 2-4 μm, the ratio of the thickness of the insulating layer at the opening corner of the through silicon via, the thickness of the insulating layer on the side wall of the through silicon via and the thickness of the insulating layer on the bottom surface of the through silicon via is 2:1: 1.7; in other applications, the depth of the through-silicon-via is in the range of 6-8 μm, and the ratio of the thickness of the insulating layer at the corner of the opening of the through-silicon-via, the thickness of the insulating layer on the sidewall of the through-silicon-via, and the thickness of the insulating layer on the bottom surface of the through-silicon-via is 2:1: 1.2.
S104, performing anisotropic etching on the insulating layer 160 until the insulating layer 160 on the bottom surface of the through silicon via 150/250 is removed, as shown in fig. 6 and 9.
After depositing the insulating layer 160, the thickness of the insulating layer 160 at the opening corner of the through silicon via 150/250 is greater than the thickness of the sidewall and the bottom of the through silicon via 150/250, and at this time, the anisotropic etching of the insulating layer 160 is performed until the insulating layer 160 on the bottom of the through silicon via 150/250 is removed, thereby exposing the dielectric layer 120/220 or the interconnect layer 130/230 or the fourth dielectric layer or the second passivation layer 240 at the bottom of the through silicon via 150/250.
Referring to fig. 7, if the insulating layer 160 is thinner at the opening corner of the through silicon via 150/250 or the thickness is uniform at all positions, referring to fig. 8, when the insulating layer 160 on the bottom surface of the through silicon via 150/250 is removed, the insulating layer 160 at the opening corner of the through silicon via 150/250 is damaged, resulting in a thinner insulating layer 160 there.
In the embodiment of the present invention, since the insulating layer 160 is thicker at the opening corner of the through silicon via 150/250, when the insulating layer 160 on the bottom surface of the through silicon via 150/250 is removed, even if the insulating layer 160 at the opening corner of the through silicon via 150/250 is damaged, the insulating layer 160 at the opening corner of the through silicon via 150/250 will not be thinned, and the thickness of the insulating layer 160 at the opening corner of the through silicon via 150/250 is still greater than the thickness of the insulating layer on the sidewall of the through silicon via 150/250, as shown in fig. 6, the outer shape of the insulating layer may be a substantially arc-shaped protrusion with a larger curvature, or may be other shapes, which is not limited herein. Meanwhile, the thickness of the insulating layer 160 on the bottom surface of the through silicon via 150/250 is smaller than that of the insulating layer 160 on the opening corner of the through silicon via 150/250, so that the amount of etching is less when the insulating layer 160 on the bottom surface of the through silicon via 150/250 is removed, the etching time is saved, and the damage to the insulating layer 160 at other positions in the etching process is reduced.
After the anisotropic etching of the insulating layer 160, the insulating layer 160 at the bottom of the through silicon via 150/250 is removed, and since the insulating layer 160 is thicker near the opening of the through silicon via 150/250 and thinner near the bottom of the through silicon via 150/250, the included angle between the outer edge of the insulating layer 160 on the sidewall of the remaining through silicon via 150/250 and the sidewall of the through silicon via 150/250 ranges from 0 to 5 °, as shown in fig. 6.
After removing the insulating layer 160 at the bottom of the through silicon via 150/250, if the through silicon via 150/250 does not penetrate to the interconnect layer 130/230, the etching of the through silicon via 150/250 may be continued until the interconnect layer 130/230 is exposed, as shown with reference to fig. 9. Specifically, if the first through-silicon via 150 does not penetrate through the first interconnect layer 130, the etching may be continued from the first through-silicon via 150, for example, the first dielectric layer 130 at the bottom of the first through-silicon via 150 is etched until the first interconnect layer 130 under the first through-silicon via 150 is exposed, and if the second through-silicon via 250 does not penetrate through the second interconnect layer 230, the etching may be continued from the second through-silicon via 250, for example, the second dielectric layer 230, the fourth dielectric layer, or the second protective layer 240 at the bottom of the second through-silicon via 250 is etched until the second interconnect layer 230 under the second through-silicon via 250 is exposed.
S105, the through-silicon via 150/250 is filled, as shown in fig. 10.
After removing the insulating layer 160 at the bottom of the through silicon via 150/250, or after continuing etching from the through silicon via 150/250, the interconnect layer 130/230 under the through silicon via 150/250 may be exposed, e.g., the first interconnect layer 130 is exposed in the first through silicon via 150 and the second interconnect layer 230 is exposed in the second through silicon via 250, at which time the filling of the through silicon via 150/250 may be performed.
Since the through-silicon via 150/250 is used to electrically connect the interconnect layer 130/230 with other components, the filling layer 170 in the through-silicon via 150/250 is made of a conductive material, such as a metal material, e.g., copper, tungsten, etc., after the through-silicon via 150/250 is filled, the filling layer 170 in the through-silicon via 150/250 contacts the interconnect layer 130/230, and the filling layer 170 can electrically connect the wafers or the wafers with an external circuit, e.g., the first interconnect layer 130 in the first wafer 100 and the second interconnect layer 230 in the second wafer 200 can electrically connect the first interconnect layer 130 in the first wafer 100 and the external circuit, or the second interconnect layer 230 in the second wafer 200 and the external circuit can electrically connect.
Before the filling of the through silicon via 150/250, a diffusion barrier 180 may also be formed on the sidewall of the through silicon via 150/250, and then the filling of the through silicon via 150/250 may be performed. Wherein the diffusion barrier 180 may further prevent the filling layer 170 from diffusing, thereby improving the reliability of the device, and specifically, the diffusion barrier 180 may be, for example, a stack of Ti and TiN.
The embodiment of the application provides a manufacturing method of a wafer structure, after a first wafer and a second wafer are bonded, etching can be carried out from a first substrate of the first wafer to form a silicon through hole, then deposition of an insulating layer is carried out, the thickness of the insulating layer at the opening corner of the silicon through hole is larger than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole, then anisotropic etching of the insulating layer is carried out until the insulating layer on the bottom surface of the silicon through hole is removed, and then filling of the silicon through hole is carried out. The insulating layer in the through silicon via plays a role in isolating and protecting a device, the thickness of the insulating layer at the opening corner of the through silicon via is larger than the thickness of the insulating layer on the side wall and the bottom surface of the through silicon via, and in the subsequent process of removing the insulating layer on the bottom surface of the through silicon via, even if the insulating layer at the opening corner of the through silicon via is lost, the thickness of the insulating layer is not too thin, so that the reliability of the insulating layer in the through silicon via is improved, and the influence of the forming process of the through silicon via on the yield and the performance of the device is.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (9)
1. A method of fabricating a wafer structure, comprising:
providing a wafer bonding structure, wherein the wafer bonding structure comprises a first wafer and a second wafer, the front surface of the first wafer is bonded to the front surface of the second wafer, the first wafer comprises a first substrate, a first dielectric layer on the first substrate and a first interconnection layer in the first dielectric layer, and the second wafer comprises a second substrate, a second dielectric layer on the second substrate and a second interconnection layer in the second dielectric layer;
etching from the first substrate to form through silicon vias, wherein the through silicon vias comprise first through silicon vias on the first interconnection layer and/or second through silicon vias on the second interconnection layer;
depositing an insulating layer, wherein the thickness of the insulating layer at the opening corner of the silicon through hole is greater than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole, and the thickness of the insulating layer on the bottom surface of the silicon through hole is greater than the thickness of the insulating layer on the side wall of the silicon through hole;
carrying out anisotropic etching on the insulating layer until the insulating layer on the bottom surface of the silicon through hole is removed;
and filling the through silicon via.
2. The manufacturing method according to claim 1,
if the first through silicon via does not penetrate to the first interconnect layer, after the removing the insulating layer on the bottom surface of the through silicon via and before the filling of the through silicon via, the method further includes:
continuing etching from the first through silicon via until a first interconnection layer below the first through silicon via is exposed;
if the second through silicon via does not penetrate to the second interconnect layer, after the removing the insulating layer on the bottom surface of the through silicon via and before the filling of the through silicon via, the method further includes:
and continuing etching from the second silicon through hole until the second interconnection layer below the second silicon through hole is exposed.
3. The method of manufacturing according to claim 2, wherein the through-silicon-via comprises the first through-silicon-via and the second through-silicon-via, and the etching from the first substrate to form a through-silicon-via comprises:
etching the first substrate on the first interconnection layer and reserving a first dielectric layer with partial thickness to form a first silicon through hole on the first interconnection layer;
and etching the first substrate on the second interconnection layer and reserving a second dielectric layer with partial thickness to form a second silicon through hole on the second interconnection layer.
4. The method of claim 1, wherein a ratio of a thickness of the insulating layer at the corner of the opening of the through silicon via to a thickness of the insulating layer on the sidewall of the through silicon via is in a range of 1.5 to 2.5, and a ratio of a thickness of the insulating layer on the bottom surface of the through silicon via to a thickness of the insulating layer on the sidewall of the through silicon via is in a range of 1.2 to 2.
5. The manufacturing method according to claim 4, wherein the depth of the through silicon via is in a range of 2-4 μm, and the ratio of the thickness of the insulating layer at the opening corner of the through silicon via, the thickness of the insulating layer on the sidewall of the through silicon via and the thickness of the insulating layer on the bottom surface of the through silicon via is 2:1: 1.7; the depth range of the silicon through hole is 6-8 mu m, and the ratio of the thickness of the insulating layer at the opening corner of the silicon through hole, the thickness of the insulating layer on the side wall of the silicon through hole and the thickness of the insulating layer on the bottom surface of the silicon through hole is 2:1: 1.2.
6. The method of claim 1, wherein an angle between an outer edge of the insulating layer on the sidewall of the through-silicon via and the sidewall of the through-silicon via is in a range of 0 to 5 ° after the anisotropic etching of the insulating layer.
7. The manufacturing method according to any one of claims 1 to 6, wherein the insulating layer has a single-layer structure.
8. The method of manufacturing according to any one of claims 1 to 6, wherein the insulating layer is a multilayer structure, and a thickness of at least one layer of the multilayer structure at the opening corner of the through-silicon via is greater than a thickness of a sidewall and a bottom surface of the through-silicon via.
9. The method of manufacturing according to claim 8, wherein at least one layer of the multilayer structure is a skin layer of the multilayer structure and other layers of the multilayer structure have a substantially uniform thickness.
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| CN117855175A (en) * | 2021-08-06 | 2024-04-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN117153780B (en) * | 2023-10-26 | 2024-01-30 | 甬矽电子(宁波)股份有限公司 | Method for producing a through-silicon-via structure and through-silicon-via structure |
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