CN106783646B - Wafer bonding method - Google Patents
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- CN106783646B CN106783646B CN201611191657.6A CN201611191657A CN106783646B CN 106783646 B CN106783646 B CN 106783646B CN 201611191657 A CN201611191657 A CN 201611191657A CN 106783646 B CN106783646 B CN 106783646B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
Abstract
The present invention provides a kind of wafer bonding methods comprising following steps: providing the first wafer and the second wafer；A cyclic annular film layer is formed in the first face isolated edge distance to a declared goal region of the first wafer and/or the first face isolated edge distance to a declared goal region of the second wafer；A planarization layer is formed in the first face of first wafer and the first face of second wafer, planarization layer on planarization layer and/or the second wafer on first wafer connects cyclic annular film layer and constitutes a continuous film layer, and the height of the fringe region of the continuous film layer is not less than the height of its central area；First face in the first face of first wafer and second wafer is staggered relatively, and pressure is applied to first wafer and/or second wafer, to realize the bonding of first wafer and the second wafer.Using wafer bonding method provided by the invention, gap is formed after avoiding wafer bonding or reduces the size in gap after wafer bonding.
Description
Technical field
The present invention relates to semiconductor process technique fields, and in particular to a kind of wafer bonding method.
Background technique
By semicentennial high speed development, microelectric technique and the information technology of microelectric technique is relied on to people
The development of class society produces revolutionary impact.However, now must in face of the problem of be: the physics limit of conventional transistor
It constantly approaches, smaller size of manufacturing technology is more and more difficult, and the investment that the power consumption of integrated circuit constantly increases fab is rapid
It is soaring.In this case, how to continue keep microelectric technique with speed sustainable development described in Moore's Law, at
All making great efforts to solve the problems, such as entire industry today.
The appearance of three dimensional integrated circuits provides a new technology solution for the sustainable development of semiconductor and microelectric technique
Certainly scheme.So-called three dimensional integrated circuits are broadly will have the wafer of integrated circuit to form bonded wafer by bonding technology,
Three-dimensional structure by penetrating wafer interconnects the signal connection realized between multilayer.Three dimensional integrated circuits can be realized smaller core
Piece area, shorter inter-chip interconnection, higher data transfer bandwidth and the heterogeneous of different process technology integrate, thus substantially
Degree reduces chip power-consumption, reduces delay, improves performance, extends function, and to realize that the system on chip (SOC) of sophisticated functions provides
It may.
In three dimensional integrated circuits, wafer and being bonded for wafer are very crucial.Traditional bonding technology the following steps are included:
As shown in Figure 1, providing the first wafer 101 and the second wafer 102；
As shown in Fig. 2, planarization layer 103 is formed on the first face of first wafer 101, in the second wafer 102
Planarization layer 104 is formed on first face, and planarization process is carried out to planarization layer 103,104；
As shown in figure 3, first face in the first face of first wafer 101 and second wafer 102 is staggered relatively,
A pressure is applied to the first wafer 101 and/or the second wafer 102 again, bonding technology can be completed.
Practice discovery, the wafer after bonding often occur edge fall off or wafer on device architecture damage the problem of,
Yield of devices is caused to decline.
Summary of the invention
The object of the present invention is to provide a kind of wafer bonding methods, to avoid forming gap after wafer bonding or subtracting
The size in gap after small wafer bonding.
The present invention provides a kind of wafer bonding methods comprising following steps:
First wafer and the second wafer are provided；
The first face isolated edge distance to a declared goal region of the first wafer and/or the first face isolated edge of the second wafer it is specified away from
A cyclic annular film layer is formed from region；
On the first face of first wafer and one planarization layer of the first face formation of second wafer, the first wafer
Planarization layer and/or the second wafer on planarization layer connect cyclic annular film layer and constitute a continuous film layer, the continuous film layer
The height of fringe region is not less than the height of its central area；
First face in the first face of first wafer and second wafer is staggered relatively, and to first wafer
And/or second wafer applies pressure, to realize the bonding of first wafer and the second wafer.
Optionally, after forming the planarization layer, by the first face of first wafer and second wafer
Before first face is staggered relatively, further includes: carry out flatening process to the planarization layer.
Optionally, the flatening process is CMP process.
Optionally, the cyclic annular film layer on first wafer is formed in from first the first face of wafer edge area 3mm~5mm
Domain, the cyclic annular film layer on second wafer are formed in from second the first face of wafer edge region 3mm~5mm.
Optionally, the planarization layer is identical as the cyclic annular material of film layer.
Optionally, the material of the planarization layer is insulating materials.
Optionally, the material of the cyclic annular film layer is insulating materials.
Optionally, a cyclic annular film layer, the annular membrane are formed in the first face isolated edge distance to a declared goal region of the first wafer
The forming method of layer are as follows:
The central area and edge for blocking the first face of first wafer are not required to form the annular section of ring dress film layer, lead to
It crosses chemical vapor deposition process and forms a cyclic annular film layer in the first face isolated edge distance to a declared goal region of first wafer.
Optionally, a cyclic annular film layer, the annular membrane are formed in the first face isolated edge distance to a declared goal region of the first wafer
The forming method of layer are as follows:
All areas deposition film by chemical vapor deposition process in the first face of first wafer；
The central area in the first face of first wafer is removed by lithography and etching technique and edge is not required to form ring
The film of film layer area is filled, the film in the first face isolated edge distance to a declared goal region of first wafer is retained, described in being formed
Cyclic annular film layer.
Optionally, a cyclic annular film layer, the annular membrane are formed in the first face isolated edge distance to a declared goal region of the second wafer
The forming method of layer are as follows:
The central area and edge for blocking the first face of second wafer are not required to form the annular section of ring dress film layer, lead to
It crosses chemical vapor deposition process and forms a cyclic annular film layer in the first face isolated edge distance to a declared goal region of second wafer.
Optionally, a cyclic annular film layer, the annular membrane are formed in the first face isolated edge distance to a declared goal region of the second wafer
The forming method of layer are as follows:
All areas deposition film by chemical vapor deposition process in the first face of second wafer；
The central area in the first face of second wafer is removed by lithography and etching technique and edge is not required to form ring
The film of film layer area is filled, the film in the first face isolated edge distance to a declared goal region of second wafer is retained, described in being formed
Cyclic annular film layer.
Optionally, first wafer and second wafer are device wafers.
Optionally, the pressure is applied to the center of first wafer and/or second wafer.
The present invention provides a kind of wafer bonding method, first in the first face of the first wafer and/or the first face of the second wafer
Edge form a cyclic annular film layer, then form a planarization in the first face of the first wafer and the first face of second wafer
Layer, the planarization layer connect cyclic annular film layer and constitute a continuous film layer, and the height of the continuous film layer fringe region is not less than it
The height of central area forms gap or reduces wafer bonding back edge gap in this way, can avoid wafer bonding back edge
Size reduces the probability that the film on crystal round fringes is fallen, enters between wafer prevented also from acid solution in subsequent technique along gap
Device architecture is formed and is polluted, the bond strength at the first wafer and the second crystal round fringes is enhanced.
Detailed description of the invention
FIG. 1 to FIG. 3 is the diagrammatic cross-section of the first wafer and the second wafer during traditional wafer bonding；
Fig. 4 is the flow chart for the wafer bonding method that one embodiment of the invention provides；
Fig. 5~Fig. 9 is the section of the first wafer and the second wafer during the wafer bonding that one embodiment of the invention provides
Schematic diagram；
Figure 10 is bowing for the first wafer in the wafer bonding method that one embodiment of the invention provides, after forming ring dress film layer
Depending on schematic diagram；
The description of symbols of attached drawing is as follows:
101, the first wafer of 201-；102, the second wafer of 202-；103,104- planarization layer；The gap 105-；109,110,
209,210- cambered surface；207,208- ring-type film layer；211, the continuous film layer of 212-；α-cambered surface tangent line and vertical direction angle.
Specific embodiment
In the background technology it has been already mentioned that bonding after wafer often occur edge fall off or wafer on device architecture
The problem of damage.Applicants have found that this is because in traditional bonding technology, the first wafer 101 the first face and
When forming planarization layer 103,104 on the first face of the second wafer 202, since marginal deposit rate is lower and crystal round fringes are arc
The influence of shape profile double factor, the thickness closer to the edge planarization layer 103,104 of wafer is also thinner, ultimately forms one
Cambered surface 109,110, and the tangent line of this cambered surface 109,110 and the angle α of vertical direction are larger (as shown in Figure 2).By planarization
After technique, this cambered surface 109,110 is still had, after the completion of leading to bonding technology, the first wafer 101 and second wafer 102
Junction can generate gap 105.Due to the presence in this gap 105, lead to shape on 102 edge of the first wafer 101 and the second wafer
At film be easy to fall.Also, acid solution is easy to enter 101 He of the first wafer along gap 105 in subsequent wet etching technics
Corrode the device architecture on wafer between second wafer 102.In addition, if this gap 105 causes the first wafer 101 and second brilliant
Circle 102 join domains rupture (not contacting) also results in metal and is exposed and causes metallic pollution.
Based on this, the present invention provides a kind of wafer bonding method, first in the first face of the first wafer and/or the second wafer
The edge in the first face forms a cyclic annular film layer, then flat in the first face of the first wafer and the first face formation one of second wafer
Smoothization layer, the planarization layer connect cyclic annular film layer and constitute a continuous film layer, and the height of the continuous film layer fringe region is not low
Height in its central area forms gap or reduces wafer bonding back edge seam in this way, can avoid wafer bonding back edge
The size of gap.
Wafer bonding method proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.Root
According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing be all made of it is very simple
The form of change and use non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
As shown in figure 4, wafer bonding method provided in an embodiment of the present invention the following steps are included:
S1, the first wafer and the second wafer are provided；
S2, refer in the first face isolated edge distance to a declared goal region of the first wafer and/or the first face isolated edge of the second wafer
Set a distance region forms a cyclic annular film layer；
S3, a planarization layer is formed in the first face of first wafer and the first face of second wafer, first is brilliant
Planarization layer on planarization layer and/or the second wafer on circle connects cyclic annular film layer and constitutes a continuous film layer, the continuous film
The height of the fringe region of layer is not less than the height of its central area；
It is S4, first face in the first face of first wafer and second wafer is staggered relatively, and to described first
Wafer and/or second wafer apply pressure, to realize the bonding of first wafer and the second wafer.
As shown in figure 5, it is the schematic diagram of the first wafer 201 and the second wafer 202.In step S1,201 He of the first wafer
Second wafer 202 is for example device wafers, and the device architecture of the device wafers may include well known capacitor, resistance, electricity
One or more in sense, MOS transistor, amplifier or logic circuit.Certainly in practical applications, 201 He of the first wafer
Second wafer 202 or the carrier wafer for being provided with circuit structure, the circuit structure of carrier wafer is for example including capacitor, electricity
The partial circuit of resistance and logic circuit composition.For simplicity, do not represented on the firstth wafer 201 and the second wafer 202 in figure
Device architecture, but those skilled in the art should know.
As shown in fig. 6, it is to be formed with the first wafer 201 of cyclic annular film layer 207 and be formed with the second of cyclic annular film layer 208
The schematic diagram of wafer 202.It the cyclic annular film layer 207 formed on the first wafer 201 in step S2 and is formed on the second wafer 202
Cyclic annular film layer 208 is, for example, insulating materials, more specifically, e.g. silica.Optionally, the cyclic annular formation of film layer 207,208
It is verified in from the region crystal round fringes 3mm~5mm, it is preferable using the cyclic annular film layer effect of above-mentioned size.The ring-type film layer
207,208 thickness can be adjusted according to the thickness of planarization layer, no longer be limited herein, as long as guaranteeing to be subsequently formed continuous
The height of the fringe region of film layer is not less than the height of (being greater than or equal to) its central area.Certainly in practical applications,
The material of cyclic annular film layer is not limited to insulating materials.In addition, (including width, outer edge are apart from crystal round fringes for the size of cyclic annular film layer
Distance etc.) can also be adjusted correspondingly, " fringe region " herein is for " central area " closer to crystalline substance
Circle side, the region on wafer other than " fringe region " can be referred to as " central area ", should " fringe region " be not
In order to limit the specific size and specific location in the region.
In an embodiment of the present invention, the cyclic annular film layer 207 and annular membrane are formed by way of chemical vapor deposition
Layer 208, specifically, blocking the central area of the first wafer 201 when carrying out chemical vapor deposition by device and edge being not required to
Form the annular section of cyclic annular film layer；The central area of the second wafer 202 is blocked by device and edge is not required to form annular membrane
The annular section (as shown in Figure 10) of layer, in this way, only forming annular membrane in 201 first face isolated edge distance to a declared goal of the first wafer
Layer 207,202 first face isolated edge distance to a declared goal of the second wafer is interior to form cyclic annular film layer 208.
In an alternative embodiment of the invention, chemical vapor deposition process can be first passed through in first wafer 201 and second
Film is formed in all areas in the first face of wafer 202, then 201 He of the first wafer is removed by lithography and etching technique
The central area and edge in the first face of the second wafer 202 are not required to form the film of cyclic annular film layer area, retain the first wafer 201
Film in first face isolated edge distance to a declared goal forms cyclic annular film layer 207；It is specified to retain 202 first face isolated edge of the second wafer
Film in distance forms cyclic annular film layer 208.It is preferred that it is brilliant to remove first wafer 201 and second using dry etch process
The central area and edge in the first face of circle 202 are not required to form the film of cyclic annular film layer area, can pass through dry etch process
Parameter adjustment makes the outside cambered surface of the cyclic annular film layer etched close to vertically.
As shown in fig. 7, in step s3, in the first face of the first wafer 201 and each idiomorphism in the first face of the second wafer 202
At a planarization layer, the planarization layer on planarization layer and the second wafer 202 on the first wafer 201 connects cyclic annular film layer and constitutes
One continuous film layer 211,212, the height of the fringe region of the continuous film layer 211,212 are not less than the height of its central area.
The planarization layer can be formed with cyclic annular film layer 207,208 in same cavity.Preferably, the material of planarization layer 211,212 with
Cyclic annular film layer 207,208 is identical, is silica.It is high that the fringe region height of continuous film layer 211,212 is higher than central area
Degree, it is preferred that the edge cambered surface 209,211 of continuous film layer 211,212 still keeps subvertical pattern in previous step.When
So, in practical applications, the generation type and material of the planarization layer 203,204 can also be with cyclic annular film layer 207,208 not phases
Together, it can be formed in different chambers.In addition, in the present embodiment, the edge and the second wafer in the first face of the first wafer 201
The edge in 202 the first face is each formed with cyclic annular film layer, on the planarization layer and the second wafer 202 on the first wafer 201
Planarization layer respectively connects cyclic annular film layer and constitutes continuous film layer.But it in other embodiments, can also be only in the first wafer 201
Cyclic annular film layer is formed on the edge in the first face, alternatively, being only formed with annular membrane on the edge in the first face of the first wafer 202
Layer, can improve the pattern of wafer bonding back edge.
In preferred embodiment, as shown in Figure 8 after step s 3, a flatening process is carried out, the flatening process is for example
It is CMP process, by CMP process to the continuous film layer 211 and the second wafer of the first wafer 201
202 continuous film layer 212 carries out planarization process, may make the first wafer 201 and 202 surface of the second wafer more smooth flat
It is whole, it is ensured that the first wafer with the second wafer in subsequent be bonded, in conjunction with it is even closer.The arc of continuous film layer 211,212 edges
Face still keeps subvertical pattern in previous step.It is understood that the flatening process not has to carry out, such as
The smooth degree on 202 surface of fruit the first wafer 201 and the second wafer can also omit planarization step in technique allowed band
Suddenly.
As shown in figure 9, finally, first face in the first face of first wafer 201 and second wafer 202 is opposite
It places, then applies a pressure in the first wafer 201 and/or the second wafer 202, bonding technology can be completed.It can be and fix
One wafer 201 simultaneously brings pressure to bear on the second wafer 202, alternatively, fix the second wafer 202 and bring pressure to bear on the first wafer 201,
Again alternatively, forcing in the first wafer 201 and the second wafer 202 simultaneously.The position of force is preferably that the first wafer 201 and second is brilliant
The center of circle 202, such bonding effect is more preferably.Finally, the first wafer 201 and the second wafer 202, can be due to intermolecular force
It combines closely.Certainly in practical applications, the position of force can also be according to circumstances adjusted.After completing above-mentioned steps, first
Wafer 201 is completed to be bonded with the second wafer 202.
In conclusion the present invention first forms one at the edge in first face in the first face and/or the second wafer of the first wafer
Cyclic annular film layer, then a planarization layer, the planarization are formed in the first face of the first wafer and the first face of second wafer
Layer connects cyclic annular film layer and constitutes a continuous film layer, and the height of the continuous film layer fringe region is not less than the height of its central area
Degree forms gap or reduces the size in wafer bonding back edge gap, reduces wafer in this way, can avoid wafer bonding back edge
The probability that film on edge is fallen enters between wafer along gap prevented also from acid solution in subsequent technique and is formed to device architecture
Pollution enhances the bond strength at the first wafer and the second crystal round fringes.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (12)
1. a kind of wafer bonding method, which comprises the following steps:
First wafer and the second wafer are provided；
In the first face isolated edge distance to a declared goal region of the first wafer and/or the first face isolated edge distance to a declared goal area of the second wafer
Domain forms a cyclic annular film layer；
A planarization layer is formed in the first face of first wafer and the first face of second wafer, it is flat on the first wafer
Planarization layer on smoothization layer and/or the second wafer connects cyclic annular film layer and constitutes a continuous film layer, the edge of the continuous film layer
The height in region is not less than the height of its central area, and the planarization layer is identical as the cyclic annular material of film layer；
First face in the first face of first wafer and second wafer is staggered relatively, and to first wafer and/
Or second wafer applies pressure, to realize the bonding of first wafer and the second wafer.
2. wafer bonding method as described in claim 1, which is characterized in that, will be described after forming the planarization layer
Before first face of the first wafer and the first face of second wafer are staggered relatively, further includes: carried out to the planarization layer
Flatening process.
3. wafer bonding method as claimed in claim 2, which is characterized in that the flatening process is chemically mechanical polishing work
Skill.
4. wafer bonding method as claimed in claim 1 or 2, which is characterized in that the cyclic annular film layer shape on first wafer
From first the first face of wafer edge region 3mm~5mm, the cyclic annular film layer on second wafer is formed in from the second wafer Cheng Yu
The first face edge region 3mm~5mm.
5. wafer bonding method as described in claim 1, which is characterized in that the material of the planarization layer is insulating materials.
6. wafer bonding method as described in claim 1, which is characterized in that the material of the ring-type film layer is insulating materials.
7. wafer bonding method as claimed in claim 1 or 2, which is characterized in that refer in the first face isolated edge of the first wafer
Set a distance region forms a cyclic annular film layer, the forming method of the ring-type film layer are as follows:
The central area and edge for blocking the first face of first wafer are not required to form the annular section of ring dress film layer, passing through
It learns gas-phase deposition and forms a cyclic annular film layer in the first face isolated edge distance to a declared goal region of first wafer.
8. wafer bonding method as claimed in claim 1 or 2, which is characterized in that refer in the first face isolated edge of the first wafer
Set a distance region forms a cyclic annular film layer, the forming method of the ring-type film layer are as follows:
All areas deposition film by chemical vapor deposition process in the first face of first wafer；
The central area in the first face of first wafer and edge is removed by lithography and etching technique to be not required to form ring dress film
The film of layer region retains the film in the first face isolated edge distance to a declared goal region of first wafer, to form the ring-type
Film layer.
9. wafer bonding method as claimed in claim 1 or 2, which is characterized in that refer in the first face isolated edge of the second wafer
Set a distance region forms a cyclic annular film layer, the forming method of the ring-type film layer are as follows:
The central area and edge for blocking the first face of second wafer are not required to form the annular section of ring dress film layer, passing through
It learns gas-phase deposition and forms a cyclic annular film layer in the first face isolated edge distance to a declared goal region of second wafer.
10. wafer bonding method as claimed in claim 1 or 2, which is characterized in that refer in the first face isolated edge of the second wafer
Set a distance region forms a cyclic annular film layer, the forming method of the ring-type film layer are as follows:
All areas deposition film by chemical vapor deposition process in the first face of second wafer；
The central area in the first face of second wafer and edge is removed by lithography and etching technique to be not required to form ring dress film
The film of layer region retains the film in the first face isolated edge distance to a declared goal region of second wafer, to form the ring-type
Film layer.
11. wafer bonding method as claimed in claim 1 or 2, which is characterized in that first wafer and second wafer
It is device wafers.
12. wafer bonding method as claimed in claim 1 or 2, which is characterized in that the pressure is applied to first wafer
The center of second wafer and/or.
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|---|---|---|---|---|
| CN102034701A (en) * | 2009-09-25 | 2011-04-27 | 无锡华润上华半导体有限公司 | Method for forming dielectric layer and polishing method |
| CN103035580A (en) * | 2012-07-24 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding and dissociating process method applied to thin silicon slices |
| US20160020129A1 (en) * | 2014-07-15 | 2016-01-21 | Micron Technology, Inc. | Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies |
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- 2016-12-21 CN CN201611191657.6A patent/CN106783646B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034701A (en) * | 2009-09-25 | 2011-04-27 | 无锡华润上华半导体有限公司 | Method for forming dielectric layer and polishing method |
| CN103035580A (en) * | 2012-07-24 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding and dissociating process method applied to thin silicon slices |
| US20160020129A1 (en) * | 2014-07-15 | 2016-01-21 | Micron Technology, Inc. | Methods for temporarily bonding a device wafer to a carrier wafer, and related assemblies |
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