CN103107128A - Metal bonding method of three-dimensional chip structure and bonding structure - Google Patents
Metal bonding method of three-dimensional chip structure and bonding structure Download PDFInfo
- Publication number
- CN103107128A CN103107128A CN2013100130617A CN201310013061A CN103107128A CN 103107128 A CN103107128 A CN 103107128A CN 2013100130617 A CN2013100130617 A CN 2013100130617A CN 201310013061 A CN201310013061 A CN 201310013061A CN 103107128 A CN103107128 A CN 103107128A
- Authority
- CN
- China
- Prior art keywords
- chip
- copper
- groove
- silicon dioxide
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to the field of semiconductor fabrication, in particular to a metal bonding method of a three-dimensional chip structure and a bonding structure. The method comprises that copper of a top chip is processed in a chemical machinery planarization mode, a silicon nitride layer is deposited on the surface after being processed in a chemical machinery planarization mode, the silicon nitride layer attached to the copper of the top chip is etched, a groove is formed, the bottom of the groove is the copper of the top chip, copper of a bottom chip is processed in a chemical machinery planarization mode, a bottom silica layer is etched, the copper is enabled to be protruded, activating treatment is carried out to the surface after etch of the copper of the bottom chip is achieved, the copper of the top chip and the copper of the bottom chip are aligned and bonded, and annealing treatment is carried out to the chips after being bonded. According to the metal bonding method of the three-dimensional chip structure and the bonding structure, silicon oxide and silicon nitride are used for being matched with metal and metal bonding, bonding quality is enabled to be better, a silicon nitride layer thin layer can prevent the metal from diffusing into around materials, and goals that a technology process is simplified, temperature needed by bonding is reduced, bonding reliability is improved, bonding efficiency is improved, and bonding cost is reduced can be achieved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, be specifically related to a kind of method and bonding structure of metal bonding of three-dimensional chip structure.
Background technology
The integrated chip of difference in functionality a trend of integrated circuit development together.The large scale integrated circuit manufacturing process is a kind of plane manufacture craft, and it forms a large amount of various types of semiconductor device on same substrate, and is connected to each other to have complete function.At present, great majority are the methods of using TSV what develop.After being about to chip bonding, chip is carried out deep via, by fill the metal part in two chips of metal material connection in deep via.But present this technique is still held in complexity, and reliability is hanged down and the high shortcoming of cost.
Summary of the invention
Method and bonding structure that technical problem to be solved by this invention is to provide a kind of metal bonding of three-dimensional chip structure solve complex process in prior art, and reliability is hanged down and the high problem of cost.
The method and technology scheme that the present invention solves the problems of the technologies described above is as follows: a kind of method of metal bonding of three-dimensional chip structure, step 1, the top chip of described three-dimensional chip is provided with the top chip groove, in described top chip groove and top chip surface all is deposited with copper, chemical mechanical planarization is carried out to exposing top silicon dioxide in the top chip surface that is deposited with copper, and described top chip ditch buried copper is top chip copper;
Step 8 is carried out annealing in process with the chip after bonding.
The invention has the beneficial effects as follows: the present invention realizes the combination of two chips by the method for utilizing at low temperatures metal and metal bonding, come complexed metal and metal bonding to make bonding quality higher with silica and silicon nitride, and the silicon nitride layer film can also stop metal to diffuse in material around, can reach simplification of flowsheet, reduce bonding temperature required, improve bonding reliability, improve bonding efficiency, lower the purpose of bonding cost.
On the basis of technique scheme, the present invention can also do following improvement.
Further, in described step 1, before the copper deposit is carried out on top chip groove and top chip surface, first deposit one deck barrier layer on top chip groove and top chip surface; In described step 4, before the copper deposit is carried out on bottom chip groove and bottom chip surface, first deposit one deck barrier layer on bottom chip groove and bottom chip surface.
Adopt the beneficial effect of above-mentioned further scheme to be: can prevent metal material diffusion towards periphery by this barrier layer, further improve the quality of chip after bonding.
Further, in described step 2, the method for deposit silicon nitride layer is the plasma reinforced chemical vapor deposition method.
Adopt the beneficial effect of above-mentioned further scheme to be: the required silicon nitride layer thickness of deposit comparatively fast, shortened process time, further improve bonding efficiency.
Further, in described step 2, the method for deposit silicon nitride layer is the high-density plasma chemical vapour-phase deposition method.
Adopt the beneficial effect of above-mentioned further scheme to be: can deposit go out the high-quality silicon nitride film, further improve the quality of chip after bonding.
Further, in described step 3, etch silicon nitride layer lithographic method used is high density plasma etch;
The etching mode of further, in described step 3, the silicon dioxide layer on bottom chip being carried out is high density plasma etch.
Adopt the beneficial effect of above-mentioned further scheme to be: the high density plasma etch mode is different phasic property etching, and etching precision is high, and because plasma density is high, etch rate is very fast, can further improve the quality of chip after bonding efficiency and bonding.
the device technique scheme that the present invention solves the problems of the technologies described above is as follows: a kind of metal bond structures of three-dimensional chip, comprise top chip and bottom chip, the top silicon dioxide of described top chip is provided with groove, be provided with top chip copper in described groove, be equipped with silicon nitride layer on bare top silicon dioxide layer segment between institute's groove and groove, described bottom silicon dioxide layer is provided with groove, be provided with bottom chip copper in described groove, the height of described bottom chip copper is higher than bottom silicon dioxide layer, described bottom chip copper is connected with top chip copper, on described top chip, silicon nitride layer is connected with bottom silicon dioxide layer.
The invention has the beneficial effects as follows: the present invention can carry out the incompatible chip bonding purpose that reaches of metal and metallic bond at low temperatures, come complexed metal and metal bonding to make bonding quality higher with silica and silicon nitride, and the silicon nitride layer film can also stop metal to diffuse in material around, reach keying features simple, the effect that reliability is high and cost is low.
On the basis of technique scheme, the present invention can also do following improvement.
Further, be equipped with one deck barrier layer between the top chip copper on described top chip and top silicon dioxide, be provided with one deck barrier layer between the bottom chip copper on described bottom chip and bottom silicon dioxide layer.
Adopt the beneficial effect of above-mentioned further scheme to be: can prevent metal material diffusion towards periphery by this barrier layer, further improve the quality of chip after bonding.
Description of drawings
Fig. 1 is the flow chart of the inventive method;
Fig. 2 is bonding crystal circle structure figure of the present invention;
Fig. 3 is the structure chart that is untreated before the wafer bonding of top in the present invention;
Fig. 4 is structure chart after top wafer deposit silicon nitride layer in the present invention;
Fig. 5 is structure chart after top wafer etch silicon nitride layer in the present invention;
Fig. 6 is the structure chart that is untreated before the bottom wafers bonding in the present invention;
Fig. 7 is to structure chart after the pre-treatment of bottom wafers bonding in invention.
In accompanying drawing, the parts of each label representative are as follows:
1, top chip, 2, top chip copper, 3, silicon nitride layer, 4, bottom chip, 5, bottom metal copper, 6, top silicon dioxide, 7, bottom silicon dioxide layer.
Embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example only is used for explaining the present invention, is not be used to limiting scope of the present invention.
As shown in Figure 1, the flow chart for the inventive method comprises the following steps:
Described step, in 101, before the copper deposit is carried out on top chip groove and top chip 1 surface, first deposit one deck barrier layer on top chip groove and top chip 1 surface; In described step 104, before the copper deposit is carried out on bottom chip groove and bottom chip 4 surfaces, first deposit one deck barrier layer on bottom chip groove and bottom chip 4 surfaces; In described step 102, the method for deposit silicon nitride layer 3 is the plasma reinforced chemical vapor deposition method, in described step 102, the method for deposit silicon nitride layer 3 is the high-density plasma chemical vapour-phase deposition method, etch silicon nitride in described step 103,3 lithographic methods used are high density plasma etch, in described step 103, to bottom silicon dioxide layer, 7 modes of carrying out etching are high density plasma etches.
When described step 101 to step 103 is carried out, simultaneously execution in step 104 is to step 106, or step 104 to step 106 first carries out, and executes rear execution in step 101 to step 103.The making of the making of top chip 1 bonding face and bottom chip 4 bonding faces does not interfere with each other, and can carry out simultaneously, further improves bonding efficiency.
Fig. 2 is bonding crystal circle structure figure of the present invention, comprise top chip 1 and bottom chip 4, the top silicon dioxide 6 of described top chip is provided with groove, be provided with top chip copper 2 in described groove, be equipped with silicon nitride layer 3 on bare top silicon dioxide layer 6 parts between institute's groove and groove, described bottom silicon dioxide layer 7 is provided with groove, be provided with bottom chip copper 5 in described groove, the height of described bottom chip copper 5 is higher than bottom silicon dioxide layer 7, described bottom chip copper 5 is connected with top chip copper 2, on described top chip 1, silicon nitride layer 3 is connected with bottom silicon dioxide layer 7.
Fig. 3 is the structure chart that is untreated before the wafer bonding of top in the present invention, comprises the top silicon dioxide 6 on top chip 1, is embedded in the top chip copper 2 in top silicon dioxide 6.
Fig. 4 is structure chart after top wafer deposit silicon nitride layer in the present invention, comprise the top silicon dioxide 6 on top chip 1, be embedded in top chip copper 2 and the silicon nitride layer 3 that is deposited on top silicon dioxide 6 and top chip copper 2 in top silicon dioxide 6.
Fig. 5 is structure chart after top wafer etch silicon nitride layer in the present invention, comprise the top silicon dioxide 6 on top chip 1, be embedded in top chip copper 2 and the silicon nitride layer 3 that is deposited on top silicon dioxide 6 and top chip copper 2 in top silicon dioxide 6, described silicon nitride layer 3 is provided with the opening identical with top chip copper 2 surface size, and described opening is placed on top chip copper 2.
Fig. 6 is the structure chart that is untreated before the bottom wafers bonding in the present invention, comprises the bottom silicon dioxide layer 7 on bottom chip 6, is embedded in the bottom chip copper 5 in top silicon dioxide 7.
Fig. 7 for the invention in to structure chart after the pre-treatment of bottom wafers bonding, comprise the bottom silicon dioxide layer 7 on bottom chip, be embedded in the bottom chip copper 5 in top silicon dioxide 7, the height of described bottom chip copper 5 is higher than bottom silicon dioxide layer 7.
Be equipped with one deck barrier layer between top chip copper 2 on described top chip 1 and top silicon dioxide 6, be provided with one deck barrier layer between the bottom chip copper 5 on described bottom chip 1 and bottom silicon dioxide layer 7.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. the method for the metal bonding of a three-dimensional chip structure is characterized in that: comprises the following steps,
Step 1, the top chip of described three-dimensional chip is provided with the top chip groove, in described top chip groove and top chip surface all is deposited with copper, chemical mechanical planarization is carried out to exposing top silicon dioxide in the top chip surface that is deposited with copper, and described top chip ditch buried copper is top chip copper;
Step 2, the described top chip surface deposition one deck silicon nitride layer after carrying out chemical-mechanical planarization;
Step 3, etching are attached to the silicon nitride layer of described top chip copper top, form groove, until expose the top chip copper of bottom portion of groove;
Step 4, the bottom chip of described three-dimensional chip is provided with the bottom chip groove, in described bottom chip groove and bottom chip surface all is deposited with copper, chemical mechanical planarization is carried out to exposing bottom silicon dioxide layer in the bottom chip surface that is deposited with copper, and described bottom chip ditch buried copper is bottom chip copper;
Step 5 is carried out etching to bottom chip upper bottom portion silicon dioxide layer and is made bottom chip copper higher than bottom silicon dioxide layer;
Step 6 uses plasma all to carry out activation processing to bottom chip copper and the bottom silicon dioxide layer surface of exposing;
Step 7 is aimed at top chip copper with bottom chip copper, and top chip and bottom chip are carried out bonding;
Step 8 is carried out annealing in process with the chip after bonding.
2. the method for the metal bonding of a kind of three-dimensional chip structure according to claim 1, it is characterized in that: in described step 1, before the copper deposit is carried out on top chip groove and top chip surface, first deposit one deck barrier layer on top chip groove and top chip surface; In described step 4, before the copper deposit is carried out on bottom chip groove and bottom chip surface, first deposit one deck barrier layer on bottom chip groove and bottom chip surface.
3. the method for the metal bonding of a kind of three-dimensional chip structure according to claim 1, it is characterized in that: in described step 2, the method for deposit silicon nitride layer is the plasma reinforced chemical vapor deposition method.
4. the method for the metal bonding of a kind of three-dimensional chip structure according to claim 1, it is characterized in that: in described step 2, the method for deposit silicon nitride layer is the high-density plasma chemical vapour-phase deposition method.
5. the method for the metal bonding of a kind of three-dimensional chip structure according to claim 1, it is characterized in that: in described step 3, etch silicon nitride layer lithographic method used is high density plasma etch.
6. the method for the metal bonding of a kind of three-dimensional chip structure according to claim 1 is characterized in that: the mode of in described step 3, bottom silicon dioxide layer being carried out etching is high density plasma etch.
7. the method for the metal bonding of a three-dimensional chip structure is characterized in that: comprises the following steps,
Step 1, the bottom chip of described three-dimensional chip is provided with the bottom chip groove, in described bottom chip groove and bottom chip surface all is deposited with copper, chemical mechanical planarization is carried out to exposing bottom silicon dioxide layer in the bottom chip surface that is deposited with copper, and described bottom chip ditch buried copper is bottom chip copper;
Step 2 is carried out etching to bottom chip upper bottom portion silicon dioxide layer and is made bottom chip copper higher than bottom silicon dioxide layer;
Step 3 uses plasma all to carry out activation processing to bottom chip copper and the bottom silicon dioxide layer surface of exposing;
Step 4, the top chip of described three-dimensional chip is provided with the top chip groove, in described top chip groove and top chip surface all is deposited with copper, chemical mechanical planarization is carried out to exposing top silicon dioxide in the top chip surface that is deposited with copper, and described top chip ditch buried copper is top chip copper;
Step 5, the described top chip surface deposition one deck silicon nitride layer after carrying out chemical-mechanical planarization;
Step 6, etching are attached to the silicon nitride layer of described top chip copper top, form groove, until expose the top chip copper of bottom portion of groove;
Step 7 is aimed at top chip copper with bottom chip copper, and top chip and bottom chip are carried out bonding;
Step 8 is carried out annealing in process with the chip after bonding.
8. the metal bond structures of a three-dimensional chip, comprise top chip and bottom chip, it is characterized in that: the top silicon dioxide of described top chip is provided with groove, be provided with top chip copper in described groove, be equipped with silicon nitride layer on bare top silicon dioxide layer segment between institute's groove and groove, described bottom silicon dioxide layer is provided with groove, be provided with bottom chip copper in described groove, the height of described bottom chip copper is higher than bottom silicon dioxide layer, described bottom chip copper is connected with top chip copper, on described top chip, silicon nitride layer is connected with bottom silicon dioxide layer.
9. the metal bond structures of a kind of three-dimensional chip according to claim 8 is characterized in that:
Be equipped with one deck barrier layer between top chip copper on described top chip and top silicon dioxide, be provided with one deck barrier layer between the bottom chip copper on described bottom chip and bottom silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310013061.7A CN103107128B (en) | 2013-01-14 | 2013-01-14 | Metal bonding method of three-dimensional chip structure and bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310013061.7A CN103107128B (en) | 2013-01-14 | 2013-01-14 | Metal bonding method of three-dimensional chip structure and bonding structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103107128A true CN103107128A (en) | 2013-05-15 |
| CN103107128B CN103107128B (en) | 2014-12-17 |
Family
ID=48314881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310013061.7A Active CN103107128B (en) | 2013-01-14 | 2013-01-14 | Metal bonding method of three-dimensional chip structure and bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103107128B (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839844A (en) * | 2014-03-10 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Encapsulating method |
| CN104201157A (en) * | 2014-08-08 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | Semiconductor cooling structure and method in hybrid bonding process |
| CN104752239A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method and packaging method |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN105280509A (en) * | 2015-09-10 | 2016-01-27 | 武汉新芯集成电路制造有限公司 | Wafer mixed bonding method based on low melting point copper eutectic metal |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| US9589937B2 (en) | 2014-08-08 | 2017-03-07 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd | Semiconductor cooling method and method of heat dissipation |
| CN107994043A (en) * | 2017-12-11 | 2018-05-04 | 德淮半导体有限公司 | Wafer, stacked semiconductor devices and its manufacture method |
| CN110148603A (en) * | 2019-05-28 | 2019-08-20 | 上海华力微电子有限公司 | The manufacturing method of back-illuminated type CMOS optical sensor |
| CN110429038A (en) * | 2019-08-09 | 2019-11-08 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110739396A (en) * | 2019-11-11 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | chip structures, round crystal structures and manufacturing method thereof |
| CN111162041A (en) * | 2020-01-09 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050042524A1 (en) * | 2003-08-22 | 2005-02-24 | Bellman Robert A. | Process for making hard pellicles |
| JP2005093774A (en) * | 2003-09-18 | 2005-04-07 | Fuji Electric Holdings Co Ltd | Semiconductor device and micro power converting device, and their manufacturing method |
| CN1708840A (en) * | 2002-12-20 | 2005-12-14 | 国际商业机器公司 | Three-dimensional device fabrication method |
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微系统与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
| CN101894816A (en) * | 2009-05-20 | 2010-11-24 | 瑞萨电子株式会社 | Semiconductor device |
| CN102157442A (en) * | 2011-03-08 | 2011-08-17 | 中国科学院微电子研究所 | Method for forming interconnection among microelectronic chips |
| CN102593087A (en) * | 2012-03-01 | 2012-07-18 | 江苏物联网研究发展中心 | Mixed bonding structure for three-dimension integration and bonding method for mixed bonding structure |
| CN203013712U (en) * | 2013-01-14 | 2013-06-19 | 陆伟 | Metal bonding structure of three-dimensional chip |
-
2013
- 2013-01-14 CN CN201310013061.7A patent/CN103107128B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1708840A (en) * | 2002-12-20 | 2005-12-14 | 国际商业机器公司 | Three-dimensional device fabrication method |
| US20050042524A1 (en) * | 2003-08-22 | 2005-02-24 | Bellman Robert A. | Process for making hard pellicles |
| JP2005093774A (en) * | 2003-09-18 | 2005-04-07 | Fuji Electric Holdings Co Ltd | Semiconductor device and micro power converting device, and their manufacturing method |
| CN101894816A (en) * | 2009-05-20 | 2010-11-24 | 瑞萨电子株式会社 | Semiconductor device |
| CN101840856A (en) * | 2010-04-23 | 2010-09-22 | 中国科学院上海微系统与信息技术研究所 | Etch tank adopted in process of packaging and manufacturing TSV (Through Silicon Via) wafer and preparation process |
| CN102157442A (en) * | 2011-03-08 | 2011-08-17 | 中国科学院微电子研究所 | Method for forming interconnection among microelectronic chips |
| CN102593087A (en) * | 2012-03-01 | 2012-07-18 | 江苏物联网研究发展中心 | Mixed bonding structure for three-dimension integration and bonding method for mixed bonding structure |
| CN203013712U (en) * | 2013-01-14 | 2013-06-19 | 陆伟 | Metal bonding structure of three-dimensional chip |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752239A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method and packaging method |
| CN104752239B (en) * | 2013-12-31 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices, preparation method and packaging method |
| CN103839844A (en) * | 2014-03-10 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Encapsulating method |
| CN103839844B (en) * | 2014-03-10 | 2016-09-14 | 上海华虹宏力半导体制造有限公司 | Method for packing |
| CN104201157A (en) * | 2014-08-08 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | Semiconductor cooling structure and method in hybrid bonding process |
| US9589937B2 (en) | 2014-08-08 | 2017-03-07 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd | Semiconductor cooling method and method of heat dissipation |
| CN104201157B (en) * | 2014-08-08 | 2017-12-19 | 武汉新芯集成电路制造有限公司 | Semiconductor heat-dissipating structures and methods in hybrid bonded technique |
| CN105185719B (en) * | 2015-06-24 | 2018-04-17 | 武汉新芯集成电路制造有限公司 | A kind of hybrid bonded method of bayonet type |
| CN105185719A (en) * | 2015-06-24 | 2015-12-23 | 武汉新芯集成电路制造有限公司 | Lock type hybrid bonding method |
| CN105280509A (en) * | 2015-09-10 | 2016-01-27 | 武汉新芯集成电路制造有限公司 | Wafer mixed bonding method based on low melting point copper eutectic metal |
| CN105957836A (en) * | 2016-06-01 | 2016-09-21 | 格科微电子（上海）有限公司 | Fan-out type wafer-level packaging method for semiconductor device |
| CN107994043A (en) * | 2017-12-11 | 2018-05-04 | 德淮半导体有限公司 | Wafer, stacked semiconductor devices and its manufacture method |
| CN110148603A (en) * | 2019-05-28 | 2019-08-20 | 上海华力微电子有限公司 | The manufacturing method of back-illuminated type CMOS optical sensor |
| CN110148603B (en) * | 2019-05-28 | 2021-05-07 | 上海华力微电子有限公司 | Method for manufacturing back-illuminated CMOS optical sensor |
| CN110429038A (en) * | 2019-08-09 | 2019-11-08 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110739396A (en) * | 2019-11-11 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | chip structures, round crystal structures and manufacturing method thereof |
| CN110739396B (en) * | 2019-11-11 | 2023-08-08 | 武汉新芯集成电路制造有限公司 | Chip structure, wafer structure and manufacturing method thereof |
| CN111162041A (en) * | 2020-01-09 | 2020-05-15 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103107128B (en) | 2014-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103107128B (en) | Metal bonding method of three-dimensional chip structure and bonding structure | |
| JP6826214B2 (en) | Die encapsulation in oxide bonded wafer stack | |
| CN105575890B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN103426732B (en) | The method of low-temperature wafer bonding and the structure formed by the method | |
| TW201611186A (en) | Manufacturing method for semiconductor device | |
| US8772125B2 (en) | Method of double-sided patterning | |
| US20120315710A1 (en) | Method for producing reconstituted wafers and method for producing semiconductor devices | |
| CN103367285B (en) | A kind of through-hole structure and preparation method thereof | |
| CN103681390A (en) | TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate | |
| US20200075482A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP2021535608A (en) | Wafer level packaging method and package structure | |
| US20140370703A1 (en) | TSV Front-top Interconnection Process | |
| CN111689460A (en) | Manufacturing method of TSV (through silicon Via) ground interconnection hole structure under silicon cavity in micro-system module | |
| CN108231567A (en) | A kind of brilliant back of the body thining method and used round jig | |
| CN203013712U (en) | Metal bonding structure of three-dimensional chip | |
| CN103390566A (en) | Wafer-level bonding method for three-dimensional integrated packaging technology | |
| CN103066093B (en) | A kind of deep trench isolation manufactures method and the image sensor structure of image sensor | |
| CN103187350B (en) | With silicon wafer attenuation clamp and the reduction process method of the electroplates in hole copper bump | |
| CN104465428A (en) | Copper-copper metal thermal pressing bonding method | |
| CN104952720A (en) | Method for forming height-controllable exposure of electric-conducting poles from back | |
| CN106252276B (en) | Manufacturing method based on TSV technology switch matrix radio frequency unit | |
| US8017497B2 (en) | Method for manufacturing semiconductor | |
| US20160284626A1 (en) | Semiconductor devices having conductive vias and methods of forming the same | |
| TWI606528B (en) | Method for fabricating a semiconductor device | |
| CN104773706A (en) | Preparation method of silicon-based magnetic material substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD. Free format text: FORMER OWNER: LU WEI Effective date: 20130802 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 200124 PUDONG NEW AREA, SHANGHAI TO: 430205 WUHAN, HUBEI PROVINCE |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20130802 Address after: 430205 Wuhan Province, East Lake City Development Zone, No., No. four high road, No. 18 Applicant after: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. Address before: 200124, room 9, No. 905, Lane 301, Haiyang Road, Shanghai, Pudong New Area Applicant before: Lu Wei |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |