CN115623790A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN115623790A CN115623790A CN202110791525.1A CN202110791525A CN115623790A CN 115623790 A CN115623790 A CN 115623790A CN 202110791525 A CN202110791525 A CN 202110791525A CN 115623790 A CN115623790 A CN 115623790A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
The embodiment of the application relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, wherein the substrate comprises a peripheral circuit area, a shallow trench isolation structure is formed in the peripheral circuit area, and a plurality of spaced active areas are isolated in the peripheral circuit area by the shallow trench isolation structure; a silicon nitride filling layer is formed in the shallow trench isolation structure; forming a laminated structure on the active region, wherein the laminated structure comprises a first silicon oxide mask layer and a silicon nitride mask layer, the first silicon oxide mask layer is positioned on the substrate, and the silicon nitride mask layer is positioned on the upper surface of the first silicon oxide mask layer, penetrates through the first silicon oxide mask layer and is contacted with the silicon nitride filling layer; and removing the silicon nitride mask layer and part of the silicon nitride filling layer, so that the upper surface of the silicon nitride filling layer reserved in the shallow trench isolation structure is flush with the upper surface of the substrate. The influence of the surface unevenness of the peripheral circuit area on the electrical performance of the semiconductor structure is eliminated.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof.
Background
A typical memory device includes an array region and a peripheral circuit region, and when an Oxide-Nitride (ON) structure located in a matrix region is formed, in a process of removing the ON structure in the peripheral circuit region, a problem that an upper surface of a silicon Nitride filling layer in a shallow trench isolation structure is higher than an upper surface of a semiconductor device, and a surface of the peripheral circuit region is uneven, so that electrical performance of the semiconductor device is affected may occur.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure and a preparation method thereof, which can optimize the surface flatness of the semiconductor structure.
In one aspect, the present application provides a method for fabricating a semiconductor structure, including:
providing a substrate, wherein the substrate comprises a peripheral circuit area, a shallow trench isolation structure is formed in the peripheral circuit area, and a plurality of spaced active areas are isolated in the peripheral circuit area by the shallow trench isolation structure; a silicon nitride filling layer is formed in the shallow trench isolation structure;
forming a laminated structure on the active region, wherein the laminated structure comprises a first silicon oxide mask layer and a silicon nitride mask layer, the first silicon oxide mask layer is positioned on the substrate, and the silicon nitride mask layer is positioned on the upper surface of the first silicon oxide mask layer, penetrates through the first silicon oxide mask layer and is contacted with the silicon nitride filling layer;
and removing the silicon nitride mask layer and part of the silicon nitride filling layer, so that the upper surface of the silicon nitride filling layer reserved in the shallow trench isolation structure is flush with the upper surface of the substrate.
In one embodiment, the first silicon oxide mask layer is formed using a thermal oxidation process.
In one embodiment, the temperature of the thermal oxidation process is not less than 600 degrees celsius and not greater than 1100 degrees celsius.
In one embodiment, the thickness of the first silicon oxide mask layer is not less than 1 nanometer and not greater than 5 nanometers.
In one embodiment, the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, wherein the width of the first shallow trench isolation structure is smaller than that of the second shallow trench isolation structure; the first shallow trench isolation structure and the second shallow trench isolation structure also comprise a first silicon oxide filling layer, and the first silicon oxide filling layer is positioned between the silicon nitride filling layer and the active region; the second shallow trench isolation structure further comprises a second silicon oxide filling layer, and the second silicon oxide filling layer is located on the surface, far away from the first silicon oxide filling layer, of the silicon nitride filling layer.
In one embodiment, the substrate further comprises an array region, the peripheral circuit region is located at the periphery of the array region, and the laminated structure covers the array region and the peripheral circuit region; removing the silicon nitride mask layer and part of the silicon nitride filling layer comprises the following steps:
forming a graphical mask layer, wherein the graphical mask layer covers the array area;
and sequentially removing the silicon nitride mask layer and part of the silicon nitride filling layer based on the patterned mask layer.
In one embodiment, the removing the silicon nitride mask layer and the partial silicon nitride filling layer in sequence based on the patterned mask layer further comprises:
and removing the patterned mask layer.
In one embodiment, the stacked structure further includes a second silicon dioxide mask layer located on the upper surface of the silicon nitride mask layer;
before removing the silicon nitride mask layer and part of the silicon nitride filling layer, the method further comprises the following steps: removing the second silicon dioxide mask layer positioned in the peripheral circuit area;
after removing the patterned mask layer, the method further comprises the following steps: and removing the second silicon oxide mask layer positioned in the array region and the first silicon oxide mask layer positioned in the peripheral circuit region.
In one embodiment, a silicon nitride mask layer and the second silicon dioxide mask layer are formed by an atomic layer deposition process.
In one embodiment, a first shallow trench isolation structure and a third shallow trench isolation structure are formed in the array region, the width of the third shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, and the third shallow trench isolation structure includes a first silicon oxide filling layer.
In one embodiment, the depth of the first shallow trench isolation structure is the same as the depth of the second shallow trench isolation structure, and both are greater than the depth of the third shallow trench isolation structure.
In one embodiment, the patterned masking layer comprises a patterned photoresist layer.
In one embodiment, the method for manufacturing a semiconductor structure further includes a step of forming a dielectric layer on the upper surface of the substrate, the stacked structure is formed on the upper surface of the dielectric layer, and the silicon nitride mask layer penetrates through the dielectric layer and contacts with the silicon nitride filling layer.
In one embodiment, the dielectric layer comprises a silicon oxide layer.
The application also provides a semiconductor structure which is manufactured by adopting the manufacturing method of any one of the above parts.
The semiconductor structure and the preparation method thereof comprise the steps of providing a substrate comprising a peripheral circuit area, wherein a shallow trench isolation structure is formed in the peripheral circuit area, the shallow trench isolation structure isolates a plurality of active areas which are arranged at intervals in the peripheral circuit area, a silicon oxide filling layer is formed in the shallow trench isolation structure, and a laminated structure on the active area comprises a first silicon oxide mask layer positioned on the substrate and a silicon nitride mask layer positioned on the upper surface of the first silicon oxide mask layer, wherein the silicon nitride mask layer penetrates through the first silicon oxide mask layer and is in contact with the silicon nitride filling layer in the shallow trench isolation structure. When the silicon nitride mask layer is removed, a part of the silicon nitride filling layer with a certain thickness in the shallow trench isolation structure can be removed, so that the upper surface of the residual silicon nitride filling layer in the shallow trench isolation structure is flush with the upper surface of the substrate, a peripheral circuit area with a smooth surface can be obtained after the first oxide mask layer is subsequently removed, and the influence of the unevenness of the surface of the peripheral circuit area on the electrical performance of the semiconductor structure is eliminated.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure before forming a stack structure in one embodiment;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure after a patterned mask layer is formed in accordance with an embodiment of FIG. 2;
FIG. 4 is a schematic flow chart illustrating the removal of the silicon nitride mask layer and a portion of the silicon nitride fill layer in one embodiment;
FIG. 5 is a schematic cross-sectional view of the semiconductor structure of FIG. 3 after removal of a portion of the silicon nitride fill layer;
FIG. 6 is a schematic cross-sectional view of a semiconductor structure after removal of a patterned mask layer, while FIG. 6 is a schematic cross-sectional view of a semiconductor device after removal of a stacked structure of a peripheral circuit region, in accordance with an embodiment;
FIG. 7 is a schematic cross-sectional view of a semiconductor structure after a patterned mask layer is formed in accordance with another embodiment of FIG. 2;
FIG. 8 is a schematic cross-sectional view of the semiconductor structure after the removal of the second silicon dioxide mask layer in the peripheral circuit region in accordance with one embodiment of FIG. 7;
FIG. 9 is a cross-sectional view of the semiconductor structure after the patterned mask layer is removed in accordance with an embodiment of FIG. 8.
Description of reference numerals:
10. a substrate; 100. a peripheral circuit region; 102. a shallow trench isolation structure; 104. an active region; 106. a dielectric layer; 108. a laminated structure; 110. patterning the mask layer; 200. an array region; 202. a first shallow trench isolation structure; 204. a second shallow trench isolation structure; 206. a third shallow trench isolation structure; 208. a first silicon oxide mask layer; 210. a silicon nitride mask layer; 212. a second silicon dioxide mask layer; 302. a first silicon oxide fill layer; 304. a silicon nitride filling layer; 306. a second silicon oxide fill layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
A typical memory device includes an array region and a peripheral circuit region, wherein an Oxide is sequentially covered ON a substrate, and an upper surface of a silicon Nitride filling layer in a shallow trench isolation structure is flush with an upper surface of the Oxide ON the substrate, so that when an Oxide-Nitride (ON) structure located in a matrix region is formed and the ON structure in the peripheral circuit region is removed, the upper surface of the silicon Nitride filling layer in the shallow trench isolation structure is higher than the upper surface of a semiconductor device, and the surface of the peripheral circuit region is uneven, thereby affecting the electrical performance of the semiconductor device.
In order to solve the above problem, in an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, and fig. 1 is a schematic flow chart of the method for manufacturing a semiconductor structure in an embodiment, as shown in fig. 1, the method includes:
s102, providing a substrate 10 including a peripheral circuit region 100, the peripheral circuit region 100 including a shallow trench isolation structure 102 and an active region 104, and a silicon nitride filling layer 304 formed in the shallow trench isolation structure 102.
Specifically, a substrate 10 is provided, the substrate 10 includes a peripheral circuit region 100, a shallow trench isolation structure 102 is formed in the peripheral circuit region 100, and the shallow trench isolation structure 102 isolates a plurality of spaced-apart source regions 104 in the peripheral circuit region 100; a silicon nitride fill layer 304 is formed within the shallow trench isolation structure 102.
S104, a stacked structure 108 is formed on the active region 104, and the silicon nitride mask layer 210 on the stacked structure 108 is in contact with the silicon nitride filling layer 304.
Specifically, a stacked structure 108 is formed on the active region 104, the stacked structure 108 includes a first silicon oxide mask layer 208 and a silicon nitride mask layer 210, the first silicon oxide mask layer 208 is located on the substrate 10, and the silicon nitride mask layer 210 is located on the upper surface of the first silicon oxide mask layer 208, penetrates through the first silicon oxide mask layer 208, and contacts with the silicon nitride filling layer 304; that is, a stacked structure 108 is formed on the peripheral circuit region 100, the stacked structure 108 includes a first silicon oxide mask layer 208 and a silicon nitride mask layer 210 sequentially stacked from the substrate 10 upward (away from the substrate 10), and the silicon nitride mask layer 210 penetrates through the first silicon oxide mask layer 208 contacting with a lower surface thereof and contacts with an upper surface of the silicon nitride filling layer 304 in the shallow trench isolation structure 102.
S106, the silicon nitride mask layer 210 and a portion of the silicon nitride filling layer 304 are removed, such that the upper surface of the silicon nitride filling layer 304 remaining in the shallow trench isolation structure 102 is flush with the upper surface of the substrate 10.
Specifically, the silicon nitride mask layer 210 is in contact with the silicon nitride filling layer 304 in the shallow trench isolation structure 102, and in the process of removing the silicon nitride mask layer 210 on the peripheral circuit region 100 by an etching process, the silicon nitride filling layer 304 which is capable of removing part of the thickness in contact with the silicon nitride mask layer 210 by over-etching is arranged, so that the upper surface of the silicon nitride filling layer 304 remained in the shallow trench isolation structure 102 is flush with the upper surface of the substrate 10; that is, the portion of the silicon nitride filling layer 304 higher than the upper surface of the substrate 10 is removed by over-etching, so as to obtain the peripheral circuit region 100 with a smooth surface after the subsequent removal of the first silicon oxide mask layer 208.
The preparation method of the semiconductor structure comprises the steps of providing a substrate 10 comprising a peripheral circuit area 100, forming a shallow trench isolation structure 102 in the peripheral circuit area 100, isolating a plurality of active areas 104 arranged at intervals in the peripheral circuit area 100 by the shallow trench isolation structure 102, forming a silicon oxide filling layer in the shallow trench isolation structure 102, wherein a laminated structure 108 on the active areas 104 comprises a first silicon oxide mask layer 208 positioned on the substrate 10 and a silicon nitride mask layer 210 positioned on the upper surface of the first silicon oxide mask layer 208, and the silicon nitride mask layer 210 penetrates through the first silicon oxide mask layer 208 and is in contact with the silicon nitride filling layer 304 in the shallow trench isolation structure 102. When the silicon nitride mask layer 210 is removed, a part of the thickness of the silicon nitride filling layer 304 in the shallow trench isolation structure 102 may be removed, so that the upper surface of the remaining silicon nitride filling layer 304 in the shallow trench isolation structure 102 is flush with the upper surface of the substrate 10, and after the first silicon oxide mask layer is subsequently removed, the peripheral circuit region 100 with a smooth surface may be obtained, thereby eliminating the influence of the unevenness of the surface of the peripheral circuit region 100 on the electrical performance of the semiconductor structure.
FIG. 2 is a cross-sectional view of a semiconductor structure prior to forming the stack structure 108 in one embodiment. As shown in fig. 2, in the present embodiment, the substrate 10 further includes an array region 200, the peripheral circuit region 100 is located at the periphery of the array region 200, and the stacked structure 108 covers the array region 200 and the peripheral circuit region 100. The semiconductor structure is composed of an array region 200 and a peripheral circuit region 100, the peripheral circuit region 100 is located at the periphery of the array region 200, for example, at one or more sides of the array region 200, disposed around the array region 200, etc., and a stacked structure 108 formed on the active region 104 covers both the peripheral circuit region 100 and the array region 200; transistors, capacitor arrays, bit line structures, word line structures, etc. in the semiconductor structure are formed in the array region 200, and peripheral structures, such as pad structures, etc. in the semiconductor structure may be formed in the peripheral circuit region 100.
Referring to fig. 2, in one embodiment, the shallow trench isolation structure 102 in the peripheral circuit region 100 includes a first shallow trench isolation structure 202 and a second shallow trench isolation structure 204, and in practical applications, the number of the first shallow trench isolation structure 202 and the second shallow trench isolation structure 204 is set as required, and different active regions 104 arranged at intervals are isolated in the peripheral circuit region 100 by the arrangement of the first shallow trench isolation structure 202 and the second shallow trench isolation structure 204; the first shallow trench isolation structure 202 and the second shallow trench isolation structure 204 both include a first silicon oxide filling layer 302, the first silicon oxide filling layer 302 is located between the silicon nitride filling layer 304 and the active region 104, and an upper surface of the first silicon oxide filling layer 302 is flush with an upper surface of the silicon nitride filling layer 304, that is, the first silicon oxide filling layer 302 is located at the bottom and the side wall of the first shallow trench isolation structure 202 and the second shallow trench isolation structure 204, and a first gap is formed between the first silicon oxide filling layer 302 between the two side walls, and the silicon nitride filling layer 304 is filled in the first gap. Further, a width W1 of the first shallow trench isolation structure 202 along the X direction is smaller than a width W2 of the second shallow trench isolation structure 204 along the X direction, wherein the X direction refers to a connection line direction of the first shallow trench isolation structure 202 and the second shallow trench isolation structure 204, the Y direction refers to a depth direction from the first shallow trench isolation structure 202, and the Y direction is perpendicular to the X direction; typically, when the width W1 of the first shallow trench isolation structure 202 is within a first predetermined range, for example, the width W1 of the first shallow trench isolation structure 202 is greater than the total width of the first silicon oxide filling layer 302 located on the sidewall of the second shallow trench isolation structure 204 along the X direction and is not greater than the total width of the first silicon oxide filling layer 302 and the silicon nitride filling layer 304 located on the sidewall of the second shallow trench isolation structure 204 along the X direction, the silicon nitride filling layer 304 is filled between the first silicon oxide filling layers 302 located on the sidewalls in the first shallow trench isolation structure 202; when the width W2 of the second shallow trench isolation structure 204 is within a second predetermined range, for example, the width W2 of the second shallow trench isolation structure 204 is greater than the total width of the first silicon oxide filling layer 302 and the silicon nitride filling layer 304 located on the sidewall of the second shallow trench isolation structure 204 along the X direction, a second gap is formed between the silicon nitride filling layers 304 filled between the first silicon oxide filling layers 302 located on the sidewall in the second shallow trench isolation structure 204, the second gap is filled with the second silicon oxide filling layer 306, and the upper surface of the second silicon oxide filling layer 306 is flush with the upper surface of the silicon nitride filling layer 304, that is, the upper surfaces of the first silicon oxide filling layer 302, the silicon nitride filling layer 304 and the second silicon oxide filling layer 306 are on the same plane, the second shallow trench isolation structure 204 further includes the second silicon oxide filling layer 306, and the second silicon oxide filling layer 306 is located on the surface of the silicon nitride filling layer 304 away from the first silicon oxide filling layer 302. Furthermore, the upper surfaces of the first filling-up layer 302, the silicon nitride filling-up layer 304 and the second filling-up layer 306 are flush with the upper surface of the substrate 10.
With continued reference to fig. 2, in one embodiment, the first shallow trench isolation structure 202 and the third shallow trench isolation structure 206 are formed in the array region 200, the width of the third shallow trench isolation structure 206 is smaller than the width of the first shallow trench isolation structure 202, the third shallow trench isolation structure 206 includes a first silicon oxide filling layer 302, that is, the first silicon oxide filling layer 302 flush with the upper surface of the substrate 10 is filled in the third shallow trench isolation structure 206, and in practical application, the number of the first shallow trench isolation structure 202 and the third shallow trench isolation structure 206 is set as required. The first and third shallow trench isolation structures (and other shallow trench isolation structures 102) in the array region 200 also isolate a plurality of spaced-apart source regions 104 in the array region 200.
In one embodiment, a second shallow trench isolation structure 204 is also formed in the array region 200. In other embodiments, other shallow trench isolation structures 102 are also formed in the array region 200 according to process requirements.
In one embodiment, a third shallow trench isolation structure 206 is further formed in the peripheral circuit region 100. In other embodiments, other shallow trench isolation structures 102 may be formed in the peripheral circuit region 100 according to process requirements.
In one embodiment, the depth of the first shallow trench isolation structure 202 in the Y direction is the same as the depth of the second shallow trench isolation structure 204 in the Y direction, and is greater than the depth of the third shallow trench isolation structure 206 in the Y direction.
In one embodiment, the width W3 of the third shallow trench isolation structure 206 along the X direction is smaller than the width W1 of the first shallow trench isolation structure 202 along the X direction.
In another embodiment, the depth of the first shallow trench isolation structure 202 in the Y direction is greater than or less than the depth of the second shallow trench isolation structure 204 in the Y direction.
With continued reference to fig. 2, in one embodiment, the method for fabricating a semiconductor structure further includes the step of forming a dielectric layer 106 on the upper surface of the substrate 10. Further, the first shallow trench isolation structure 202, the second shallow trench isolation structure 204, and the third shallow trench isolation structure 206 all penetrate through the dielectric layer 106 and extend into the corresponding active region 104. At this time, the upper surfaces of the first filling-up layer 302, the silicon nitride filling-up layer 304 and the second filling-up layer 306 are flush with the upper surface of the dielectric layer 106.
In one embodiment, dielectric layer 106 comprises a silicon oxide layer.
In one embodiment, the stacked structure 108 is formed on the upper surface of the dielectric layer 106, and the silicon nitride mask layer 210 in the stacked structure 108 is in contact with the silicon nitride filling layer 304 through the dielectric layer 106. Fig. 3 is a cross-sectional view of the semiconductor structure after forming the patterned mask layer 110 in an embodiment corresponding to fig. 2. Referring to fig. 3, in the present embodiment, the stacked structure 108 is formed by a first silicon oxide mask layer 208 and a silicon nitride mask layer 210 stacked in sequence from the substrate 10 upward, and is an ON structure (oxide-nitride structure), compared with the stacked structure 108 being an ONO structure, the array region 200 has an ON structure that needs to be reserved, which simplifies the process steps and reduces the cost. At this time, the forming of the stack structure 108 on the active region 104 specifically includes: first, a first silicon oxide mask layer 208 is formed on the upper surface of the dielectric layer 106 through a film forming process, wherein the first silicon oxide mask layer 208 covers the upper surfaces of the first silicon oxide filling layer 302 and the second silicon oxide filling layer 306 at the same time, and a first trench exposing the silicon nitride filling layer 304 is formed in the first silicon oxide mask layer 208. Next, a silicon nitride mask layer 210 is formed on the upper surface of the first silicon oxide mask layer 208, the silicon nitride mask layer 210 fills the first trench and contacts the silicon nitride filling layer 304, and the silicon nitride mask layer 210 with a flat surface is obtained after planarization processing is performed through a chemical polishing process. When the silicon nitride mask layer 210 is removed by etching, the partial thickness of the silicon nitride filling layer 304 in contact with the silicon nitride mask layer 210 may be removed by increasing the process time for etching the silicon nitride mask layer 210, that is, the partial thickness of the silicon nitride filling layer 304 in contact with the silicon nitride mask layer 210, which is higher than the upper surface of the substrate 10, may be removed by increasing the process time for etching the silicon nitride mask layer 210, so that the upper surface of the remaining silicon nitride filling layer 304 is flush with the upper surface of the substrate 10.
In one embodiment, the first silicon oxide mask layer 208 is formed using a thermal oxidation process. In this way, the first silicon oxide mask layer 208 formed on the upper surface of the dielectric layer 106 exposes the silicon nitride filling layer 304 flush with the dielectric layer 106, i.e., a first trench exposing the silicon nitride filling layer 304 is formed in the first silicon oxide mask layer 208.
In one embodiment, the temperature of the thermal oxidation process is not less than 600 degrees celsius and not greater than 1100 degrees celsius, such as 650 degrees celsius, 700 degrees celsius, 750 degrees celsius, 800 degrees celsius, 900 degrees celsius, 1000 degrees celsius, or the like.
In one embodiment, the thickness of the first silicon oxide mask layer 208 is not less than 1 nm and not greater than 5 nm, such as 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, etc.
In another embodiment, the total thickness of the first silicon oxide mask layer 208 and the dielectric layer 106 is not less than 1 nm and not more than 5 nm, such as 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, etc.
Fig. 4 is a schematic flow chart illustrating the removal of the silicon nitride mask layer 210 and a portion of the silicon nitride fill layer 304 according to an embodiment. As shown in fig. 3 and 4, in the present embodiment, the removing the silicon nitride mask layer 210 and the partial silicon nitride filling layer 304 includes:
s202, forming a patterned mask layer 110, wherein the patterned mask layer 110 covers the array region 200;
specifically, a patterned mask layer 110 is formed on the substrate 10, and the patterned mask layer 110 covers the stacked structure 108 that needs to be retained in the array region 200 and exposes the stacked structure 108 that needs to be removed in the peripheral circuit region 100. Further, the patterned mask layer 110 covers the upper surface of the stacked structure 108 to be remained in the array region 200. As shown in fig. 3, the stacked structure 108 is an ON structure, and the patterned mask layer 110 covers the upper surface of the silicon nitride mask layer 210 required to be remained in the array region 200. Further, patterned masking layer 110 includes a patterned photoresist layer.
S204, the silicon nitride mask layer 210 and a portion of the silicon nitride filling layer 304 are sequentially removed based on the patterned mask layer 110.
Fig. 5 is a cross-sectional view of the semiconductor structure after removing a portion of the silicon nitride fill layer 304 in accordance with an embodiment of fig. 3. As shown in fig. 5, specifically, the patterned mask layer 110 is used as a mask, a first etching process is performed to etch and remove the silicon nitride mask layer 210 exposed by the patterned mask layer 110, and then the silicon nitride filling layer 304 higher than the upper surface of the substrate 10 is etched and removed by an over-etching process (increasing the process time of the first etching process), so that the upper surface of the remaining silicon nitride filling layer 304 is flush with the upper surface of the substrate 10, wherein the rate of etching the silicon nitride mask layer 210 and the silicon nitride filling layer 304 by the first etching process is greater than the rate of etching the first silicon oxide mask layer 208 and greater than the rate of etching the patterned mask layer 110.
Further, step S204 is followed by a step of removing the first silicon oxide mask layer 208 based on the patterned mask layer 110. Fig. 6 is a cross-sectional view of the semiconductor structure after removal of patterned masking layer 110, in accordance with an embodiment. Referring to fig. 6, after step S204, a second etching process is performed to remove the first silicon oxide mask layer 208 exposed by the patterned mask layer 110 by etching, with the patterned mask layer 110 as a mask, wherein a rate of etching the first silicon oxide mask layer 208 by the second etching process is greater than a rate of etching the patterned mask layer 110 and greater than a rate of etching the silicon nitride filling layer 304. Further, when the dielectric layer 106 is formed on the surface of the substrate 10, the removing the first silicon oxide mask layer 208 based on the patterned mask layer 110 further includes: dielectric layer 106 is removed based on patterned masking layer 110. It is understood that when the material of the dielectric layer 106 is a silicon dioxide layer, the dielectric layer 106 and the first silicon oxide mask layer 208 may be removed simultaneously by increasing the process time of the second etching process. During the etching of the dielectric layer 106, the portion of the first silicon oxide filling layer 302 higher than the substrate 10 and the portion of the second silicon oxide filling layer 306 higher than the substrate 10 (if the second silicon oxide filling layer 306 is present) are etched and removed simultaneously.
With continued reference to fig. 6, in one embodiment, the removing the silicon nitride mask layer 210 and the portion of the silicon nitride fill layer 304 in sequence based on the patterned mask layer 110 further comprises: patterned masking layer 110 is removed. Further, when the stacked structure 108 is a structure (e.g., an ON structure) that needs to be formed in the area covered by the patterned mask layer 110 (the array area 200), the silicon nitride mask layer 210 and a portion of the silicon nitride filling layer 304 are sequentially removed by using the patterned mask layer 110 as a mask, and the patterned mask layer 110 is removed after the peripheral circuit area 100 exposed by the patterned mask layer 110 exposes the upper surface of the substrate 10. Still further, after removing the dielectric layer 106, removing the portion of the first silicon oxide filling layer 302 higher than the substrate 10, and removing the portion of the second silicon oxide filling layer 306 higher than the substrate 10, the patterned mask layer 110 is removed. Further, while the silicon nitride mask layer 210, a portion of the silicon nitride filling layer 304, the first silicon oxide mask layer 208, and the dielectric layer 106 (if the dielectric layer 106 is present) are sequentially removed based on the patterned mask layer 110, the patterned mask layer is removed, that is, while the silicon nitride mask layer 210, a portion of the silicon nitride filling layer 304, the first silicon oxide mask layer 208, and the dielectric layer 106 (if the dielectric layer 106 is present) are sequentially removed based on the patterned mask layer 110, the patterned mask layer covering region exposes the upper surface of the stacked structure 108 (the silicon nitride mask layer 210 in the array region 200).
In one embodiment, the stacked structure 108 further comprises a second silicon dioxide mask layer 212 on the upper surface of the silicon nitride mask layer 210; before removing the silicon nitride mask layer 210 and the part of the silicon nitride filling layer 304, the method further comprises: removing the second silicon dioxide mask layer 212 in the peripheral circuit region 100; removing the patterned mask layer 110 further comprises: the second silicon oxide mask layer 212 in the array region 200 and the first silicon oxide mask layer 208 in the peripheral circuitry region 100 are removed.
Specifically, fig. 7 is a schematic cross-sectional view of the semiconductor structure after forming a patterned mask layer 110 according to another embodiment of fig. 2. Fig. 8 is a cross-sectional view of the semiconductor structure after the second silicon dioxide mask layer 212 in the peripheral circuit region 100 is removed in an embodiment corresponding to fig. 7. As shown in fig. 7, the stacked structure 108 is formed by sequentially stacking a first silicon oxide mask layer 208, a silicon nitride mask layer 210, and a second silicon oxide mask layer 212 from the substrate 10 upward, and is an ONO (oxide-nitride-oxide) structure, and the patterned mask layer 110 covers the upper surface of the second silicon oxide mask layer 212 that needs to be remained in the array region 200. At this time, the forming of the stack structure 108 on the active region 104 specifically includes: first, a first silicon oxide mask layer 208 is formed on the upper surface of the dielectric layer 106 through a film forming process, the first silicon oxide mask layer 208 covers the upper surfaces of the first silicon oxide filling layer 302 and the second silicon oxide filling layer 306 at the same time, and a first trench exposing the silicon nitride filling layer 304 is formed in the first silicon oxide mask layer 208. Next, a silicon nitride mask layer 210 is formed on the upper surface of the first silicon oxide mask layer 208, the silicon nitride mask layer 210 fills the first trench and contacts the silicon nitride filling layer 304, and the silicon nitride mask layer 210 with a flat surface is obtained after planarization processing is performed through a chemical polishing process. Third, a second silicon dioxide mask layer 212 is formed on the upper surface of the silicon nitride mask layer 210, and when the silicon nitride mask layer 210 is removed by etching, the silicon nitride filling layer 304 with a partial thickness contacting with the silicon nitride mask layer 210 can be removed by increasing the etching process time, that is, the silicon nitride filling layer 304 with a partial thickness higher than the upper surface of the substrate 10 contacting with the silicon nitride mask layer 210 is removed by increasing the etching process time of the silicon nitride mask layer 210, so that the upper surface of the remaining silicon nitride filling layer 304 is flush with the upper surface of the substrate 10. Before removing the silicon nitride mask layer 210 and a portion of the silicon nitride filling layer 304, a step of removing the second silicon oxide mask layer 212 located in the peripheral circuit region 100 (the second silicon oxide mask layer 212 where the peripheral circuit region 100 is not covered by the patterned mask layer 110) is further included, that is, the second silicon oxide mask layer 212 on the silicon nitride mask layer 210 where the peripheral circuit region 100 is not covered by the patterned mask layer 110 is removed, so as to expose the silicon nitride mask layer 210 where the peripheral circuit region 100 needs to be removed, at this time, a cross-sectional view of the semiconductor structure is shown in fig. 8.
Fig. 9 is a cross-sectional view of the semiconductor structure after the patterned masking layer 110 is removed in accordance with an embodiment of fig. 8. As shown in fig. 9, the method further includes the step of removing the patterned mask layer 110 after removing the silicon nitride mask layer 210 and the portion of the silicon nitride filling layer 304 in sequence based on the patterned mask layer 110. Further, when the stacked structure 108 is an ONO structure, instead of a structure (e.g., an ON structure) that needs to be formed in the area covered by the patterned mask layer 110 (the array area 200), the patterned mask layer 110 is removed after the silicon nitride mask layer 210 and a portion of the silicon nitride filling layer 304 are sequentially removed using the patterned mask layer 110 as a mask, and before the peripheral circuit area 100 exposed by the patterned mask layer 110 exposes the upper surface of the substrate 10. Further, the patterned mask layer is removed while the silicon nitride mask layer 210 and the silicon nitride filling layer 304 are sequentially removed based on the patterned mask layer 110, that is, the patterned mask layer covers the area exposing the upper surface of the stacked structure 108 (the array area 200, the second silicon dioxide mask layer 212) while the silicon nitride mask layer 210 and the silicon nitride filling layer 304 are sequentially removed based on the patterned mask layer 110, and at this time, the cross-sectional view of the semiconductor structure is shown in fig. 9. The step of removing the second silicon oxide mask layer 212 in the array region 200 and the first silicon oxide mask layer 208 in the peripheral circuit region 100 is further included after the second silicon oxide mask layer 212 is exposed in the array region 200. Further, after the second silicon dioxide mask layer 212 is exposed in the array region 200 (after the patterned mask layer 110 is removed), the steps of removing the second silicon dioxide mask layer 212 in the array region 200, the first silicon oxide mask layer 208 in the peripheral circuit region 100, and the dielectric layer 106 in the peripheral circuit region 100 are also included, and at this time, the cross-sectional view of the semiconductor structure is as shown in fig. 6. Further, the second silicon oxide mask layer 212 in the array region 200, the first silicon oxide mask layer 208 in the peripheral circuit region 100, and the dielectric layer 106 in the peripheral circuit region 100 are removed simultaneously. Specifically, the second silicon oxide mask layer 212 of the array region 200, the first silicon oxide mask layer 208 located in the peripheral circuit region 100, and the dielectric layer 106 located in the peripheral circuit region 100 are simultaneously removed by a third etching process, that is, the array region 200 exposes the upper surface of the silicon nitride mask layer 210 while the peripheral circuit region 100 exposes the upper surface of the substrate 10, wherein the rate of etching the second silicon oxide mask layer 212 (including the rate of etching the dielectric layer 106 when the dielectric layer 106 exists) by the third etching process is greater than the rate of etching the silicon nitride mask layer 210, and is greater than the rate of etching the silicon nitride filling layer 304.
In other embodiments, after removing the silicon nitride mask layer 210 and the portion of the silicon nitride fill layer 304 in sequence based on the patterned mask layer 110, the method further comprises the step of simultaneously removing the patterned mask layer 110, removing the second silicon oxide mask layer 212 in the array region 200, the first silicon oxide mask layer 208 in the peripheral circuit region 100, and the dielectric layer 106 in the peripheral circuit region 100, i.e., the patterned mask layer 110 is removed during the process of removing the silicon nitride mask layer 210, the portion of the silicon nitride fill layer 304, the first silicon oxide mask layer 208 in the peripheral circuit region 100, and the dielectric layer 106 in the peripheral circuit region 100. By the method, the process steps are reduced, and the production cost is reduced.
In one embodiment, the silicon nitride mask layer 210 and the second silicon dioxide mask layer 212 are formed using an atomic layer deposition process.
The application also provides a semiconductor structure which is manufactured by adopting the manufacturing method of any one of the above-mentioned methods.
In one embodiment, the semiconductor structure includes a memory device, a transistor, and the like.
The application also provides an electronic device which comprises the semiconductor structure.
The semiconductor structure comprises a substrate 10 including a peripheral circuit region 100, a shallow trench isolation structure 102 is formed in the peripheral circuit region 100, the shallow trench isolation structure 102 isolates a plurality of active regions 104 arranged at intervals in the peripheral circuit region 100, a silicon oxide filling layer is formed in the shallow trench isolation structure 102, a laminated structure 108 on the active region 104 comprises a first silicon oxide mask layer 208 located on the substrate 10 and a silicon nitride mask layer 210 located on the upper surface of the first silicon oxide mask layer 208, wherein the silicon nitride mask layer 210 penetrates through the first silicon oxide mask layer 208 and is in contact with the silicon nitride filling layer 304 in the shallow trench isolation structure 102. When the silicon nitride mask layer 210 is removed, a part of the thickness of the silicon nitride filling layer 304 in the shallow trench isolation structure 102 may be removed, so that the upper surface of the remaining silicon nitride filling layer 304 in the shallow trench isolation structure 102 is flush with the upper surface of the substrate 10, and after the first oxide mask layer is subsequently removed, the peripheral circuit region 100 with a smooth surface may be obtained, thereby eliminating the influence of the unevenness of the surface of the peripheral circuit region 100 on the electrical performance of the semiconductor structure.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express a few embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a peripheral circuit area, a shallow trench isolation structure is formed in the peripheral circuit area, and a plurality of spaced source areas are isolated in the peripheral circuit area by the shallow trench isolation structure; a silicon nitride filling layer is formed in the shallow trench isolation structure;
forming a laminated structure on the active region, wherein the laminated structure comprises a first silicon oxide mask layer and a silicon nitride mask layer, the first silicon oxide mask layer is positioned on the substrate, and the silicon nitride mask layer is positioned on the upper surface of the first silicon oxide mask layer, penetrates through the first silicon oxide mask layer and is in contact with the silicon nitride filling layer;
and removing the silicon nitride mask layer and part of the silicon nitride filling layer, so that the upper surface of the silicon nitride filling layer reserved in the shallow trench isolation structure is flush with the upper surface of the substrate.
2. The method of claim 1, wherein the first silicon oxide mask layer is formed by a thermal oxidation process.
3. The production method according to claim 2, wherein a temperature of the thermal oxidation process is not less than 600 degrees celsius and not more than 1100 degrees celsius.
4. The method of claim 1, wherein the first silicon oxide mask layer has a thickness of not less than 1 nm and not more than 5 nm.
5. The method according to claim 1, wherein the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, and a width of the first shallow trench isolation structure is smaller than a width of the second shallow trench isolation structure; the first shallow trench isolation structure and the second shallow trench isolation structure also comprise a first silicon oxide filling layer, and the first silicon oxide filling layer is positioned between the silicon nitride filling layer and the active region; the second shallow trench isolation structure further comprises a second silicon oxide filling layer, and the second silicon oxide filling layer is located on the surface, far away from the first silicon oxide filling layer, of the silicon nitride filling layer.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the substrate further comprises an array region, the peripheral circuit region is located at the periphery of the array region, and the stacked structure covers the array region and the peripheral circuit region; the removing the silicon nitride mask layer and part of the silicon nitride filling layer comprises the following steps:
forming a graphical mask layer, wherein the graphical mask layer covers the array area;
and removing the silicon nitride mask layer and part of the silicon nitride filling layer in sequence based on the graphical mask layer.
7. The method of claim 6, wherein the step of removing the silicon nitride mask layer and the portion of the silicon nitride filling layer in sequence based on the patterned mask layer further comprises:
and removing the patterned mask layer.
8. The method of claim 7, wherein the stacked structure further comprises a second silicon dioxide mask layer on an upper surface of the silicon nitride mask layer;
before removing the silicon nitride mask layer and part of the silicon nitride filling layer, the method further comprises the following steps: removing the second silicon dioxide mask layer positioned in the peripheral circuit area;
the removing the patterned mask layer further comprises: and removing the second silicon oxide mask layer positioned in the array region and the first silicon oxide mask layer positioned in the peripheral circuit region.
9. The method of claim 8, wherein the silicon nitride mask layer and the second silicon dioxide mask layer are formed using an atomic layer deposition process.
10. The method of claim 6, wherein the first and third STI structures are formed in the array region, the third STI structure has a width less than the width of the first STI structure, and the third STI structure includes the first silicon oxide fill layer.
11. The method of claim 10, wherein the depth of the first shallow trench isolation structure is the same as the depth of the second shallow trench isolation structure and is greater than the depth of the third shallow trench isolation structure.
12. The method of claim 6, wherein the patterned mask layer comprises a patterned photoresist layer.
13. The method of claim 1, further comprising: and forming a dielectric layer on the upper surface of the substrate, wherein the laminated structure is formed on the upper surface of the dielectric layer, and the silicon nitride mask layer penetrates through the dielectric layer and is in contact with the silicon nitride filling layer.
14. The method of claim 13, wherein the dielectric layer comprises a silicon oxide layer.
15. A semiconductor structure, characterized in that it is produced using a production method according to any one of claims 1 to 14.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116053214A (en) * | 2023-03-29 | 2023-05-02 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
| CN118366920A (en) * | 2024-06-06 | 2024-07-19 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116053214A (en) * | 2023-03-29 | 2023-05-02 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
| CN116053214B (en) * | 2023-03-29 | 2023-06-27 | 合肥新晶集成电路有限公司 | Semiconductor structure and preparation method thereof |
| CN118366920A (en) * | 2024-06-06 | 2024-07-19 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN118366920B (en) * | 2024-06-06 | 2024-08-16 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
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