CN116053214B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
- Publication number
- CN116053214B CN116053214B CN202310316092.3A CN202310316092A CN116053214B CN 116053214 B CN116053214 B CN 116053214B CN 202310316092 A CN202310316092 A CN 202310316092A CN 116053214 B CN116053214 B CN 116053214B
- Authority
- CN
- China
- Prior art keywords
- shallow trench
- trench isolation
- layer
- substrate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 183
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005192 partition Methods 0.000 claims description 9
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 description 22
- 239000012212 insulator Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: the substrate is internally provided with a plurality of shallow trench isolation structures which are arranged at intervals, and the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate; wherein the plurality of active regions includes a first active region of a first conductivity type and a second active region of a second conductivity type, the number of second active regions being greater than the number of first active regions; the plurality of shallow trench isolation structures comprise first shallow trench isolation structures and second shallow trench isolation structures, the depths of the first shallow trench isolation structures are different from those of the second shallow trench isolation structures, the first shallow trench isolation structures are shallow trench isolation structures between two adjacent first active areas or shallow trench isolation structures between the first active areas and the second active areas, and the second shallow trench isolation structures are shallow trench isolation structures between two adjacent second active areas.
Description
Technical Field
The present disclosure relates to semiconductor technology, and in particular, to a semiconductor structure and a method for fabricating the same.
Background
With the development of semiconductor technology, the performance requirements of semiconductor devices are higher and higher, and the semiconductor devices are composed of a plurality of different elements, so that the coordination and adaptation of the different elements are also higher and higher.
The N-type element and the P-type element in different application scenes and different circuit designs can be designed into the same line width (pitch), when the element needs to be adjusted to meet the performance requirement, the N-type element cannot be adjusted independently or the P-type element cannot be adjusted independently, so that the device cannot realize functional diversity adjustment, cannot adapt to different application scenes, and reduces the application range of the device.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same in order to solve the above-mentioned problems.
To achieve the above object, in one aspect, the present application provides a semiconductor structure, including:
the substrate is internally provided with a plurality of shallow trench isolation structures which are arranged at intervals, and the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate; wherein the plurality of active regions includes a first active region of a first conductivity type and a second active region of a second conductivity type, the number of the second active regions being greater than the number of the first active regions;
the plurality of shallow trench isolation structures comprise first shallow trench isolation structures and second shallow trench isolation structures, the heights of the first shallow trench isolation structures are different from those of the second shallow trench isolation structures, the first shallow trench isolation structures are two adjacent shallow trench isolation structures between the first active areas or between the first active areas and the second active areas, and the second shallow trench isolation structures are two adjacent shallow trench isolation structures between the second active areas.
The semiconductor structure comprises a plurality of shallow trench isolation structures which are arranged at intervals and a plurality of active areas which are arranged at intervals, wherein the active areas comprise first active areas of a first conductivity type and second active areas of a second conductivity type, the number of the second active areas is larger than that of the first active areas, so that the first conductivity type elements and the second conductivity type elements can have different line widths, when the elements are required to be adjusted to meet the requirement of performance, the first conductivity type elements can be independently adjusted or the second conductivity type elements can be independently adjusted, the semiconductor device is helped to realize functional diversification, different application scenes are adapted, and the application range of the device is improved; in addition, the heights of the first shallow trench isolation structure and the second shallow trench isolation structure are different, so that the element structure comprising the first shallow trench isolation structure and the element structure comprising the second shallow trench isolation structure are not identical, and the first conductive type element and the second conductive type element can be distinguished, so that the first conductive type element can be adjusted independently or the second conductive type element can be adjusted independently.
In one embodiment, the first shallow trench isolation structure has a height greater than a height of the second shallow trench isolation structure.
In one embodiment, the number of the second active regions is 2 times to 3 times that of the first active regions.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
In one embodiment, the semiconductor structure further comprises:
the grid dielectric layer is positioned on the upper surface of the substrate;
the first conductive layer is positioned on the upper surface of the dielectric layer;
the second conductive layer is positioned on the upper surface of the first conductive layer;
and the isolation wall is positioned on the side walls of the grid dielectric layer, the first conductive layer, the second conductive layer and part of the substrate.
The application also provides a preparation method of the semiconductor structure, which comprises the following steps:
providing a substrate;
forming a plurality of initial shallow trench isolation structures which are arranged at intervals in the substrate, wherein the initial shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate; wherein the plurality of active regions includes a first active region of a first conductivity type and a second active region of a second conductivity type, the number of the second active regions being greater than the number of the first active regions;
etching part of the initial shallow trench isolation structure to form a first shallow trench isolation structure and a second shallow trench isolation structure with different heights; the first shallow trench isolation structure is positioned between two adjacent first active areas or between the first active areas and the second active areas, and the second shallow trench isolation structure is positioned between two adjacent second active areas.
According to the preparation method of the semiconductor structure, the plurality of shallow trench isolation structures which are arranged at intervals and the plurality of active areas which are arranged at intervals are formed, the active areas comprise the first active areas of the first conductivity type and the second active areas of the second conductivity type, the number of the second active areas is larger than that of the first active areas, so that the first conductivity type elements and the second conductivity type elements can have different line widths, when the elements are required to be adjusted to meet the performance requirements, the first conductivity type elements can be independently adjusted or the second conductivity type elements can be independently adjusted, the semiconductor device is helped to realize functional diversification, different application scenes are adapted, and the application range of the device is improved; in addition, the heights of the first shallow trench isolation structure and the second shallow trench isolation structure are different, so that the element structure comprising the first shallow trench isolation structure and the element structure comprising the second shallow trench isolation structure are not identical, and the first conductive type element and the second conductive type element can be distinguished, so that the first conductive type element can be adjusted independently or the second conductive type element can be adjusted independently.
In one embodiment, before the etching the portion of the initial shallow trench isolation structure, the method further includes:
forming an anti-reflection layer on the initial shallow trench isolation structure and the upper surface of the active region, wherein the anti-reflection layer is provided with a first opening, and the first opening exposes the shallow trench isolation structure to be etched;
after etching a portion of the initial shallow trench isolation structure to form a first shallow trench isolation structure and a second shallow trench isolation structure having different heights, the method further comprises:
and removing the anti-reflection layer.
In one embodiment, before the forming of the anti-reflection layer on the initial shallow trench isolation structure and the upper surface of the active region, the method further comprises:
forming a sacrificial layer on the upper surface of the initial shallow trench isolation structure and the active region;
forming a partition wall on the sacrificial layer and a part of the side wall of the substrate;
removing the sacrificial layer; wherein, the anti-reflection layer is formed on the inner wall of the isolation wall.
In one embodiment, the forming an anti-reflection layer on the initial shallow trench isolation structure and the upper surface of the active region includes:
forming an anti-reflection material layer on the upper surface of the initial shallow trench isolation structure and the active region;
forming a photoresist layer on the upper surface of the anti-reflection material layer;
exposing the photoresist layer based on a patterned photomask;
developing the exposed photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer is provided with a second opening;
and etching the anti-reflection material layer based on the second opening to obtain the anti-reflection layer.
In one embodiment, after the removing the anti-reflection layer, the method further comprises:
forming a gate dielectric layer on the upper surface of the substrate;
forming a first conductive layer on the upper surface of the gate dielectric layer;
forming a second conductive layer on the upper surface of the first conductive layer;
the grid dielectric layer, the first conductive layer and the second conductive layer are formed on the inner wall of the isolation wall.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;
FIG. 2 is a schematic cross-sectional structure of a semiconductor structure provided in another embodiment;
FIG. 3 is a flow chart illustrating steps of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 4 is a schematic cross-sectional view of the structure obtained in step S102 in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a schematic cross-sectional view of a structure obtained by forming a spacer on a sacrificial layer and a portion of a sidewall of a substrate in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 6 is a schematic cross-sectional view of a structure obtained by removing a sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 7 is a schematic cross-sectional view of a structure obtained by a step of forming an anti-reflective layer in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 8 is a schematic cross-sectional view of the structure obtained in step S104 in the method for fabricating a semiconductor structure according to an embodiment;
fig. 9 is a schematic cross-sectional structure of the structure obtained in step S105 in the method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate:
1-a substrate; 2-an initial shallow trench isolation structure; 21-a first shallow trench isolation structure; 22-a second shallow trench isolation structure; 31-a first active region; 32-a second active region; 4-a sacrificial layer; 5-a partition wall; a 6-antireflective layer; 7-patterning the photoresist layer; an 8-gate structure; 81-gate dielectric layer; 82-a first conductive layer; 83-a second conductive layer.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
With the development of semiconductor technology, the performance requirements of semiconductor devices are higher and higher, and the semiconductor devices are composed of a plurality of different elements, so that the coordination and adaptation of the different elements are also higher and higher.
The N-type element and the P-type element in different application scenes and different circuit designs can be designed into the same line width (pitch), when the element needs to be adjusted to meet the performance requirement, the N-type element cannot be adjusted independently or the P-type element cannot be adjusted independently, so that the device cannot realize functional diversity adjustment, cannot adapt to different application scenes, and reduces the application range of the device.
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same in order to solve the above-mentioned problems.
As shown in fig. 1, the present application provides a semiconductor structure, including: the substrate 1 is internally provided with a plurality of shallow trench isolation structures which are arranged at intervals, and the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate 1; wherein the plurality of active regions includes a first active region 31 of a first conductivity type and a second active region 32 of a second conductivity type, the number of second active regions 32 being greater than the number of first active regions 31; the plurality of shallow trench isolation structures include a first shallow trench isolation structure 21 and a second shallow trench isolation structure 22, wherein the heights of the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 are different, the first shallow trench isolation structure 21 is a shallow trench isolation structure between two adjacent first active regions 31 or a shallow trench isolation structure between a first active region 31 and a second active region 32, and the second shallow trench isolation structure 22 is a shallow trench isolation structure between two adjacent second active regions 32.
By way of example, the material of the substrate 1 may be any suitable material, for example at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and also include multilayer structures formed of these semiconductors, or the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, or may be Double polished silicon wafer (Double Side PolishedWafers, DSP), and the like, and the present embodiment is not limited thereto.
The semiconductor structure in the above embodiment includes a plurality of shallow trench isolation structures arranged at intervals and a plurality of active regions arranged at intervals, where the active regions include a first active region 31 of a first conductivity type and a second active region 32 of a second conductivity type, and the number of the second active regions 32 is greater than that of the first active regions 31, so that the first conductivity type elements and the second conductivity type elements can have different line widths, and when the elements need to be adjusted to meet performance requirements, the first conductivity type elements or the second conductivity type elements can be adjusted independently, thereby helping the semiconductor device to realize functional diversification, so as to adapt to different application scenarios and promote the application range of the device; in addition, the heights of the first shallow trench isolation structures 21 and the second shallow trench isolation structures 22 are different, so that the element structure including the first shallow trench isolation structures 21 and the element structure including the second shallow trench isolation structures 22 are not completely the same, and the first conductive type element and the second conductive type element can be distinguished, so that the first conductive type element can be adjusted independently or the second conductive type element can be adjusted independently.
In one embodiment, still referring to fig. 1, the height of the first shallow trench isolation structure 21 may be greater than the height of the second shallow trench isolation structure 22.
In the above embodiment, the height of the first shallow trench isolation structure 21 is greater than the height of the second shallow trench isolation structure 22, so that the element including the first shallow trench isolation structure 21 and the element including the second shallow trench isolation structure 22 are not completely identical, and different gate structures 8 can be obtained when the gate structures 8 are formed on the substrate 1 in the subsequent process, so as to facilitate adjusting the element performance and realizing the function allocation among different types of elements.
In one embodiment, the height of the first shallow trench isolation structure 21 may be 5 nm to 10 nm greater than the height of the second shallow trench isolation structure 22.
Illustratively, the height of the first shallow trench isolation structure 21 may be 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, etc. greater than the height of the second shallow trench isolation structure 22; in particular, the height difference between the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 may be other dimensions, which are not limited by the specific dimensions illustrated.
In one embodiment, the number of the second active regions 32 may be 2 times to 3 times the number of the first active regions 31.
The number of the second active regions 32 may be 2 times, 2.5 times, 2.8 times or 3 times the number of the first active regions 31, or may be other times, which is not limited by the example; the number of the first active regions 31 of the first conductivity type is different from the number of the second active regions 32 of the second conductivity type, so that the first conductivity type elements and the second conductivity type elements can have different line widths, and the first conductivity type elements or the second conductivity type elements can be independently adjusted according to requirements, so that the efficiency between the different types of elements is improved.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.
In some examples, the semiconductor structure may include a plurality of first conductivity type elements and a plurality of second conductivity type elements. The first conductivity type element and the second conductivity type element may have different line widths; the plurality of first conductivity type elements may have different line widths; the plurality of second conductivity type elements may have different line widths; it is understood that in the same semiconductor device, the N-type element and the P-type element may be designed with different line widths, different N-type elements may be designed with different line widths, or different P-type elements may be designed with different line widths. The shallow trench isolation structure of the first conductivity type element and the shallow trench isolation structure of the second conductivity type element may have different heights; the shallow trench isolation structures of the plurality of first conductivity type elements may have different heights; the shallow trench isolation structures of the plurality of second conductivity type elements may have different heights; it is understood that in the same semiconductor device, the shallow trench isolation structures of the N-type element and the P-type element may be designed to have different heights, the shallow trench isolation structures of the different N-type elements may be designed to have different heights, or the shallow trench isolation structures of the different P-type elements may be designed to have different heights.
In one embodiment, as shown in fig. 2, the semiconductor structure further comprises: a gate dielectric layer 81, a first conductive layer 82, a second conductive layer 83, and a partition wall 5; the gate dielectric layer 81 is located on the upper surface of the substrate 1; the first conductive layer 82 is located on the upper surface of the dielectric layer; the second conductive layer 83 is located on the upper surface of the first conductive layer 82; the isolation wall 5 is located on the sidewalls of the gate dielectric layer 81, the first conductive layer 82, the second conductive layer 83 and a portion of the substrate 1.
Wherein, the gate dielectric layer 81, the first conductive layer 82 and the second conductive layer 83 together form a gate structure 8; therefore, the grid structures 8 on the shallow trench isolation structures with different heights have different heights, and the grid structures 8 on different active areas have different line widths, so that elements with different grid structures 8 can be obtained; i.e. it can be achieved that different conductivity type elements are provided with different gate structures 8 and/or that the same conductivity type element is provided with different gate structures 8.
Illustratively, the gate dielectric layer 81 may include, but is not limited to, at least one of a silicon oxide layer and a high-k dielectric layer; the first conductive layer 82 may include, but is not limited to, a metal layer or a polysilicon layer; the second conductive layer 83 may include, but is not limited to, a metal layer or a polysilicon layer.
As shown in fig. 3, the present application further provides a method for preparing a semiconductor structure, where the method for preparing a semiconductor structure may include the following steps:
s101: a substrate 1 is provided.
S102: forming a plurality of initial shallow trench isolation structures 2 which are arranged at intervals in a substrate 1, wherein the initial shallow trench isolation structures 2 isolate a plurality of active areas which are arranged at intervals in the substrate 1; wherein the plurality of active regions includes a first active region 31 of a first conductivity type and a second active region 32 of a second conductivity type, the number of second active regions 32 being greater than the number of first active regions 31; as shown in fig. 4.
S103: etching part of the initial shallow trench isolation structure 2 to form a first shallow trench isolation structure 21 and a second shallow trench isolation structure 22 with different heights; the first shallow trench isolation structure 21 is located between two adjacent first active regions 31 or between a first active region 31 and a second active region 32, and the second shallow trench isolation structure 22 is located between two adjacent second active regions 32; as shown in fig. 1.
The semiconductor structure obtained after steps S101 to S103 may be referred to fig. 1. Of course, in order to facilitate understanding of the present application, fig. 1 shows an example of a semiconductor structure prepared by using the method for preparing a semiconductor structure of the present application, and other suitable examples of a semiconductor structure prepared by using the method for preparing a semiconductor structure of the present application may also be provided, which is not limited herein.
By way of example, the material of the substrate 1 may be any suitable material, for example at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and also include multilayer structures formed of these semiconductors, or the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, or may be Double polished silicon wafer (Double Side PolishedWafers, DSP), and the like, and the present embodiment is not limited thereto.
In one embodiment, the number of the second active regions 32 may be 2 times to 3 times the number of the first active regions 31.
The number of the second active regions 32 may be 2 times, 2.5 times, 2.8 times or 3 times the number of the first active regions 31, or may be other times, which is not limited by the example; the number of the first active regions 31 of the first conductivity type is different from the number of the second active regions 32 of the second conductivity type, so that the first conductivity type elements and the second conductivity type elements can have different line widths, and the first conductivity type elements or the second conductivity type elements can be independently adjusted according to requirements, so that the efficiency between the different types of elements is improved.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.
In some examples, the semiconductor structure may include a plurality of first conductivity type elements and a plurality of second conductivity type elements. The first conductivity type element and the second conductivity type element may have different line widths; the plurality of first conductivity type elements may have different line widths; the plurality of second conductivity type elements may have different line widths; it is understood that in the same semiconductor device, the N-type element and the P-type element may be designed with different line widths, different N-type elements may be designed with different line widths, or different P-type elements may be designed with different line widths. The shallow trench isolation structure of the first conductivity type element and the shallow trench isolation structure of the second conductivity type element may have different heights; the shallow trench isolation structures of the plurality of first conductivity type elements may have different heights; the shallow trench isolation structures of the plurality of second conductivity type elements may have different heights; it is understood that in the same semiconductor device, the shallow trench isolation structures of the N-type element and the P-type element may be designed to have different heights, the shallow trench isolation structures of the different N-type elements may be designed to have different heights, or the shallow trench isolation structures of the different P-type elements may be designed to have different heights.
According to the preparation method of the semiconductor structure in the embodiment, the plurality of shallow trench isolation structures which are arranged at intervals and the plurality of active areas which are arranged at intervals are formed, the active areas comprise the first active areas 31 of the first conductivity type and the second active areas 32 of the second conductivity type, the number of the second active areas 32 is larger than that of the first active areas 31, so that the first conductivity type elements and the second conductivity type elements can have different line widths, when the elements are required to be adjusted to meet the requirement of the applicable performance, the first conductivity type elements can be independently adjusted or the second conductivity type elements can be independently adjusted, the semiconductor device is helped to realize functional diversification, the application range of the device is adapted to different application scenes, and the application range of the device is improved; in addition, the heights of the first and second shallow trench isolation structures 21 and 22 are different to distinguish the first and second conductive type elements, so that the first or second conductive type elements can be adjusted independently.
In step S102, referring to step S102 in fig. 3 and fig. 4, a plurality of initial shallow trench isolation structures 2 are formed in the substrate 1 at intervals, and the initial shallow trench isolation structures 2 isolate a plurality of active regions in the substrate 1 at intervals.
The forming of the plurality of initial shallow trench isolation structures 2 in the substrate 1 at intervals may include the following steps: forming a plurality of shallow trenches which are arranged at intervals in a substrate 1; and filling isolation materials in the shallow trenches.
Further, forming a plurality of shallow trenches arranged at intervals in the substrate 1 may include the following steps: forming a liner layer on the upper surface of the substrate 1, wherein the liner layer may be formed on the upper surface of the substrate 1 by a chemical vapor deposition process or an atomic layer deposition process, and the liner layer may include, but is not limited to, a silicon oxide layer; forming a patterned mask layer on the upper surface of the liner layer, wherein the patterned mask layer is provided with a mask opening, and the mask opening defines the shape and the position of the shallow trench, and the patterned mask layer can comprise, but is not limited to, a silicon nitride layer or a silicon oxynitride layer, and can also comprise a laminated structure of the silicon nitride layer and the silicon oxynitride layer; the liner layer and the substrate 1 are sequentially etched based on the mask opening to form a shallow trench in the substrate 1.
In one embodiment, the method of fabricating a semiconductor structure may further comprise the steps of, prior to etching a portion of the initial shallow trench isolation structure 2: forming a sacrificial layer 4 on the upper surfaces of the initial shallow trench isolation structure 2 and the active region; forming a partition wall 5 on the sacrificial layer 4 and a part of the side wall of the substrate 1, wherein the obtained structure is shown in fig. 5; the sacrificial layer 4 is removed and the resulting structure is shown in fig. 6.
Wherein, before etching part of the shallow trench isolation structure, forming a partition wall 5 to isolate and protect the active region and the region where the shallow trench isolation structure is located. For example, the barrier wall 5 may be formed on the sacrificial layer 4 and a portion of the sidewall of the substrate 1 using a chemical vapor deposition process or an atomic layer deposition process.
When the initial shallow trench isolation structure 2 is formed, the upper surface of the substrate 1 is inevitably damaged, the formation of the sacrificial layer 4 can improve the damaged surface of the substrate 1, and the structure morphology is optimized, so that the subsequent process on the substrate 1 is facilitated. For example, the sacrificial layer 4 may be formed on the upper surfaces of the shallow trench isolation structure and the active region using a chemical vapor deposition process or an atomic layer deposition process.
Before etching portions of the initial shallow trench isolation structure 2, the sacrificial layer 4 is removed to expose the active region and the initial shallow trench isolation structure 2. Illustratively, the sacrificial layer 4 may be removed using a dry etching process or a wet etching process.
In one embodiment, after removing the sacrificial layer 4 before etching a portion of the initial shallow trench isolation structure 2, the method of fabricating a semiconductor structure further includes: a step of forming an anti-reflection layer 6 on the initial shallow trench isolation structure 2 and the upper surface of the active region, as shown in fig. 7; the anti-reflection layer 6 is provided with a first opening, and the shallow trench isolation structure to be etched is exposed out of the first opening; wherein the anti-reflection layer 6 is formed on the inner wall of the partition wall 5.
In one embodiment, the formation of the anti-reflection layer 6 on the initial shallow trench isolation structure 2 and the upper surface of the active region includes: forming an anti-reflection material layer on the initial shallow trench isolation structure 2 and the upper surface of the active region; forming a photoresist layer on the upper surface of the anti-reflection material layer; exposing the photoresist layer based on the patterned photomask; developing the exposed photoresist layer to obtain a patterned photoresist layer 7, wherein the patterned photoresist layer 7 is provided with a second opening; etching the anti-reflection material layer based on the second opening to obtain an anti-reflection layer 6; the resulting structure is shown in FIG. 7. It should be noted that, after the anti-reflection layer 6 is obtained, the patterned photoresist layer 7 needs to be removed to reduce the pollution of the patterned photoresist layer 7 to the substrate 1. Specifically, the patterned photoresist layer 7 may be removed using, but not limited to, an ashing process.
The photoresist layer may be formed on the upper surface of the anti-reflection material layer by spin coating in a coating method, and may include a positive photoresist layer or a negative photoresist layer.
In step S103, referring to step S103 in fig. 3 and fig. 7 and 1, etching a portion of the initial shallow trench isolation structure 2 to form a first shallow trench isolation structure 21 and a second shallow trench isolation structure 22 with different heights; the first shallow trench isolation structure 21 is located between two adjacent first active regions 31 or between a first active region 31 and a second active region 32, and the second shallow trench isolation structure 22 is located between two adjacent second active regions 32.
Illustratively, a portion of the initial shallow trench isolation structure 2 may be etched using a Quasi-atomic layer etching (Quasi-atomic layer etch) process to form first and second shallow trench isolation structures 21, 22 that are different in height.
In one embodiment, after etching a portion of the initial shallow trench isolation structure 2 to form the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 having different heights, in combination with fig. 7 and 1, further includes: the step of removing the anti-reflection layer 6 is performed so that subsequent processes can be performed on the upper surfaces of the first and second shallow trench isolation structures 21 and 22.
In one embodiment, still referring to fig. 1, the height of the first shallow trench isolation structure 21 may be greater than the height of the second shallow trench isolation structure 22.
In the above embodiment, the height of the first shallow trench isolation structure 21 is greater than the height of the second shallow trench isolation structure 22, so that the element including the first shallow trench isolation structure 21 and the element including the second shallow trench isolation structure 22 are not completely identical, and different gate structures 8 can be obtained when the gate structures 8 are formed on the substrate 1 in the subsequent process, so as to facilitate adjusting the element performance and realizing the function allocation among different types of elements. In one embodiment, the height of the first shallow trench isolation structure 21 may be 5 nm to 10 nm greater than the height of the second shallow trench isolation structure 22.
Illustratively, the height of the first shallow trench isolation structure 21 may be 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, etc. greater than the height of the second shallow trench isolation structure 22; in particular, the height difference between the first shallow trench isolation structure 21 and the second shallow trench isolation structure 22 may be other dimensions, which are not limited by the specific dimensions illustrated.
In one embodiment, after removing the anti-reflection layer 6, the method for manufacturing a semiconductor structure may further include the steps of:
s104: forming a gate dielectric layer 81 on the upper surface of the substrate 1; the resulting structure is shown in FIG. 8.
S105: forming a first conductive layer 82 on the upper surface of the gate dielectric layer 81; the resulting structure is shown in FIG. 9.
S106: forming a second conductive layer 83 on the upper surface of the first conductive layer 82; wherein the gate dielectric layer 81, the first conductive layer 82 and the second conductive layer 83 are formed on the inner wall of the isolation wall 5; the resulting structure is shown in figure 2.
For example, the gate dielectric layer 81 may be formed on the upper surface of the substrate 1 using a chemical vapor deposition process or an atomic layer deposition process, and the gate dielectric layer 81 may include, but is not limited to, at least one of a silicon oxide layer and a high-k dielectric layer. The first conductive layer 82 may be formed on the upper surface of the gate dielectric layer 81 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the first conductive layer 82 may include, but is not limited to, a metal layer or a polysilicon layer. The second conductive layer 83 may be formed on the upper surface of the first conductive layer 82 using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the second conductive layer 83 may include, but is not limited to, a metal layer or a polysilicon layer.
Wherein, the gate dielectric layer 81, the first conductive layer 82 and the second conductive layer 83 together form a gate structure 8; therefore, the grid structures 8 on the shallow trench isolation structures with different heights have different heights, and the grid structures 8 on different active areas have different line widths, so that elements with different grid structures 8 can be obtained; i.e. it can be achieved that different conductivity type elements are provided with different gate structures 8 and/or that the same conductivity type element is provided with different gate structures 8. Therefore, NMOS (Positive channel-Metal-Oxide-Semiconductor) and PMOS (P-type Metal-Oxide-Semiconductor) obtained based on the Semiconductor structure of the present application may have different gate line widths and/or gate heights, and further, NMOS and PMOS obtained based on these NMOS and PMOS, such as memory, I/O (computer interface), logic device, embedded device, and the like, have different line widths, so that product characteristics are easier to be deployed, and applicability is improved.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming a plurality of initial shallow trench isolation structures which are arranged at intervals in the substrate, wherein the initial shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate; wherein the plurality of active regions includes a first active region of a first conductivity type and a second active region of a second conductivity type, the number of the second active regions being greater than the number of the first active regions;
forming a sacrificial layer on the upper surface of the initial shallow trench isolation structure and the active region;
forming a partition wall on the sacrificial layer and a part of the side wall of the substrate;
removing the sacrificial layer;
forming an anti-reflection layer on the initial shallow trench isolation structure and the upper surface of the active region, wherein the anti-reflection layer is provided with a first opening, and the first opening exposes the shallow trench isolation structure to be etched; wherein the anti-reflection layer is formed on the inner wall of the partition wall;
etching part of the initial shallow trench isolation structure to form a first shallow trench isolation structure and a second shallow trench isolation structure with different heights; the first shallow trench isolation structure is positioned between two adjacent first active areas or between the first active areas and the second active areas, and the second shallow trench isolation structure is positioned between two adjacent second active areas;
and removing the anti-reflection layer.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein forming a plurality of initial shallow trench isolation structures in the substrate at intervals comprises:
forming a plurality of shallow trenches which are arranged at intervals in the substrate;
and filling isolation materials in the shallow trenches.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein forming a plurality of shallow trenches in the substrate at intervals comprises:
forming a liner layer on the upper surface of the substrate;
forming a patterned mask layer on the upper surface of the liner layer, wherein the patterned mask layer is provided with a mask opening, and the shape and the position of the shallow trench are defined by the mask opening;
and etching the liner layer and the substrate in sequence based on the mask opening so as to form a plurality of shallow trenches which are arranged at intervals in the substrate.
4. The method of claim 1, wherein forming an anti-reflective layer on the initial shallow trench isolation structure and the upper surface of the active region comprises:
forming an anti-reflection material layer on the upper surface of the initial shallow trench isolation structure and the active region;
forming a photoresist layer on the upper surface of the anti-reflection material layer;
exposing the photoresist layer based on a patterned photomask;
developing the exposed photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer is provided with a second opening;
and etching the anti-reflection material layer based on the second opening to obtain the anti-reflection layer.
5. The method of claim 1, wherein after removing the anti-reflective layer, the method further comprises:
forming a gate dielectric layer on the upper surface of the substrate;
forming a first conductive layer on the upper surface of the gate dielectric layer;
forming a second conductive layer on the upper surface of the first conductive layer;
the grid dielectric layer, the first conductive layer and the second conductive layer are formed on the inner wall of the isolation wall.
6. A semiconductor structure manufactured by the method of manufacturing a semiconductor structure according to any one of claims 1-5, the semiconductor structure comprising:
the substrate is internally provided with a plurality of shallow trench isolation structures which are arranged at intervals, and the shallow trench isolation structures isolate a plurality of active areas which are arranged at intervals in the substrate; wherein the plurality of active regions includes a first active region of a first conductivity type and a second active region of a second conductivity type, the number of the second active regions being greater than the number of the first active regions;
a partition wall located on a side wall of a portion of the substrate;
the plurality of shallow trench isolation structures comprise first shallow trench isolation structures and second shallow trench isolation structures, the heights of the first shallow trench isolation structures are different from those of the second shallow trench isolation structures, the first shallow trench isolation structures are two adjacent shallow trench isolation structures between the first active areas or between the first active areas and the second active areas, and the second shallow trench isolation structures are two adjacent shallow trench isolation structures between the second active areas.
7. The semiconductor structure of claim 6, wherein a height of the first shallow trench isolation structure is greater than a height of the second shallow trench isolation structure.
8. The semiconductor structure of claim 6, wherein the number of second active regions is 2-3 times the number of first active regions.
9. The semiconductor structure of claim 6, wherein the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
10. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises:
the grid dielectric layer is positioned on the upper surface of the substrate;
the first conductive layer is positioned on the upper surface of the dielectric layer;
the second conductive layer is positioned on the upper surface of the first conductive layer;
the grid dielectric layer, the first conductive layer and the second conductive layer are positioned on the inner wall of the isolation wall.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310316092.3A CN116053214B (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310316092.3A CN116053214B (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116053214A CN116053214A (en) | 2023-05-02 |
| CN116053214B true CN116053214B (en) | 2023-06-27 |
Family
ID=86114924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310316092.3A Active CN116053214B (en) | 2023-03-29 | 2023-03-29 | Semiconductor structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116053214B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115623790A (en) * | 2021-07-13 | 2023-01-17 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| WO2023029401A1 (en) * | 2021-08-30 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242295B1 (en) * | 1998-01-05 | 2001-06-05 | Texas Instruments Incorporated | Method of fabricating a shallow doped region for a shallow junction transistor |
| US7994020B2 (en) * | 2008-07-21 | 2011-08-09 | Advanced Micro Devices, Inc. | Method of forming finned semiconductor devices with trench isolation |
| US8853700B2 (en) * | 2011-08-10 | 2014-10-07 | International Business Machines Corporation | Cross-coupling of gate conductor line and active region in semiconductor devices |
| JP2013038336A (en) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | Semiconductor device |
| US9455198B1 (en) * | 2014-12-08 | 2016-09-27 | Globalfoundries Inc. | Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices |
| US9583616B2 (en) * | 2015-03-10 | 2017-02-28 | Globalfoundries Inc. | Semiconductor structure including backgate regions and method for the formation thereof |
| DE102016109555A1 (en) * | 2016-05-24 | 2017-11-30 | Infineon Technologies Austria Ag | POWER SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR COMPONENT |
| CN108074867A (en) * | 2016-11-08 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10164008B1 (en) * | 2017-06-03 | 2018-12-25 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
| US10262997B2 (en) * | 2017-09-14 | 2019-04-16 | Vanguard International Semiconductor Corporation | High-voltage LDMOSFET devices having polysilicon trench-type guard rings |
| CN112885770A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Shallow trench isolation structure, semiconductor structure and preparation method thereof |
| CN111261713B (en) * | 2020-03-25 | 2022-09-09 | 广东芯聚能半导体有限公司 | Trench type IGBT device structure |
| US11450743B2 (en) * | 2020-10-21 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a semiconductor device with implantation of impurities at high temperature |
| CN114446886A (en) * | 2020-11-04 | 2022-05-06 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| US11923366B2 (en) * | 2021-05-05 | 2024-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor isolation regions and methods of forming the same |
| US11742426B2 (en) * | 2021-05-11 | 2023-08-29 | International Business Machines Corporation | Forming crossbar and non-crossbar transistors on the same substrate |
| US20230032102A1 (en) * | 2021-08-02 | 2023-02-02 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory |
| CN114530447B (en) * | 2022-04-24 | 2022-10-25 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
-
2023
- 2023-03-29 CN CN202310316092.3A patent/CN116053214B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115623790A (en) * | 2021-07-13 | 2023-01-17 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| WO2023029401A1 (en) * | 2021-08-30 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116053214A (en) | 2023-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10998235B2 (en) | FinFET with sloped surface at interface between isolation structures and manufacturing method thereof | |
| TWI380343B (en) | Planar substrate devices integrated with finfets and method of manufacture | |
| US7750429B2 (en) | Self-aligned and extended inter-well isolation structure | |
| US20220319921A1 (en) | Semiconductor Structure and Method for Manufacturing Semiconductor Structure | |
| CN109119470B (en) | Boundary spacer structure and integration | |
| CN114446769A (en) | Method for manufacturing semiconductor device | |
| CN111199880B (en) | Manufacturing method of semiconductor device and semiconductor device | |
| US7666800B2 (en) | Feature patterning methods | |
| TW202137572A (en) | Integrated chip | |
| CN116053214B (en) | Semiconductor structure and preparation method thereof | |
| TWI735877B (en) | Integrated circuit, semiconductor structure and the method for fabricating the same | |
| US20080283930A1 (en) | Extended depth inter-well isolation structure | |
| CN114334618A (en) | Self-alignment method of semiconductor device | |
| CN113097133A (en) | Semiconductor structure and preparation method thereof | |
| US10304679B2 (en) | Method of fabricating a mask | |
| US20100173497A1 (en) | Method of fabricating semiconductor integrated circuit device | |
| US9564317B1 (en) | Method of forming a nanowire | |
| US11810786B2 (en) | Method for fabricating semiconductor device | |
| CN116390490B (en) | Method for preparing semiconductor structure | |
| US7312132B2 (en) | Field insulator FET device and fabrication method thereof | |
| CN112259505B (en) | Method for forming fin body of semiconductor device | |
| KR100345067B1 (en) | Manufacturing method of semiconductor device | |
| CN117832073A (en) | Semiconductor device structure and processing method thereof | |
| TW202410459A (en) | Semiconductor devices and methods for making the same | |
| CN118098936A (en) | Manufacturing method of semiconductor structure, mask structure and semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |