CN117832073A - Semiconductor device structure and processing method thereof - Google Patents

Abstract

The invention relates to a semiconductor device structure and a processing method thereof, wherein the method comprises the following steps: obtaining a substrate; patterning the substrate, and forming at least one groove extending from the first surface of the substrate into the substrate in a first area of the substrate, wherein a substrate structure is remained in the first area except for each groove; the depth-to-width ratio of each groove is larger than 1/2, and the height-to-width ratio of the substrate structure remained in the first area is larger than 1/2; depositing a target material to fill each groove; removing the residual substrate structure of the first region through photoetching and etching; depositing the target material fills the locations of the removed base structure. The invention can realize the deep groove filling with small depth-to-width ratio of tens to hundreds of micrometers which is not possessed by the traditional process through the twice deposition process with thinner deposition thickness, and has simpler process and lower cost.

Description

Semiconductor device structure and processing method thereof

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device structure and a processing method of the semiconductor device structure.

Background

In semiconductor manufacturing processes, particularly MEMS manufacturing processes, deep trench filling processes are often used. One exemplary approach is to etch the deep trench first and then fill the deep trench with other materials. Such deep trench filling processes are not problematic when filling deep trenches with small widths, e.g., with aspect ratios greater than 1/2. In the filling process, the film thickness of the filled material is continuously increased on the side walls and the bottom of the deep groove, and finally, the filled material on the side walls on two sides of the deep groove contacts as the width of the deep groove is not large, so that the deep groove filling is completed, as shown in fig. 1. However, in this filling process, when filling deep trenches having a large width, for example, a deep trench having a depth-to-width ratio of less than 1/2, since the trench width is greater than twice the trench depth, the filling cannot be performed by the lateral deposition of the filling material on the sidewalls of the deep trench, and therefore, the deep trench can be filled only by depositing the filling material having a thickness exceeding the depth thereof. Alternatively, when using such a filling process to fill deep trenches having a greater depth and a greater width, such as those having a depth greater than 5 microns and a width greater than 10 microns, it may be necessary to deposit a very thick fill material having a film thickness at least greater than the depth of the deep trench, which may require significant processing time and cost, as shown in FIG. 2. Meanwhile, after the deep trench filling is completed, the filling material of the surface layer needs to be removed by Chemical Mechanical Polishing (CMP) in a subsequent process. As the film thickness increases, the process time required for the CMP process increases, which also results in a decrease in production efficiency and an increase in cost. In addition, when it is required to fill deep grooves of a depth of tens or even tens of micrometers, it is difficult for conventional equipment to deposit such thick filling materials if the above-mentioned is adopted.

Disclosure of Invention

Accordingly, it is desirable to provide a method of fabricating a semiconductor device structure that can complete filling of deep trenches having a greater depth and a greater width with a thinner deposition thickness.

A method for processing a semiconductor device structure includes: obtaining a substrate; patterning the substrate, and forming at least one groove extending from the first surface of the substrate into the substrate in a first area of the substrate, wherein a substrate structure is remained in the first area except for each groove; the depth-to-width ratio of each groove is larger than 1/2, and the height-to-width ratio of the substrate structure remained in the first area is larger than 1/2; depositing a target material to fill each groove; removing the residual substrate structure of the first region through photoetching and etching; depositing the target material fills the locations of the removed base structure.

According to the processing method of the semiconductor device structure, the large groove (deep groove) occupying the whole first area is formed by etching the residual substrate structure of the first area, and as the depth-to-width ratio of the groove filled twice is larger than 1/2, only a thinner target material needs to be deposited for the filling twice, and finally the deep groove filled with the target material can be obtained.

In one embodiment, in the step of forming at least one trench in the first region of the substrate, the trench extends from the first surface of the substrate into the substrate, the aspect ratio of each trench is greater than 1/2.

In one embodiment, in the step of forming at least one trench in the first region of the substrate, the at least one trench extending from the first surface of the substrate into the substrate, the aspect ratio of the substrate structure remaining in the first region is greater than 1/2.

In one embodiment, the step of depositing the target material fills the removed locations of the substrate structure further comprises the step of chemical mechanical polishing the first surface of the substrate.

In one embodiment, after the step of filling each of the trenches with the deposition target material, before the step of removing the substrate structure remaining in the first region by photolithography and etching, the method further includes a step of chemically mechanically polishing the first surface of the substrate.

In one embodiment, in the step of removing the substrate structure remaining in the first region by photolithography and etching, an etching depth is the same as a depth of each of the trenches.

In one embodiment, the step of patterning the substrate comprises: forming an etching opening in a second area of the first surface of the substrate by photoetching, wherein photoresist is formed in the second area except for the etching opening; and etching the substrate by taking the photoresist as an etching barrier layer, forming at least one groove below the etching opening, and forming a substrate structure below the photoresist.

In one embodiment, before the step of depositing the target material to fill each of the trenches, the method further includes a step of removing photoresist on the substrate.

In one embodiment, the step of depositing the target material fills the locations of the removed substrate structures further comprises the step of removing photoresist on the substrate.

It is also desirable to provide a semiconductor device structure.

A semiconductor device structure having a deep trench formed in a substrate thereof, the deep trench being filled with the target material, the semiconductor device structure being formed by processing the semiconductor device structure of any of the preceding embodiments.

In one embodiment, the deep grooves have a groove depth of greater than 5 microns and a groove width of greater than 10 microns.

Drawings

For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.

FIG. 1 is a schematic illustration of an exemplary trench fill having an aspect ratio greater than 1/2;

FIG. 2 is a schematic illustration of an exemplary trench fill having an aspect ratio of less than 1/2;

FIG. 3 is a flow chart of a method of fabricating a semiconductor device structure in accordance with one embodiment of the present application;

fig. 4a is a schematic cross-sectional view of the semiconductor device structure after step S320 is completed in one embodiment of the present application, and fig. 4b is a schematic cross-sectional view of the structure shown in fig. 4a before etching in one embodiment;

FIG. 5a is a top view of the grooves 411 in an embodiment of the grid structure of the grooves 411 of the present application, and FIG. 5b is a top view of the grooves 411 in an embodiment of the grid structure of the grooves 411 of the present application;

FIG. 6 is a schematic cross-sectional view of the semiconductor device structure after step S330 is completed in one embodiment of the present application;

FIG. 7 is a schematic view of the structure of FIG. 6 after a CMP process in accordance with one embodiment of the present application;

FIG. 8 is a schematic cross-sectional view of the semiconductor device structure after the photolithography is completed in step S340 in one embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of the semiconductor device structure after etching at step S340 in one embodiment of the present application;

FIG. 10 is a schematic cross-sectional view of a semiconductor device structure after photoresist removal at step S340 in one embodiment of the present application;

FIG. 11 is a schematic cross-sectional view of a semiconductor device structure after step S350 is completed in an embodiment of the present application;

fig. 12 is a schematic view of the structure of fig. 11 after CMP processing in accordance with an embodiment of the present application.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.

The method is suitable for deep grooves with deeper depth and wider width. For example, for a target deep trench having a depth greater than 5 microns and a width greater than 10 microns, the method of fabricating a semiconductor device structure of the present application is capable of completing filling of the target deep trench with a thinner deposition thickness. Fig. 3 is a flowchart of a method for fabricating a semiconductor device structure according to an embodiment of the present application, including the following steps:

s310, acquiring a substrate.

In one embodiment of the present application, the base 410 of the wafer comprises a semiconductor substrate. In one embodiment of the present application, the material of the semiconductor substrate may be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, and may be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment shown in fig. 4a, the substrate is made of monocrystalline silicon. Devices, such as transistors, e.g., NMOS and/or PMOS, may be formed on the substrate. Accordingly, a conductive member may be formed in the substrate, and the conductive member may be a gate, a source, or a drain of the transistor, or may be a metal interconnection structure electrically connected to the transistor, or the like. In addition, the substrate may be formed with an isolation structure such as STI (shallow trench isolation structure).

S320, patterning the substrate, forming a groove in the first area, and leaving a substrate structure at the position except the groove of the first area.

Referring to fig. 4a, the trench 411 extends from the front surface of the substrate 410 into the substrate 410. The purpose of the present application is to finally achieve filling of a deep trench of greater depth and width. The trench 411 is formed in the space where the target deep trench is to be formed (i.e., the first region a), and the remaining position of the first region a is the remaining base structure 412, see fig. 4b. Each groove 411 may be a plurality of stripe grooves arranged side by side, may be a grid structure as shown in fig. 5a, or may be a mesh structure as shown in fig. 5 b. It should be noted that the base structure 412 in the present specification refers to a base structure remaining in the first area a after the completion of the step S320, and does not include the base 410 outside the first area a.

In one embodiment of the present application, step S320 specifically includes:

an etched opening is formed in a second region B of the front surface of the substrate 410 by photolithography. The second region B is formed with a photoresist 431 at a position other than the etched opening.

The substrate 410 is etched using photoresist as an etch stop layer, and a trench 411 is formed below the etched opening, with a residual substrate structure 412 below the photoresist. Fig. 4B shows the positions of a first area a and a second area B in an embodiment, the first area a being located below the second area B.

After step S320 is completed, the photoresist is removed.

S330, depositing target materials to fill the grooves.

The target material is made of a material different from the substrate. It may be silicon dioxide, siN, polysilicon, etc. In one embodiment of the present application, the target material 422 may be deposited on the front side of the substrate 410. Since the target deep trench is separated into a plurality of smaller trenches 411 by the remaining base structure 412, the trench width of each trench 411 is a portion of the trench width of the target deep trench, and thus the aspect ratio of the trench 411 is significantly greater than the aspect ratio of the target deep trench. As previously described, as the thickness of the deposited target material 422 on the sidewalls of the trenches 411 increases, the target material 422 on the sidewalls eventually closes, completing the filling of the trenches 411, as shown in fig. 6.

In one embodiment of the present application, after step S330 is completed, the front side of the substrate 410 may also be subjected to Chemical Mechanical Polishing (CMP) to remove the target material 422 on the residual substrate structure 412, see fig. 7. The base structure 412 may act as a CMP stop layer.

And S340, removing the residual substrate structure of the first region through photoetching and etching.

In one embodiment of the present application, a photoresist layer 432 may be formed by coating a photoresist layer on the front surface of the substrate 410, and then developing the photoresist layer after exposure using a corresponding photolithography mask. The photoresist layer 432 exposes the base structure 412 and covers other structures (the target material 422, other structures of the base 410, etc.), see fig. 8. The base structure 412 is then removed by etching, forming a trench 413 in the original base structure 412, see fig. 9. The photoresist 432 is removed to yield the structure shown in fig. 10.

S350, depositing a target material to fill the locations of the removed base structure.

The same target material 422 as in step S330 is deposited again on the front surface of the substrate 410. Referring to fig. 10, similar to step S330, the target deep trench is separated into a plurality of smaller trenches 413 by the target material 422 formed in step S330, and the trench width of each trench 413 is a portion of the trench width of the target deep trench, so the aspect ratio of the trench 413 is significantly greater than the aspect ratio of the target deep trench. As the thickness of the deposited target material 422 on the sidewalls of the trenches 413 increases, the target material 422 on the sidewalls eventually closes, completing the filling of the trenches 413, as shown in fig. 11.

In one embodiment of the present application, CMP may also be performed on the front side of the substrate 410 to remove excess target material 422, see fig. 12. The top of the base structure 410 may act as a CMP stop layer.

In one embodiment of the present application, the aspect ratio of the trench 411 is greater than 1/2. By rationally designing the structure of the trench 411 to ensure that the aspect ratio of the trench 411 is greater than 1/2, the deposition thickness required to fill the trench 411 with the deposition target material 422 of step S330 can be reduced. It will be appreciated that for trenches 411 having aspect ratios greater than 1/2, the target material 422 may be deposited to a thickness that is only half the width of the trench 411 to fill the trench 411. On the other hand, since the filling capability of the deposition tool is limited, the aspect ratio of the trench 411 should not be too large (e.g., the aspect ratio reaches 10:1), otherwise, when the trench 411 is filled with the deposition target material 422 in step S330, a void (void) may occur in the middle of the trench 411. In other embodiments, the aspect ratio of the trench 411 may be adjusted to be higher (e.g., the aspect ratio reaches 10:1, even higher) for the void (void) to be present in the middle of the trench 411. The specific value of the aspect ratio of the trench 411 is limited by the filling capability of the stage used for the deposition of step S330 with respect to the target material 422. For embodiments in which trenches 411 communicate with each other within a target trench, an aspect ratio of greater than 1/2 for trench 411 means that the aspect ratio is greater than 1/2 for each portion of trench 411.

In one embodiment of the present application, the aspect ratio of the trench 413 is greater than 1/2, i.e., the aspect ratio of the base structure 412 formed in step S320 is greater than 1/2. The aspect ratio of the trench 413 is greater than 1/2, which may reduce the deposition thickness required to deposit the target material 422 to fill the trench 413 in step S350. It will be appreciated that for trenches 413 having aspect ratios greater than 1/2, the target material 422 may be deposited to a thickness that is only half the width of the trench 413 to fill the trench 413. On the other hand, since the filling capability of the deposition tool is limited, the aspect ratio of the trench 413 should not be too large (e.g., the aspect ratio reaches 10:1), otherwise, when the trench 413 is filled with the deposition target material 422 in step S350, a void may occur in the middle of the trench 413. In other embodiments, the aspect ratio of the trench 413 may be adjusted to be higher (e.g., to an aspect ratio of 10:1, or even higher) for the void (void) to be present in the middle of the trench 413. The specific value of the aspect ratio of the trench 413 is limited by the filling capability of the stage used for the deposition of step S350 with respect to the target material 422.

In the above method for processing a semiconductor device structure, the trench 411 is connected to the target deep trench by etching the substrate structure 412 remained in the first region, and since the filling of the trench 411 and the trench 413 in step S330 and step S350 is performed respectively, the aspect ratio of the filled trench is greater than 1/2, and therefore, the thickness of the deposited target material 422 in step S330 and step S350 only needs half the width of the trench 411 and half the width of the trench 413 respectively, so that a large trench filled with the target material 422 can be obtained. Therefore, the processing method of the semiconductor device structure has the deep groove filling capability with the small depth-to-width ratio of tens to hundreds of micrometers, which is not possessed by the traditional process, and has the advantages of shorter process time, lower cost and shorter process time of corresponding CMP.

In one embodiment of the present application, the etching depth of step S330 is the same as the groove depth of the groove 411, i.e. the groove depth of the groove 413 is the same as the groove 411, and the bottom of the groove 413 is on the same plane as the bottom of the groove 411.

In one embodiment of the present application, the depth of the trench 411 is greater than 5 microns. In one embodiment of the present application, the depth of the grooves 413 is greater than 5 microns.

The present application accordingly provides a semiconductor device structure that may be formed by the method for fabricating a semiconductor device structure according to any of the foregoing embodiments. Referring to fig. 12, a deep trench 41 filled with a target material 422 is formed in a substrate 410 of a semiconductor device structure.

In one embodiment of the present application, deep groove 41 has a groove depth greater than 5 microns and a groove width greater than 10 microns.

In one embodiment of the present application, the base 410 comprises a semiconductor substrate. In one embodiment of the present application, the material of the semiconductor substrate may be undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like, and may be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors. In the embodiment shown in fig. 12, the substrate is made of monocrystalline silicon. Devices, such as transistors, e.g., NMOS and/or PMOS, may be formed on the substrate. Accordingly, a conductive member may be formed in the substrate, and the conductive member may be a gate, a source, or a drain of the transistor, or may be a metal interconnection structure electrically connected to the transistor, or the like. In addition, the substrate may be formed with an isolation structure such as STI (shallow trench isolation structure).

In one embodiment of the present application, the target material 422 is a different material than the substrate. Which may be silicon dioxide, siN, polysilicon, etc.

The deep trench 41 may be applied in a MEMS process. For example, in a dual-chip parallel microphone structure, the back cavities (back cavities) of two microphones need to be connected together through a communication cavity, and the depth and width of the back cavity and the communication cavity are both large. And the deep groove 41 may be used as the communication chamber.

It should be understood that, although the steps in the flowcharts of this application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or others.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims (10)

1. A method for processing a semiconductor device structure includes:

obtaining a substrate;

patterning the substrate, and forming at least one groove extending from the first surface of the substrate into the substrate in a first area of the substrate, wherein a substrate structure is remained in the first area except for each groove; the depth-to-width ratio of each groove is larger than 1/2, and the height-to-width ratio of the substrate structure remained in the first area is larger than 1/2;

depositing a target material to fill each groove;

removing the residual substrate structure of the first region through photoetching and etching;

depositing the target material fills the locations of the removed base structure.

2. The method of claim 1, wherein in the step of forming at least one trench in the first region of the substrate extending into the substrate from the first surface of the substrate, each trench has a depth greater than 5 microns.

3. The method of processing a semiconductor device structure of claim 1, further comprising the step of chemical mechanical polishing the first surface of the substrate after the step of depositing the target material to fill the removed locations of the substrate structure.

4. The method of claim 1, further comprising the step of chemical mechanical polishing the first surface of the substrate after the step of depositing a target material to fill each of the trenches and before the step of removing the substrate structure remaining in the first region by photolithography and etching.

5. The method according to claim 1, wherein in the step of removing the base structure remaining in the first region by photolithography and etching, an etching depth is the same as a depth of each of the trenches.

6. The method of processing a semiconductor device structure of claim 1, wherein the step of patterning the substrate comprises:

forming an etching opening in a second area of the first surface of the substrate by photoetching, wherein photoresist is formed in the second area except for the etching opening;

and etching the substrate by taking the photoresist as an etching barrier layer, forming at least one groove below the etching opening, and forming a substrate structure below the photoresist.

7. The method of claim 6, further comprising the step of removing photoresist from said substrate prior to said step of depositing a target material to fill each of said trenches.

8. The method of processing a semiconductor device structure of claim 1, wherein the step of depositing the target material fills the removed locations of the base structure is preceded by the step of removing photoresist on the base.

9. A semiconductor device structure having a deep trench formed in a substrate thereof, the deep trench being filled with the target material, wherein the semiconductor device structure is formed by processing the semiconductor device structure according to any one of claims 1-8.

10. The semiconductor device structure of claim 9, wherein the deep trench has a trench depth greater than 5 microns and a trench width greater than 10 microns.