CN114530447B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN114530447B CN114530447B CN202210433073.4A CN202210433073A CN114530447B CN 114530447 B CN114530447 B CN 114530447B CN 202210433073 A CN202210433073 A CN 202210433073A CN 114530447 B CN114530447 B CN 114530447B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure and the manufacturing method thereof, a substrate comprises a first element area and a second element area, a plurality of fin parts are formed on the substrate, the fin parts comprise a first fin part and a second fin part, the first fin part is positioned on the substrate of the first element area, and the second fin part is positioned on the substrate of the second element area; the fin structure comprises a first fin part, a second fin part, a first element region, a second element region and a plurality of adjacent first fin parts, wherein the cross-section width of the first fin part is not equal to that of the second fin part, the number of the first fin parts in the first element region and the number of the second fin parts in the second element region are more than two, the distance between every two adjacent first fin parts is different from that between every two adjacent second fin parts, so that two types of fin parts with different cross-section widths and different distances can be formed on the same substrate, finFETs with different characteristics can be formed, the coexistence goal of different FinFETs is realized, the diversification of the functions of the semiconductor structure is realized, and the use area of the semiconductor structure is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, the conventional planar device has not been able to meet the demand of people for high performance devices. A Fin-Field-Effect Transistor (FinFET) is a three-dimensional device that includes a Fin vertically formed on a substrate and a stacked gate intersecting the Fin. This design can greatly improve circuit control and reduce leakage current (leakage), and can also greatly shorten the gate length of the transistor.
Currently, in a FinFET semiconductor process, the cross-sectional widths of all fins on the same substrate are generally equal, i.e., the Critical Dimensions (CDs) of all fins are equal. To increase the device characteristics of the FinFET, the cross-sectional width of the fin needs to be increased to increase the current effect of the FinFET. But increasing the cross-sectional width of the fin increases the integrated capacitance of the device. According to the cut-off frequency
It is known that, when the parasitic capacitance C of the FinFET increases, the cutoff frequency fc decreases, and thus increasing the cross-sectional width of the fin portion affects the performance of some finfets having a desired cutoff frequency, such as Ring oscillators (Ring oscillators) and RF devices. Thus, the semiconductor structure formed in the current FinFET semiconductor processThe requirement of function diversification cannot be met.
Disclosure of Invention
An object of the present invention is to provide a semiconductor structure and a method for fabricating the same, which can realize diversification of functions of the semiconductor structure.
In order to achieve the above object, an aspect of the present invention provides a semiconductor structure including a substrate and a plurality of fins. The substrate includes a first element region and a second element region. The multiple fin portions are formed on the substrate and comprise a first fin portion and a second fin portion, the first fin portion is located on a first element region of the substrate, and the second fin portion is located on a second element region of the substrate; the cross-sectional width of the first fin portion is not equal to that of the second fin portion; the number of the first fin parts on the first element region is more than two, and the number of the second fin parts on the second element region is more than two; the distance between two adjacent first fin portions is different from the distance between two adjacent second fin portions.
Optionally, the base includes a substrate and a first epitaxial layer on the substrate, and the plurality of fins are located on the first epitaxial layer.
Optionally, the resistivity of the first epitaxial layer in the first element region is different from the resistivity of the first epitaxial layer in the second element region.
Optionally, the longitudinal cross section of the first fin portion is in a shape of a spliced graph of a regular trapezoid, a rectangle, an inverted trapezoid or a rectangle and a trapezoid; the longitudinal section of the second fin portion is in a shape of a regular trapezoid, a rectangle, an inverted trapezoid or a spliced graph of the rectangle and the trapezoid.
Optionally, the first element region is used to form a logic device, and the logic device includes the first fin portion; the second element region is used for forming a radio frequency device or a ring oscillator, and the radio frequency device or the ring oscillator comprises the second fin portion; the cross-sectional width of the first fin portion is greater than the cross-sectional width of the second fin portion.
Optionally, the width of the cross section of the first fin portion ranges from 11nm to 20nm, and the width of the cross section of the second fin portion ranges from 5nm to 10nm.
The invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps: providing a substrate comprising a first element region and a second element region; forming a plurality of fin parts on the substrate, wherein the fin parts comprise a first fin part and a second fin part, the first fin part is positioned on a first element region of the substrate, and the second fin part is positioned on a second element region of the substrate; the cross-section width of the first fin part is not equal to that of the second fin part; the number of the first fin parts on the first element region is more than two, and the number of the second fin parts on the second element region is more than two; the distance between two adjacent first fin portions is different from the distance between two adjacent second fin portions.
Optionally, the base includes a substrate and a first epitaxial layer on the substrate, and the first epitaxial layer covers an upper surface of the substrate.
Optionally, the method for forming the plurality of fin portions on the substrate includes: forming a second epitaxial layer on the substrate; forming a first patterned mask layer, etching the second epitaxial layer by taking the first mask layer as a mask, and forming a first fin part on a first element region of the substrate; and removing the first mask layer, forming a patterned second mask layer, etching the second epitaxial layer by taking the second mask layer as a mask, and forming a second fin part on the second element region of the substrate.
In the semiconductor structure and the manufacturing method thereof, a substrate comprises a first element area and a second element area, a plurality of fin parts are formed on the substrate, the fin parts comprise a first fin part and a second fin part, the first fin part is positioned on the first element area of the substrate, and the second fin part is positioned on the second element area of the substrate; the number of the first fin parts on the first element region is more than two, the number of the second fin parts on the second element region is more than two, the distance between every two adjacent first fin parts is different from the distance between every two adjacent second fin parts, so that two types of fin parts with different section widths (namely critical dimension CD) and different distances can be formed on the same substrate, finFETs with different characteristics can be formed, the coexistence of different FinFETs is realized, the diversification of semiconductor structure functions is realized, and the use area of a semiconductor structure is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.
Fig. 2 is a flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the invention.
Fig. 3 to 5 are schematic views of a step structure of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Description of reference numerals: 10-a substrate; 10 a-a first element region; 10 b-a second component area; 11-a first fin portion; 12-a second fin portion; 13-a first epitaxial layer; 14-a second epitaxial layer; 15-a first mask layer; 16-second mask layer.
Detailed Description
The semiconductor structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or imply that there is a number of the indicated technical features. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
In order to realize diversification of functions of the semiconductor structure, the invention provides the semiconductor structure which comprises a substrate and a plurality of fin parts. Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, the substrate includes a first element region 10a and a second element region 10b. The plurality of fin portions are formed on the substrate and comprise a first fin portion 11 and a second fin portion 12, the first fin portion 11 is located on a first element region 10a of the substrate, and the second fin portion 12 is located on a second element region 10b of the substrate; the cross-sectional width W1 of the first fin portion 11 is not equal to the cross-sectional width W2 of the second fin portion.
As shown in fig. 1, the base may include a substrate 10 and a first epitaxial layer 13 on the substrate 10, and the plurality of fins are located on the first epitaxial layer 13. Compared with the case that the plurality of fins are directly arranged on the substrate 10, the arrangement of the plurality of fins on the first epitaxial layer 13 is beneficial to improving the performance of the fins, and further improves the performance of the semiconductor structure.
In this embodiment, the substrate 10 may be a silicon substrate. In other embodiments, the substrate 10 may also be a semiconductor substrate such as a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. The material of the first epitaxial layer 13 may be polysilicon. Without being limited thereto, the material of the first epitaxial layer 13 may also be selected according to the material of the substrate 10. The thickness of the first epitaxial layer 13 may be 2 to 6 micrometers, for example, 4 micrometers. Without being limited thereto, the thickness of the first epitaxial layer 13 may be set as desired.
In order to meet the different characteristic requirements of finfets formed in different regions, in the present embodiment, the resistivity of the first epitaxial layer in the first element region 10a may be different from the resistivity of the first epitaxial layer in the second element region 10b. In different element regions, devices with different characteristics can be formed by setting different resistivity of the first epitaxial layer and different fin part section widths, and the electrical performance of the devices is good, so that the electrical performance of the semiconductor structure is improved while the function diversification of the semiconductor structure is realized.
In order to make the resistivity of the first epitaxial layer in the first element region 10a and the resistivity of the first epitaxial layer in the second element region 10b different, the doping species or the doping concentration of the first epitaxial layer in the first element region 10a and the first epitaxial layer in the second element region 10b are different.
As shown in fig. 1, in the present embodiment, the longitudinal cross-sectional shapes of the first fin portion 11 and the second fin portion 12 may be both regular trapezoids. But not limited thereto, the longitudinal cross-sectional shape of the first fin portion 11 may be a rectangle, an inverted trapezoid, or a spliced pattern of a rectangle and a trapezoid; the longitudinal cross-sectional shape of the second fin portion 12 may be rectangular, inverted trapezoidal, or a spliced pattern of rectangular and trapezoidal shapes. The rectangular and trapezoidal stitch pattern is, for example, a pattern in which the upper portion is rectangular and the lower portion is a regular trapezoid, or a pattern in which the upper portion is an inverted trapezoid and the lower portion is rectangular. The "longitudinal section" referred to herein is a plane perpendicular to the upper surface of the substrate (or the upper surface of the substrate 10 or the upper surface of the first epitaxial layer 13).
In this embodiment, the longitudinal cross-sectional shape of the first fin portion 11 and the longitudinal cross-sectional shape of the second fin portion 12 may be the same. However, the first fin 11 and the second fin 12 may have different longitudinal sectional shapes.
The plurality of fins are distributed on the substrate at intervals, the number of the first fins 11 on the first element region 10a may be two or more, and the number of the second fins 12 on the second element region 10b may be two or more. The distance between two adjacent first fin portions 11 and the distance between two adjacent second fin portions 12 may be different, which facilitates diversification of functions of the semiconductor structure.
As an example, the first element region 10a is used to form a logic device, which includes the first fin portion 11; the second element region 10b is used to form a radio frequency device or a ring oscillator that includes the second fin 12. In order to meet different characteristic requirements of different devices, for example, to meet different characteristic requirements of a logic device and a radio frequency device, the cross-sectional width W1 of the first fin 11 is greater than the cross-sectional width W2 of the second fin 12, and the resistivity of the first epitaxial layer on the first element region 10a is smaller than the resistivity of the first epitaxial layer on the second element region 10b. Specifically, the cross-sectional width W1 of the first fin 11 may be 11nm to 20nm, and the cross-sectional width W2 of the second fin 12 may be 5nm to 10nm.
In the semiconductor structure of this embodiment, a substrate includes a first element region 10a and a second element region 10b, a plurality of fin portions are formed on the substrate, the plurality of fin portions include a first fin portion 11 and a second fin portion 12, the first fin portion 11 is located on the first element region 10a of the substrate, and the second fin portion 12 is located on the second element region 10b of the substrate; the cross-sectional width W1 of the first fin portion 11 is not equal to the cross-sectional width W2 of the second fin portion 12, so that fin portions with different cross-sectional widths (namely, critical dimensions) can be formed on the same substrate, finfets with different characteristics can be formed, the coexistence of different finfets is achieved, the diversification of functions of a semiconductor structure is achieved, and the use area of the semiconductor structure is reduced.
The embodiment also provides a manufacturing method of the semiconductor structure, which can be used for manufacturing the semiconductor structure. Fig. 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the invention. As shown in fig. 1 and fig. 2, the method for manufacturing the semiconductor structure includes:
s1, providing a substrate, wherein the substrate comprises a first element region 10a and a second element region 10b; and
s2, forming a plurality of fin parts on the substrate, wherein the fin parts comprise a first fin part 11 and a second fin part 12, the first fin part 11 is located on a first element region 10a of the substrate, and the second fin part 12 is located on a second element region 10b of the substrate; the cross-sectional width W1 of the first fin portion 11 is not equal to the cross-sectional width W2 of the second fin portion 12; the number of the first fin portions 11 on the first element region 10a is more than two, and the number of the second fin portions 12 on the second element region 10b is more than two; the distance between two adjacent first fin portions 11 is different from the distance between two adjacent second fin portions 12.
Specifically, the base may include a substrate 10 and a first epitaxial layer 13 located on the substrate 10, and the first epitaxial layer 13 may cover an upper surface of the substrate 10.
Before the plurality of fins are formed, the resistivity of the first epitaxial layer on the first element region 10a may be made different from the resistivity of the first epitaxial layer on the second element region 10b by implanting different dopants, such as copper (Cu), into different regions of the first epitaxial layer 13 or adjusting the doping concentration of different regions of the first epitaxial layer 13. But not limited thereto, in the substrate provided by the supplier, the epitaxial layer disposed on the substrate surface of the first element region 10a is different from the epitaxial layer disposed on the substrate surface of the second element region 10b, and the epitaxial layer on the substrate surface of the first element region 10a and the epitaxial layer on the substrate surface of the second element region 10b together constitute the first epitaxial layer 13, so that the resistivity of the first epitaxial layer of the first element region 10a and the resistivity of the first epitaxial layer of the second element region 10b are different and do not need to be adjusted by an additional ion implantation process.
Fig. 3 to 5 are schematic views of a step structure of a method for fabricating a semiconductor structure according to an embodiment of the invention. In this embodiment, the method of forming the plurality of fins on the substrate may include: as shown in fig. 3, a second epitaxial layer 14 is formed on the substrate; as shown in fig. 4, a patterned first mask layer 15 is formed, the second epitaxial layer 14 is etched by using the first mask layer 15 as a mask, and a first fin 11 is formed on the first device region 10a of the substrate, for example, the remaining second epitaxial layer on the first device region 10a is used as the first fin 11; as shown in fig. 5, the first mask layer 15 is removed, a patterned second mask layer 16 is formed, the second epitaxial layer 14 is etched by using the second mask layer 16 as a mask, and a second fin portion 12 is formed on the second element region 10b of the substrate, for example, the remaining second epitaxial layer 14 on the second element region 10b is used as the second fin portion 12. The material of the second epitaxial layer 14 comprises polysilicon.
It should be noted that, the present specification is described in a progressive manner, and the manufacturing method of the semiconductor structure described later mainly illustrates the differences from the semiconductor structure described earlier, and the same and similar parts may be referred to each other.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "one embodiment" or "the present embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (6)
1. A semiconductor structure, comprising:
the substrate comprises a first element area and a second element area, the substrate comprises a substrate and a first epitaxial layer positioned on the substrate, and the resistivity of the first epitaxial layer in the first element area is different from that of the first epitaxial layer in the second element area; and
the multiple fin parts are formed on the substrate and located on the first epitaxial layer, and each fin part comprises a first fin part and a second fin part, wherein the first fin part is located on a first element region of the substrate, and the second fin part is located on a second element region of the substrate; the cross-section width of the first fin part is not equal to that of the second fin part; the number of the first fin portions on the first element region is more than two, and the number of the second fin portions on the second element region is more than two; the distance between two adjacent first fin portions is different from the distance between two adjacent second fin portions.
2. The semiconductor structure of claim 1, wherein the first fin has a right trapezoid, a rectangle, an inverted trapezoid, or a mosaic of a rectangle and a trapezoid in a longitudinal cross-sectional shape; the longitudinal section of the second fin portion is in a shape of a regular trapezoid, a rectangle, an inverted trapezoid or a spliced graph of the rectangle and the trapezoid.
3. The semiconductor structure of claim 1, in which the first element region is to form a logic device, the logic device comprising the first fin; the second element region is used for forming a radio frequency device or a ring oscillator, and the radio frequency device or the ring oscillator comprises the second fin portion; the cross-sectional width of the first fin portion is greater than the cross-sectional width of the second fin portion.
4. The semiconductor structure according to claim 3, wherein a cross-sectional width of the first fin is 11nm to 20nm, and a cross-sectional width of the second fin is 5nm to 10nm.
5. A method for fabricating a semiconductor structure, comprising:
providing a base, wherein the base comprises a first element area and a second element area, the base comprises a substrate and a first epitaxial layer positioned on the substrate, the first epitaxial layer covers the upper surface of the substrate, and the resistivity of the first epitaxial layer in the first element area is different from that of the first epitaxial layer in the second element area; and
forming a plurality of fin portions on the substrate, wherein the plurality of fin portions are located on the first epitaxial layer and comprise a first fin portion and a second fin portion, the first fin portion is located on a first element region of the substrate, and the second fin portion is located on a second element region of the substrate; the cross-section width of the first fin part is not equal to that of the second fin part; the number of the first fin portions on the first element region is more than two, and the number of the second fin portions on the second element region is more than two; the distance between two adjacent first fin portions is different from the distance between two adjacent second fin portions.
6. The method of fabricating the semiconductor structure of claim 5, wherein forming the plurality of fins on the substrate comprises:
forming a second epitaxial layer on the substrate;
forming a first patterned mask layer, etching the second epitaxial layer by taking the first mask layer as a mask, and forming the first fin part on the first element region of the substrate; and
and removing the first mask layer, forming a patterned second mask layer, etching the second epitaxial layer by taking the second mask layer as a mask, and forming the second fin part on the second element region of the substrate.
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