WO2019132928A1

WO2019132928A1 - Group iii-nitride (iii-n) logic and rf devices and their methods of fabrication

Info

Publication number: WO2019132928A1
Application number: PCT/US2017/068759
Authority: WO
Inventors: Sansaptak DASGUPTA; Han Wui Then; Marko Radosavljevic; Tristan A. TRONIC
Original assignee: Intel Corporation
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2019-07-04

Abstract

A device including a first fin structure and an adjacent second fin structure. Each fin structure includes III-Nitride (III-N) channel material and a III-N polarization charge inducing layer. The device further includes gate structures above the polarization charge inducing layers and on a portion of sidewalls of the first fin structures. The device further includes a pair of source and drain structures on opposite sides of the gate structures.

Description

GROUP III-NITRIDE (III-N) LOGIC AND RF DEVICES AND THEIR METHODS OF FABRICATION

BACKGROUND

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. For example, in radio frequency (RF) communication, the RF front-end is a generic term for the circuitry between an antenna and a digital baseband system. Such RF front-end components may include one or more diodes in conjunction with one or more transistors, such as one or more field-effect transistors (FETs). Due, in part, to their large bandgap and high mobility, gallium nitride (GaN) and other III-N semiconductor materials are suited for applications such as high-frequency and high-power.

For many non-silicon device materials, it can be challenging to integrate logic with RF devices. Non-planar GaN devices may be integrated with RF devices as an attractive solution for GaN based integrated devices for enhanced performance and/or reduce device power

consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified“ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 A illustrates a cross-sectional view of a pair of III-N transistors in accordance with embodiments of the present disclosure.

Figure 1B illustrates a cross-sectional view of a gate formed around a fin structure of a depletion mode III-N transistor, in accordance with an embodiment of the present disclosure.

Figure 1C illustrates a cross-sectional view of a gate formed around a fin structure of an enhancement mode III-N transistor, in accordance with an embodiment of the present disclosure.

Figure 1D illustrates a cross-sectional view of a gate electrode on a gate dielectric layer.

Figure 1E illustrates a cross-sectional view of a mobility enhancement layer between the fin structure and the polarization charge inducing layer.

Figure 2A illustrates a cross-sectional view of a pair of III-N transistors, each having a different polarization charge inducing layer, in accordance with embodiments of the present disclosure.

Figure 2B illustrates a cross-sectional view of a gate formed around a fin structure of a depletion mode III-N transistor, in accordance with an embodiment of the present disclosure.

Figure 2C illustrates a cross-sectional view of a mobility enhancement layer between the fin structure and the polarization charge inducing layer, in accordance with an embodiment of the present disclosure.

Figure 3 A illustrates a cross-sectional view of a III-N RF transistor and a pair of logic III- N transistors, in accordance with embodiments of the present disclosure.

Figure 3B illustrates a cross-sectional view of a gate formed on a large mesa structure, in accordance with an embodiment of the present disclosure.

Figure 3C illustrates a plan view of a III-N RF transistor and a plurality of logic III-N transistors, in accordance with embodiments of the present disclosure.

Figure 3D illustrates a plan view of a III-N RF transistor and a plurality of logic III-N transistors, in accordance with embodiments of the present disclosure.

Figure 4 illustrates a cross-sectional view of a III-N RF transistor and a pair of logic III-N transistors each having a different polarization charge inducing layer, in accordance with embodiments of the present disclosure.

Figure 5 is a flow diagram illustrating methods of forming III-N RF transistor and a plurality of logic III-N transistors, in accordance with embodiments of the present disclosure.

Figure 6A illustrates a cross-sectional view of a stack of III-N materials formed above a substrate.

Figure 6B illustrates a cross-sectional view the structure of Figure 6A following the formation of a polarization charge inducing layer on the stack of III-N materials formed above the substrate.

Figure 6C illustrates a cross-sectional view of the structure of Figure 6B following the formation of a mesa region and a logic region and the formation of isolation.

Figure 6D illustrates a plan view of the structure of Figure 6C depicting the plurality of fin structures in the logic region adjacent the mesa region.

Figure 6E illustrates the structure of Figure 6A following the formation of a mesa region and a logic region and the formation of isolation, in accordance with embodiments of the present disclosure.

Figure 6F illustrates a cross-sectional view of the structure of Figure 6E following the formation of a first polarization charge inducing layer in the mesa region and on a first fin structure of the logic region.

Figure 6G illustrates the structure of Figure 6F following the formation of a sacrificial dielectric layer and the formation of an opening over the first fin structure, in accordance with embodiments of the present disclosure.

Figure 6H illustrates the structure of Figure 6G following the formation of a second polarization charge inducing layer on a second fin structure of the logic region.

Figure 7 illustrates a cross-sectional view of the structure of Figure 6C following the formation of trenches in portions of the polarization charge inducing layer, and in portions of the III-N material adjacent to the isolation.

Figure 8 illustrates a cross-sectional view of the structure of Figure 7 following the formation of drain structures and source structures in the trenches.

Figure 9 illustrates a cross-sectional view of the structure of Figure 8 following the deposition of a dielectric layer on the plurality of source structures, drain structures and on the polarization charge inducing layer.

Figure 10A illustrates a cross-sectional view the structure of Figure 9 following the formation of gate openings in the dielectric layer over a portion of the polarization charge inducing layer in the mesa region and over a portion of the polarization charge inducing layer of a first fin structure.

Figure 10B illustrates a cross-sectional view the isolation surrounding the polarization charge inducing layer in the mesa region.

Figure 10C illustrates a cross-sectional view depicting a recess in the isolation surrounding the first fin structure in the logic region.

Figure 10D illustrates a plan view of the opening formed over a portion of the polarization charge inducing layer and the isolation surrounding the first fin structure in the logic region.

Figure 11 A illustrates a cross-sectional view of the structure of Figure 10A following the formation of a gate in the mesa region and the formation of a gate over the first fin structure in logic region.

Figure 11B illustrates a plan view of the gate formed over the first fin structure in the logic region.

Figure 11C illustrates a cross-sectional view of the gate formed around the first fin structure, in accordance with an embodiment of the present disclosure.

Figure 12A illustrates a cross-sectional view the structure of Figure 11 A following the formation of a second dielectric layer on the first dielectric layer and the formation of a gate opening over a portion of the polarization charge inducing layer of a second fin structure.

Figure 12B illustrates a plan view of the opening formed over a portion of the

polarization charge inducing layer and the isolation surrounding the second fin structure in the logic region.

Figure 12C illustrates a cross-sectional view depicting a recess in the isolation surrounding the second fin structure in the logic region.

Figure 13A illustrates a cross-sectional view the structure of Figure 12A following the recess of the portion of the polarization charge inducing layer on the second fin structure exposed by the gate opening.

Figure 13B illustrates an enhanced cross-sectional view of the structure of the recess in the polarization charge inducing layer.

Figure 14 illustrates a cross-sectional view of the structure of Figure 13A following the formation of a gate over the second fin structure in logic region to form a second logic transistor.

Figure 15 illustrates a cross-sectional view of the structure of Figure 14 following the formation of source and drain contact openings in the mesa transistor region and in the logic transistor region.

Figure 16 illustrates a cross-sectional view of the structure of Figure 15 following the formation of source contacts and drain contacts on the mesa transistor and on the first and on the second logic transistor.

Figure 17 is a functional block diagram of a group III-N SoC implementation of a mobile computing platform, in accordance with an embodiment of the present disclosure.

Figure 18 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 19 illustrates an integrated circuit (IC) structure that includes one or more transistors, all arranged in accordance with at least some embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Devices including III-N semiconductor materials for logic, SoC and memory applications and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as enhancement mode operations associated with III-N devices, are described in lesser detail in order to not

unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”, and“below” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present disclosure may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to“an embodiment” or“one embodiment” or“some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase“in an embodiment” or“in one embodiment” or“some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms“a”,“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term“and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms“coupled” and“connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). The terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of’ or“one or more of’ can mean any combination of the listed terms. For example, the phrase“at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. The ability to co-integrate logic circuitry fashioned from III-N materials alongside RF power amplifiers, for example will provide enhanced capability as well as help realize significant cost savings from integrating logic and PA. In an embodiment of the present disclosure, an RF device such as a power amplifier is co-integrated with a fin-FET on insulator device, where the RF device and the fin-FET on insulator devices both include a first III-N material as a channel layer. The fin-FET on insulator devices may further include an enhancement (E) mode transistor adjacent to and electrically isolated from a depletion (D) mode transistor. An E-mode transistor is in an off-state when the gate-source voltage is zero and a D-mode transistor is in an on-state when the gate-source voltage is zero.

The RF device includes a transistor having a large mesa structure, which includes the channel layer. A polarization charge inducing layer is on a portion of the mesa structure. The polarization charge inducing layer includes a III-N material that induces a 2-dimensional charge carrier sheet, such as a 2D electron gas (2DEG), in the channel layer. The 2D charge carrier sheet may form below an interface between the polarization charge inducing layer and the underlying first III-N material of the channel layer. A gate is above the polarization charge inducing layer. A source structure and a drain structure is on either side of the gate and on the mesa structure.

While the mesa structure may share the same channel material as each of fin structures, the mesa structure and fin structures are electrically isolated from each other. Both the fin and mesa structures may include a fourth III-N material that has a large band-gap and thus limits substrate leakage currents.

A fin structure in each of the E-mode and D-mode fin-FET transistors includes the channel layer. Each of the E-mode and D-mode fin-FET transistors further include a polarization charge inducing layer on the fin structure. The fin-FET transistors further include a gate structure above a portion of the polarization charge inducing layer and a source and a drain structure on either side of the gate structure. In each of the enhancement mode and depletion mode fin-FET transistors, the gate structures have sidewall portions that are adjacent to sidewalls of the fin structures. When the gate structures are voltage biased during operation of an integrated circuit, the sidewall portions of the gate structures can provide an electric field to affect the 2DEG within the channel providing for an improved transistor operation. Unlike the mesa structure that may have lateral dimensions ranging in the microns, the fin structures may have a width that are in the order of tens of nanometer to a couple of hundred nanometers. Thus, the sidewall potions of the gate structure which may be separated by only tens of nanometers can exert an electric field that may be comparable to an electric field created by a portion of the gate structure directly above the polarization charge inducing layer.

Figure 1 A illustrates a cross-sectional illustration of a device 100, including a depletion (D) mode transistor 100 A adjacent to an enhancement (E) mode transistor 100B. The E-mode transistor is separated from the D-mode transistor lOOAby an isolation 106. Examples of the isolation layer 106 may include any material that has sufficient dielectric strength to provide electrical isolation such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

The D-mode transistor 100A includes a fin structure 102 having a channel layer 108 having a first Ill-Nitride (III-N) material above a buffer layer 126. The buffer layer 126 is above a substrate 130. The D-mode transistor further includes a polarization layer 110 above the fin structure 102, a gate structure 114 on the polarization layer 110. The polarization charge inducing layer 110 induces a 2-dimensional electron gas (2DEG is indicated by the dashed lines 111) within channel layer 108 near an interface between the polarization charge inducing layer 110 and the channel layer 108. The 2DEG renders a portion of the channel layer 108 under the polarization charge inducing layer 110 electrically active. The D-mode transistor 100A further includes a source structure 118 and a drain structure 120 on opposite sides of the gate structure 114 coupled to recessed portions of the fin structure 102. The D-mode transistor 100A further includes a source contact 132 coupled with the source structure 118 and a drain contact 134 coupled with the drain structure 120.

The E-mode transistor 100B includes a fin structure 104 having the first Ill-Nitride (III- N) material above the buffer layer 126. The E-mode transistor 100B further includes a polarization layer 112 above the fin structure 104, and a gate structure 116 on the polarization layer 112. A polarization charge inducing layer portion 112A under the gate structure 116 is thinner than the polarization layer 110 under the gate structure 114. The thinner polarization charge inducing layer portion 112A is unable to induce a 2DEG and hence the 2DEG is interrupted under the polarization charge inducing layer 112 (break in dashed lines 113). The E- mode transistor 100B further includes a source structure 122 and a drain structure 124 on opposite sides of the gate structure 116 and coupled to recessed portions of the fin structure 104. The E-mode transistor 100B further includes a source contact 132 coupled with the source structure 118 and a drain contact 134 coupled with the drain structure 120.

In an embodiment, the source structures 118 and 122 and drain structures 120 and 124, have uppermost surfaces that are corrugated and above the level of the isolation 106. In an embodiment, the source structures 118 and 122 and drain structures 120 and 124 extend laterally (e.g., in the X-dimension) onto the isolation 106.

Figure 1B illustrates a cross-sectional view, taken along a line A-A’ shown in Figure 1 A. As shown, the gate structure 114 is over a sidewall of the fin structure 102 and on the

polarization charge inducing layer 110. In the cross-sectional view, the fin structure 102 has a pair of vertical sidewalls. The 2DEG extends from one vertical sidewall to the opposing sidewall of the fin structure 102. In an embodiment, the fin structure 102 has a width W_F between 5nm and lOOnm and a height H_F, between 500nm and 2 microns. In another example (not depicted), sidewalls of a fin structure may be tapered to provide an increasing width from an uppermost surface of the fin structure to a lowermost surface of the fin structure 102.

The isolation 106 is recessed below an uppermost surface of the polarization charge inducing layer 110, by an amount HR. In an embodiment, the polarization charge inducing layer 110 has a thickness that depends on the choice of material and is between 5nm and 30nm. The recess HR depends on the thickness of the polarization charge inducing layer 110. The recess in the isolation 106 exposes, sidewalls of the polarization charge inducing layer 110, two opposing sidewall portions 102 A of the fin structure 102 and the 2DEG between the two opposing sidewall portions 102A. The gate structure 114 has two opposing sidewall portions that are in direct contact with the 2DEG. In an embodiment, the recess HR in the isolation 106 is at least 2nm below the 2DEG. A recess HR of 7nm-50nm exposes the sidewall 102A by an amount between 2nm - l5nm.

In one embodiment, when the gate structure 114 is biased negatively during operation, an electric field is created by a portion of the gate above the polarization charge inducing layer 110 and affects the 2DEG. Additionally, portions of the gate structure 114 directly adjacent to the sidewall portions 102A also give rise to electric fields in the channel layer 108. When the fin structure 102 has a sufficiently small width (e.g., between lOnm and lOOnm) and the sidewall portions 102A is recessed below the 2DEG by at least 2nm-3nm, the 2DEG in the vicinity of the sidewall portions l02A may be affected when the gate structure 114 is electrically biased. The cumulative electric field on three sides of the fin structure 102 may advantageously turn off the D-mode transistor 100A faster than a transistor having a gate structure confined above a polarization charge inducing layer or than a transistor where the fin structure 102 has a width that is substantially greater than lOOnm, for example one micron or more.

Figure 1C illustrates a cross-sectional view of the gate structure 116 around the fin structure 104 of an enhancement mode III-N transistor 100B, where the cross-section is taken along a line B-B’ in the Figure 1 A. The line B-B’ cuts along the thinned polarization charge inducing layer portion 112A. In some embodiments, the portion of the polarization charge inducing layer portion 112A under the gate structure 116 is less than 10% of the thickness of the polarization charge inducing layer 110 under the gate structure 114 (Figure 1B). In an embodiment, the thinned polarization charge inducing layer portion H2A has a thickness between 0.7nm-2.5nm and depends on the choice of material. As a result, the isolation 106, illustrated in Figure 1C, is recessed below an uppermost surface of the thinned polarization charge inducing layer 112A, by the recess H_R2 that is less than the recess H_R illustrated in Figure 1B. In an embodiment, the recess H_R2 extends at least 2nm below the lowermost surface of the thinned polarization charge inducing layer 112 A. In other embodiments, the recess H_R2 extends by as much as 50nm below the lowermost surface of the thinned polarization charge inducing layer 112A. The recess in the isolation 106 exposes two opposing sidewall portions 104A of the fin structure 104 and sidewalls of the thinner polarization charge inducing layer portion 112A.

The gate structure 116 has two opposing sidewall portions that are in direct contact with the two opposing sidewall portions 104A and sidewalls of the thinner polarization charge inducing layer portion 112A. In an embodiment, the recess H_R2 in the isolation 106 is approximately between 5nm-20nm. A recess H_R2 of approximately 5nm-20nm exposes the sidewall l04Aby approximately 2.5nm-l9.25nm. At zero gate bias, the 2DEG is absent from a portion of the fin structure 104 under the thinner polarization charge inducing layer portion 112A but is present under the thicker portions of the polarization charge inducing layer 112 (Figure 1 A). In an embodiment, when the fin structure 102 has a width W_F between lOnm and lOOnm and the gate structure 116 is biased positively, an electric field maybe created in the vicinity of sidewalls 104A, which generates a 2DEG under the thinner polarization charge inducing layer portion 112A.

Figure 1D illustrates a cross-sectional view of components of the gate structure 114. In an embodiment, the gate structure 114 includes a gate dielectric layer 114A and a gate electrode 114B on the gate dielectric layer 114A. In the illustrative embodiment, the gate dielectric layer 114A is adjacent to three sides of the polarization charge inducing layer 110, sidewalls 102, the 2DEG and on the isolation 106. In an embodiment, the gate structure 116 also includes a gate dielectric layer that is the same or substantially the same as the gate dielectric layer 114A and a gate electrode that is the same or substantially the same as the gate electrode 114B on the gate dielectric layer (not shown).

The gate dielectric layer 114A may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric embodiments, the gate dielectric layer 114A is a metal oxide (e.g., including oxygen and one or more metals, such as, but not limited to, aluminum, hafnium, zirconium, tantalum or titanium). In another embodiment, the gate dielectric layer 114A includes a silicon dioxide or a silicon nitride. In some examples, the gate dielectric layer 114A has a thickness between 2nm and 10 nm.

In an embodiment, the gate electrode 114B includes a metal such as but not limited to Pt, Ni and an alloy such as TiN or TaN. In one such embodiment, the gate electrode 114B has a length, LG, approximately in the range of l0-30nm. In some embodiments, the gate electrode 114B further includes a work function metal and a gate cap. The work function metal may include a metal such as Pt, Ni, and an alloy such as TiN or TaN and the gate cap may include a metal such as W.

Referring once again to Figure 1 A, in an embodiment, the channel layer 108 includes binary gallium nitride (GaN). In one such embodiment, the channel layer 108 has a relatively high carrier mobility, (greater than 500 cm² V ¹). In other embodiments, the channel layer 108 includes one or more ternary III-N alloys such as AlGaN, AllnN, or a quaternary alloy of GaN including at least three group III elements and nitrogen, such as In_xAl_yGai_-x-yN, where x ranges from 0.01-0.1 and y ranges from 0.01-0.1. The channel layer 108 may be a substantially un doped III-N material (i.e., 0₂ impurity concentration minimized) for minimal impurity scattering. Depending on applications, the channel layer 108 has a thickness approximately between lOOnm to 5um.

In an embodiment, the polarization charge inducing layer 110 may include any binary, ternary, or quaternary III-N alloy that has a spontaneous polarization and/or piezoelectric polarization suitable for the chosen channel material. In an embodiment, the polarization charge inducing layer 110 has a thickness sufficient to introduce a polarization difference in the interface between the channel layer 108 and the polarization charge inducing layer 110, creating a 2DEG 111 in the vicinity of an uppermost surface of the channel layer 108. In an embodiment, the polarization charge inducing layer 110 includes a material such as, but not limited to, Al_zGai_ _ZN, Al_wIn_l-wN, or A1N, where Z ranges from 0.2-0.3 and W ranges from 0.7-0.85. One combination includes a AlGaN polarization charge inducing layer 110 and a binary GaN channel layer 108. In one such combination, an AlGaN polarization charge inducing layer 110 has a bandgap (e.g., 3.7 eV) that is wider than the bandgap of a GaN III-N material 102 (e.g., 3.4 eV), facilitating a quantum well at the interface between the AlGaN polarization charge inducing layer 110 and the GaN III-N material 102. The thickness of the polarization charge inducing layer 110 may vary with material composition, for instance a layer of Al_zGai_-zN can have a thickness between 5nm-30nm depending on the Al concentration. The thickness may vary inversely with the Al concentration. For example, for Z between 20 and 50 atomic percent, the thickness may vary between 30nm and 5nm, respectively. In an exemplary embodiment, the polarization charge inducing layer 110 includes an Al_zGai_-zN, where Z is 30 atomic percent, and the thickness of the polarization charge inducing layer 110 is 25nm. In another example where the polarization charge inducing layer 110 is Al_wIn_l-wN, the thickness is between l0nm-20nm depending on the Al concentration. The thickness may again vary inversely with the Al concentration. For example, for W between 60 and 80 atomic percent, the thickness may vary between 20nm and lOnm, respectively. In the illustrative embodiment, the polarization charge inducing layer 112 and the polarization charge inducing layer 110 have substantially the same composition and thickness.

In one or more embodiments, an intermediate layer between the polarization charge inducing layer 110 and the channel layer 108 may help to increase mobility of the 2DEG. Figure 1E illustrates a cross-sectional view of a mobility enhancement layer 128 between the channel layer 108 and the polarization charge inducing layer 110. In an embodiment, the mobility enhancement layer 128 has a thickness that is less than lnm. The combined thicknesses of the mobility enhancement layer 128 and the thinned polarization charge inducing layer portion 112A (in Figure 1 A), is insufficient to introduce a 2DEG. Likewise, in an embodiment (not shown), a mobility enhancement layer 128 between the polarization charge inducing layer 112 and the channel layer 108 may also help to increase mobility of the 2DEG.

In an embodiment, the mobility enhancement layer 128 and the underlying channel layer 108 are binary alloys. In one such embodiment, when the mobility enhancement layer 128 and the underlying channel layer 108 are binary alloys, enhanced electron confinement can occur in the channel layer 108. Enhanced electron mobility may result from reduced alloy scattering. In one such embodiment, when the mobility enhancement layer 128 is an A1N layer and the underlying channel layer 108 is GaN, the A1N mobility enhancement layer 128 has a bandgap (6.02 eV) that is wider than the bandgap of the GaN channel layer 108 (3.4 eV), facilitating a quantum well at an interface between the A1N mobility enhancement layer 128 and the GaN channel layer 108. The presence of the quantum well and reduced alloy scattering may enable enhanced electron mobility in the channel layer 108.

Referring once again to Figure 1A, in an embodiment, the source structures 118 and 122, and drain structures 120 and 124 include a III-N material. This III-N material may be advantageously single crystalline. In some such embodiments, the crystalline III-N material is lattice matched to the channel layer material. In one exemplary embodiment where the channel layer 108 includes a material such as GaN, the source structures 118 and 122, and drain structures 120 and 124 include a single crystal of InGaN. In the illustrative embodiment, the source structures 118 and 122, and drain structures 120 and 124, are crystals having faceted sidewalls, that are approximately 60 degrees with respect to plane of the substrate 130.

In an exemplary embodiment, the third III-N material includes an impurity dopant such as an n-type dopant (donor impurity). Examples of an n-type dopant includes an impurity such as Si or Ge. In one embodiment, the n-type impurity is silicon. As a further example, the silicon n-type dopant may have a n-dopant density of at least lel9/cm³. The N-type doping can reduce the bandgap between the source structures 118 and 122 and the source contacts 132 and 136. Likewise, doping of the third III-N material can reduce the bandgap between the drain structures 120 and 124 and the drain contacts 134 and 138. A reduced bandgap may lead to a reduced contact resistances, which is increasingly important as the source structures 118 and 122 and drain structure 120 and 124 have surface areas that become limited by the width (e.g., Z-axis) and length (e.g., X-axis) of the fin structure 102. In an embodiment, the height and length of the source structures 118 and 122 and drain structures 120 and 124, the n-type dopant density, and 3D faceted sidewalls all help to achieve a transistor on-resistance value that is less than 300 ohm- um. Depending on embodiments, the source structures 118 and 122 and the drain structures 120 and 124 each have a thickness that is between 40nm-60nm.

In an embodiment, the source contacts 132 and 136, and the drain contacts 134 and 138 each include a multi-layer stack. In an embodiment, the multi-layer stack includes two or more distinct layers of metal such as a layer of Ti, Ru or Al and a conductive cap on the layer of metal. The conductive cap may include a material such as W or Cu.

The buffer 126 may include a plurality of layers of III-N materials above the substrate 130. In an embodiment, the buffer layer 126 has a thickness that minimizes crystal defects in the channel layer 108 that would ordinarily arise from lattice mismatch between the channel layer 108 and the underlying substrate 130. In an embodiment, the buffer layer 126 has a thickness that is between 400nm - 3 microns. The layers may be interleaved with two or more layers of III-N materials such as but not limited to Al_zGai_-zN, Al_wIn_l-wN, or A1N. In one embodiment, the buffer 126 includes three layers of Al_zGai_-zN on a layer of A1N, where the three layers of Al_zGai_ _ZN have decreasing Al content in each layer. In one such embodiment, the uppermost layer has a lowest amount of Al content of the three layers, resulting in a large band-gap that limits substrate leakage currents. In a specific example, the uppermost layer has an Al content between 10-30 atomic percent, the second layer below the upper most layer has an Al content between 30-60 atomic percent and the third layer below the second layer has an Al content between 60-80 atomic percent.

In an embodiment, the substrate 130, includes a semiconductor material. In some embodiments, the buffer 126 and the substrate 130 have mismatched lattice structures. The lattice mismatch between the buffer layer 126 and the substrate 130 may be between 15% - 50%. Exemplary substrates include, but are not limited to, silicon, silicon germanium (Ge) or silicon carbide (SiC). In an exemplary embodiment, the substrate 130 is a silicon substrate having a (100) top surface. A silicon substrate with a (100) top surface may facilitate co-integration of silicon CMOS transistor technology with a III-N material. In a second embodiment, a silicon substrate has a (111) top surface.

Figure 2A illustrates a cross-sectional view of a device 200 including a D-mode transistor 200A and the E-mode transistor 100B (described in association with Figure 1 A and 1C).

Transistor 200Ahas a different polarization charge inducing layer than transistor 100B, in accordance with embodiments of the present disclosure. In the illustrative embodiment, transistor 200A includes a fin structure 202, a polarization charge inducing layer 210 on the fin structure 202, the gate structure 114 on the polarization charge inducing layer 210, and the source structure 118 and drain structure 120 on either side of the gate structure 114. The fin structure 202 includes the channel layer 108 described in association with Figure 1 A.

In the illustrative embodiment, the polarization charge inducing layer 210 includes a compositionally graded III-N material. In some embodiments, the polarization charge inducing layer 210 includes aluminum, with some examples being Al_zGa_l-zN, Al_wIn_l-wN, or A1N. In an embodiment, the aluminum content increases with distance from the channel layer 108.

Depending on embodiments, the aluminum content increases from 0.1% to 50% with distance from the channel layer 108. In a specific example, the polarization charge inducing layer 210 includes a layer of Al_zGai_-zN, where the aluminum content increases over the y-axis from 0.1% at an interface of the channel layer 108 and reaches a value of approximately 30% at the uppermost surface of the polarization charge inducing layer 210. When the aluminum

concentration so varies across a thickness of the polarization charge inducing layer 210, a 3- dimensional electron gas 211 (3DEG) exists over that thickness of the polarization charge inducing layer 210. In an embodiment, the polarization charge inducing layer 210 has a thickness between 5nm and 25nm. For a fixed amount of Al grading (for e.g. between 0.1% to 30%) the 3DEG has an amount of charge that varies with the total thickness of the polarization charge inducing layer 210. For example, an AlGaN - polarization charge inducing layer 210 having a 20 nm thickness graded from 0% - 30% Al has more charge than a AlGaN - polarization charge inducing layer 210 having a 30 nm. The presence of polarization charge inducing layer 210 having a graded Al content may also increase the total volume of the electron gas beyond the lowermost surface of the polarization charge inducing layer 210, into upper portions of the channel layer 108. The polarization charge inducing layer 210 may have a thickness that is independent of the thickness of the polarization charge inducing layer 112.

Figure 2B illustrates a cross-sectional view, taken along a line A-A in the Figure 2A, of the gate structure 114 on an uppermost surface and on sidewalls of the polarization charge inducing layer 210 and on sidewalls of the fin structure 202 of the D-mode transistor 200A. In the illustrative embodiment, the polarization charge inducing layer 210 and the fin structure 202 each have a pair of vertical parallel sidewalls. The 3DEG extends from one vertical sidewall of the polarization charge inducing layer 210 to the opposing sidewall of the polarization charge inducing layer 210. The isolation 106 is recessed below an uppermost surface of the polarization charge inducing layer 210, by an amount HR. The recess in the isolation 106 exposes two opposing sidewall portions 202 A of the fin structure 202 and sidewall portions 210A. The gate structure 114 has two opposing sidewall portions that are in direct contact with the 3DEG. In an embodiment, the recess HR in the isolation 106 is between 6nm-35nm. Since the 3DEG is confined to the polarization charge inducing layer 210, the recess in the isolation 106 below a lowermost surface of the polarization charge inducing layer 210 may help to ensure that the gate 114 is fully adjacent to the sidewalls 210A. In most embodiments, the recess HR extends approximately between 2nm-l5nm below the interface between the polarization charge inducing layer 210 and the channel layer 108 and expose sidewall portions 202A of the fins structure 202.

In an embodiment, the polarization charge inducing layer 210 and the fin structure 202 each have widths W_F between lOnm and lOOnm. The 3DEG in the vicinity of the sidewalls 210A may be influenced when the gate structure 114 is electrically biased in a manner similar to the discussion above. In one embodiment, when the gate structure 114 is biased negatively, the electric field created by the gate structure from directly above the polarization charge inducing layer 210 will affect the 3DEG throughout the volume of the polarization charge inducing layer 210 under the gate structure 114. Additionally, portions of the gate structure 114 directly adjacent to the sidewall portions 2lOAmay create an electric field affecting the 3DEG in the vicinity of sidewalls 210A. Thus, the cumulative electric field resulting from the gate structure 114 on three sides of the polarization charge inducing layer 210 may help to turn off the III-N transistor 200A faster than a transistor having a gate structure only above the polarization charge inducing layer 210, or than for a transistor where the polarization charge inducing layer 210 has a width greater than 200nm.

Figure 2C illustrates a cross-sectional view of a mobility enhancement layer 140 between the channel layer 108 and the polarization charge inducing layer 210. In an embodiment, the mobility enhancement layer 140 includes a material and has a thickness that is the same as or substantially the same as the material and having a thickness of mobility enhancement layer 128 described in association with figure 1E. In other examples, the mobility enhancement layer 140 includes a material and/or has a thickness that is different from the mobility enhancement layer 128.

As a further embodiment, logic transistors such as transistors 100A and 100B can be integrated alongside a III-N RF transistor suitable for RF power amplifier and switch

applications. Figure 3 A illustrates a cross-sectional view of a III-N RF transistor 300 in a mesa region 301 adjacent to the D-mode transistor 100A and E-mode transistor 100B in a logic transistor region 101, in accordance with embodiments of the present disclosure. In an embodiment, the III-N RF transistor 300 includes a mesa structure 302. In the illustrative embodiment, the mesa structure 302 includes the channel layer 108 which is common to the D- mode transistor 100 A and the E-mode transistor 100B. The III-N RF transistor 300 further includes a polarization layer above a portion of the mesa structure 302, a gate structure 312 on the polarization layer 310, a source structure 314 and a drain structure 316 on opposite sides of the gate structure 312, and coupled to a recess in the mesa structure 302.

The III-N RF transistor 300 may have an area that is between 500-5000 times larger than the D-mode transistor 100A or E-mode transistor 100B. In an embodiment, the mesa structure 302 has length L_M between 2micron - 5microns in contrast to the fin structures 102, 104 which have a length between l00nm-300nm. In the illustrative embodiment, the mesa transistor 300 is operative as a depletion mode transistor.

Despite the massive size of the III-N RF transistor 300 the polarization charge inducing layer 310, has the same material composition and thickness as the polarization charge inducing layer 110, 112. In one or more embodiments, the polarization charge inducing layer 310 also has the same thickness as the polarization charge inducing layer 110,112.

In an embodiment, the source structure 314 and a drain structure 316 each have a same material as the source structure 118, 122 and drain structure 120, 124 respectively. In other examples, the overall height of the source structure 314 and a drain structure 316 may be 10% greater than the height of the source structure 118, 122 and drain structure 120, 124, respectively.

The source contact 318 and the drain contact 320 may have a material that is the same or substantially the same as the material of source contact 132 and drain contact 134, respectively. Figure 3B illustrates a cross-sectional view, taken along a line A-A in the Figure 3 A. As shown, the gate structure 312 is on an uppermost surface of the polarization charge inducing layer 310 of the III-N RF transistor 300. In the illustrative embodiment, the gate structure 312 has a portion on the polarization charge inducing layer 310 and portions over the isolation 106. In this example, the isolation surrounding the mesa structure 302 is not recessed as it is within logic transistor region 101. For reasons discussed above, recessing the isolation 106 around the mesa structure 302 does not necessarily improve the turn off characteristics of the III-N transistor 300. Under a biasing scheme where the gate 312 is biased negatively, the 2DEG may be

predominantly influenced by a transverse electric field (acting in the Y-direction). However, for practical purposes, as discussed further below, in some embodiments the isolation 106 around the mesa structure 302 may be recessed by an amount that is approximately similar to an amount of recess in the isolation 106 in the logic transistor region 100.

Figure 3C illustrates a plan view of the III-N RF transistor 300 and a plurality of D-mode transistors 100 A and E-mode transistors 100B, depicted in the cross-sectional illustration of Figure 3A, in accordance with embodiments of the present disclosure. In Figure 3C, the polarization charge inducing layer and the source and drain contacts are not illustrated for the sake of clarity. Furthermore, the transistors 100A and 100B are not drawn to scale with the mesa transistor 300. In an embodiment, the fin structures of each transistor 100A and 100B have a length oriented along the X-direction. The illustrative embodiment further depicts a column of D-mode transistors 100A adjacent to a column of E-mode transistors 100B surrounded by isolation 106. Each D-mode transistor lOOA may be paired with an E-mode transistor 100B, for example to implement depletion-load NMOS logic.

Figure 3D illustrates a plan view of a III-N RF transistor 300 and a plurality of D-mode and E-mode transistors lOOA and 100B, respectively, in accordance with some embodiments of the present disclosure. In Figure 3D, the polarization charge inducing layer and the source and drain contacts are not illustrated for the sake of clarity. Furthermore, the transistors 100A and 100B are not drawn to scale with the mesa transistor 300. In an embodiment, the fin structures of each transistor 100A and 100B have a length oriented along the Z-direction (orthogonal to the orientation depicted in Figure 3C). The illustrative embodiment further depicts a row of D-mode transistors 100A adjacent to a row of E-mode transistors 100B surrounded by solation 106. Each D-mode transistor 100 A may be paired with an E-mode transistor 100B, for example to implement depletion-load NMOS logic.

In a further embodiment, Figure 4 illustrates a cross-sectional view of a III-N RF transistor 300 in a mesa region 301 adjacent to the D-mode transistor 200A, and E-mode transistor 100B in a logic transistor region 401, in accordance with embodiments of the present disclosure. In an embodiment, the D-mode transistor 200Ahas a graded polarization charge inducing layer 210 inducing a 3DEG 211, and the E-mode transistor 100B has a polarization charge inducing layer 112 of fixed composition that gives rise to 2DEG, for example described in association with Figures 2A-2B. As discussed earlier, the polarization charge inducing layer 210 may have a thickness that is independent of the thickness of the polarization charge inducing layer 112 and 310.

Figure 5 illustrates method 501 for fabricating a mesa transistor 300 integrated with a D- mode transistor 100A and E-mode transistor 100B, in accordance with embodiments of the present disclosure. Method 501 begins with receiving a substrate including a silicon for e.g., and forming a stack of layers of III-N materials at operation 510. In a subsequent operation 520, an RF transistor region and logic regions are formed, where the RF transistor region and logic regions are separated by an isolation. The formation of the RF transistor region includes forming a mesa structure and the formation of the logic region includes forming a plurality of fin structures, where the mesa structure and the plurality of fin structures include a channel layer and are capped by a polarization charge inducing layer. The method 501 is continued in operation 530 with formation of trenches in portions of the mesa structure and trenches in each of the plurality of fin structures. The trenches are designed to promote epitaxial growth of a conductive material adjacent to 2DEG formed in the channel layer. In an embodiment, a III-N material is grown in the trenches during operation 540, where the III-N material is utilized to form source and drain structures in the mesa structure and in the plurality of fin structures. An RF transistor gate is formed in a subsequent operation 550. A gate for a depletion mode transistor is also formed over a first fin structure during operation 550. In a subsequent operation 560, a gate for an enhancement mode transistor is formed over a second fin structure. The method 501 concludes in operation 570 with the formation of source and drain contacts over the source and drain structures in the RF transistor and over the plurality of source and drain structures formed over the plurality of fins in the logic region.

Figures 6-16 illustrate various cross-sectional and plan views of a method to fabricate the mesa transistor 300, D-mode transistor 100A and E-mode transistor 100B depicted in Figure 3A.

Figure 6A illustrates a cross-sectional view of a stack of III-N materials formed above a substrate. In an embodiment, the stack of III-N materials includes a channel layer 602 on a buffer layer 606 formed above a substrate 130. In an embodiment, a silicon substrate 130 with a (100) top surface enables co-integration of silicon CMOS transistor technology with a III-N material. In a second embodiment, the silicon substrate 130, has a (111) top surface. In embodiments, the buffer layer 606 and the substrate 130 have mismatched lattice structures. The lattice mismatch between the buffer layer 606 and the substrate 130 may be between 15% - 50%.

In an embodiment, the buffer layer 606 is formed between the channel layer 602 and the substrate 130 to overcome lattice and thermal mismatch between the substrate 130 and the buffer layer 606. In an embodiment, the buffer layer 606 is grown on the substrate 130 by a metal organic chemical vapor deposition (MOCYD) process at a temperature in the range of 1000-1100 degrees Celsius. In an embodiment, the buffer layer 606 has a material composition that is the same or substantially the same as the buffer layer 126. In an exemplary embodiment, the buffer layer 606 includes AlGaN. The buffer layer 606 including AlGaN may be grown to a thickness between l00nm-200nm to minimize lattice mismatch between the channel layer 602 and the substrate 130.

In an embodiment, the channel layer 602 is grown on the substrate 130 by a metal organic chemical vapor deposition (MOCVD) process at a temperature in the range of 1000-1100 degrees Celsius. In an embodiment, the channel layer 602 has a material composition that is the same or substantially the same as the III-N material of the channel layer 108 descried in association with Figure 1 A. In an embodiment, the channel layer 602 is a GaN layer. In an embodiment, the GaN III-N material 602 is grown to a thickness that is approximately in the range of l00nm-5 micrometers. The channel layer 602 may have a defect density less than (lel0/cm2) when grown to a sufficient thickness, such as a thickness of at least lOOnm.

In an embodiment, exemplary embodiment, the substrate 130 includes silicon, the buffer layer 606 includes AlGaN and the channel layer 602 includes a single crystal GaN.

Figure 6B illustrates a cross-sectional view the structure of Figure 6A following the formation of a polarization charge inducing layer 608 on the stack of III-N materials formed above the substrate 130. In an embodiment, the polarization charge inducing layer 608 is grown on the channel layer 602 by a metal organic chemical vapor deposition (MOCVD) process at a temperature in the range of 1000-1100 degrees Celsius. Depending on the embodiment, the polarization charge inducing layer 608 includes a material such as but not limited to Al_zGai_-zN, Al_wIn_l-wN, or A1N, where Z ranges from 0.2-0.5 and W ranges from 0.7-0.85 and the channel layer 602 includes a material such as but not limited to InGaN or GaN. In an exemplary embodiment, the polarization charge inducing layer 608 includes an AlGaN. In an exemplary embodiment, the polarization charge inducing layer 608 is AllnN. A polarization charge inducing layer 608 having a thickness between 3nm-30nm induces 2DEG (represented by dashed lines 607) underneath an interface between the polarization charge inducing layer 608 and the channel layer 602.

Figure 6C illustrates a cross-sectional view of the structure of Figure 6B following the formation of a mesa region 614 and a logic region 616 and the formation of isolation 612, in accordance with an embodiment of the present disclosure. In an embodiment, a mask (not shown) is formed on the polarization charge inducing layer 608. The mask defines where a mesa transistor, isolation, and a plurality of the logic transistors will be made. An etch process such as, for example, a plasma etch process may be utilized to etch the polarization charge inducing layer 608 and the channel layer 602 through an exposed area in the mask. The plasma etch process patterns the polarization charge inducing layer 608 and the channel layer 602 and forms trenches, exposing the underlying buffer layer 606 in the trenches. The patterned channel layer 602 provides a mesa region 614 where a subsequent mesa transistor will be fabricated and a logic region 616 where a plurality of logic transistors will be fabricated. A first dielectric layer is then deposited on the patterned channel layer 602 filling the trenches. In a subsequent processing operation, the first dielectric layer is then planarized forming isolation 612 in the trenches. The isolation 612 separates the mesa transistor region 614 from the logic region 616. The

planarization process may utilize, for example, a chemical mechanical polish (CMP) process. In the embodiment depicted in the cross-sectional illustration of Figure 6C, the CMP process forms the isolation 612 having an uppermost surface that is co-planar or substantially co-planar with an uppermost surface of the polarization charge inducing layer 608. The plasma etch and CMP processes also defines in the logic region 616, the first fin structure 102 and the second fin structure 104 separated by the isolation 612.

Figure 6D illustrates a plan view of the structure of Figure 6C depicting the plurality of fin structures 102 in the logic region 616 adjacent the mesa region 614 and the isolation 612.

In another embodiment, the polarization layer can be independently formed after patterning of the mesa structure 302 and fin structures 102 and 104. Figure 6E illustrates the structure of Figure 6 A following the formation of a mesa region 614 and a logic region 616 and the formation of isolation 612. In an embodiment, the mesa structure 302 and fin structures 102 and 104 are formed in channel layer 602 in a manner outlined above.

Figure 6F illustrates a cross-sectional view of the structure of Figure 6E following the formation of a first polarization charge inducing layer in the mesa region and on a first fin structure of the logic region. In an embodiment, a dielectric layer 615 is deposited on the structure of Figure 6E and a mask is lithographically patterned above the dielectric layer 615. In one example, openings are formed above the mesa structure 302 and the fin structure 104 and a first polarization layer 609 is formed above the mesa structure 302 and above the fin structure 104. In an embodiment, the polarization charge inducing layer 609 includes a material and is formed in a manner similar to the material and formation of the polarization charge inducing layer 608. In an exemplary embodiment, the polarization charge inducing layer 609 includes an Al_zGai_-zN, where Z is 30 atomic percent.

Figure 6G illustrates a cross-sectional view of the structure of the structure of Figure 6F following the deposition of a sacrificial dielectric layer 617. In an embodiment, the dielectric layer 617 includes a material that is the same or substantially the same as the dielectric layer 615. In an embodiment, the dielectric layer 617 is blanket deposited on the structure of Figure 6F. Following the deposition process an opening is formed above the first fin structure 102. The polarization charge inducing layer 609 is masked during this process.

Figure 6H illustrates the structure of Figure 6G following the formation of a second polarization charge inducing layer 611 on a fin structure 104 in the logic region 616. In an embodiment, the polarization charge inducing layer 611 is formed in a manner similar to the formation of polarization charge inducing layer 609. In an embodiment, the polarization charge inducing layer 609 includes a material that is the same or substantially the same as the material of the polarization charge inducing layer 210 described in association with Figure 2A. In an exemplary embodiment, the polarization charge inducing layer 611 includes an Al_zGai_-zN, where, Z varies between 0.1 atomic percent and 30 atomic percent with increasing height away from fin structure 102. Depending on embodiments, the polarization charge inducing layer 611 may have a thickness that is comparable to or greater than a thickness of the polarization charge inducing layer 609.

Figure 7 illustrates a cross-sectional view of the structure of Figure 6C following the formation of trenches in portions of the polarization charge inducing layer 608, and in portions of the channel layer 602 adjacent to the isolation 612. In an embodiment, a mask 621 is formed on a portion of the polarization charge inducing layer 608. The process of fabricating the mask includes depositing a dielectric layer 620 on the structure of Figure 6C, forming a lithographic pattern on the dielectric layer 620 and etching through the lithographic pattern to form the mask 621. The mask 621 may include a material that can withstand high temperature processing such as a silicon oxide or a silicon nitride. In an embodiment, a plasma etch process is utilized to etch unmasked portions of the polarization charge inducing layer 608 to uncover the first layer 602.

In an embodiment, the etch is then resumed and removes portions of the uncovered first layer 602 to form trenches 6l9A and 619B in the mesa region and trenches 621 A, 621B, 623 A and 623B in the logic region. Any plasma etch process known to be suitable for etching a trench in a GaN channel layer 602 may be utilized, as embodiments are not limited in this respect. The trenches produce a recess in the channel layer 602 by an amount, ¾. It is to be appreciated that the recess ¾, in the fin structure 102, 104 may be 10% greater than the recess ¾, in the mesa structure 302 due to plasma loading effects. In an embodiment, ¾, is between 20nm and 40nm. In an embodiment, the patterned III-N material 602, has sloped sidewalls 602D and an approximately flat lowermost surfaces 602E. The sloped sidewalls 602D may be defined by a linear facet or have a profile that has a compound slope (not depicted).

Figure 8 illustrates a cross-sectional view of the structure of Figure 7 following the formation of drain structures and source structures in the trenches. In an embodiment, the source structures 624A, 626A and 628A and drain structures 624B 626B and 628B include a crystalline third III-N material that is the same or substantially the same as the third III-N material of the source structure 118 and drain structure 120, respectively. Epitaxial growth of the crystalline third III-N material may utilize a variety of techniques and processing chamber configurations.

In an embodiment, the crystalline third III-N material are grown from the exposed, undamaged surfaces of channel layer 602 in the trenches 619A, 619B, 621A, 621B, 623A and 623B using a metal organic chemical vapor deposition MOCVD process. The MOCVD process may be carried out at process temperatures between 1000 and 1100 degrees Celsius. In an embodiment, the crystalline third III-N material is epitaxially grown sufficiently thick to fill trenches 619A, 619B, 621A, 621B, 623A and 623B and extend vertically to a have a height, H_E, as measured from the bottom of the trench 619A, 619B, 621A, 621B, 623A and 623B. The cross-sectional illustration in Figure 8 represents an embodiment of the source structures 624A, 626A and 628A and drain structures 624B 626B and 628B having corrugated upper surfaces. In some examples, the corrugation is between 5nm-20nm.

Figure 9 illustrates a cross-sectional view of the structure of Figure 8 following the deposition of a dielectric layer 622 on the plurality of source structures, drain structures and on the polarization charge inducing layer. In an embodiment, the dielectric layer 622 includes a material that is the same as or substantially the same as the dielectric layer 620. In an embodiment, the dielectric layer 622 is planarized after the deposition process.

Figure 10A illustrates a cross-sectional view the structure of Figure 9 following the formation of gate opening 623 in the dielectric layer 622 over a polarization charge inducing layer portion 608B on the fin structure 102 and gate opening 625 over a polarization charge inducing layer portion 608A in the mesa region 614. In an embodiment, a photoresist mask (not shown) is patterned over the dielectric layer 622, where the pattern defines a location for an opening to be formed relative to the polarization charge inducing layer portion 608B above the fin 102. In one embodiment, a plasma etch process is utilized to form the opening 623 in the dielectric layer 622, selectively to the underlying polarization charge inducing layer portion 608B as shown in the cross-sectional illustration of Figure 10. In an embodiment, gate opening 623 has a width, at the bottom of the opening 623 that is approximately between l0nm-50nm and defines a parameter known as a transistor gate length. In an embodiment, the gate opening 623 exposes a portion of the isolation 612. Figure 10C illustrates a plan view, from a line A-A’ in Figure 10A, of the gate opening 623 formed over polarization charge inducing layer portion 608B and isolation 612 surrounding the fin structure 102 (dashed lines). In an embodiment, the plasma etch process is continued until a portion of the isolation 612 is etched below the level of the lowermost surface of the polarization charge inducing layer 608B. Figure 10D illustrates a cross-sectional view, through a line B-B’ in Figure 10A, depicting the recess HR in the isolation 612 surrounding the fin structure 102. The recess in the isolation 612 exposes sidewall portions 102A of the fin structure 102. In an embodiment, a recess between 7nm-50nm in the isolation 612 exposes the sidewall portions 102 A by an amount between 2nm - l5nm.

Referring again to Figure 10A, the mesa gate opening 625 is performed after etching the gate opening 623. In an embodiment, a sacrificial material is deposited onto the dielectric layer 622 filling the gate opening 623. A second photoresist mask is patterned on the sacrificial material over the mesa structure 302. A plasma etch process, for example may be utilized to form the gate opening 625 in the dielectric layer 622, selectively to the underlying polarization charge inducing layer portion 608A over the mesa structure 302. In an embodiment, gate opening 623 has a width, at the bottom of the opening 625 that is approximately between 250nm- 500nm and defines a parameter known as the mesa transistor gate length. In the illustrative embodiment, the isolation 216 is not exposed while forming the opening 625. Thus, the isolation is not recessed around the polarization charge inducing layer portion 608A above the mesa structure 302 as is depicted in the cross-sectional illustration of Figure 10D taken along a line C- C’ in Figure 10 A.

Figure 11 A illustrates a cross-sectional view of the structure of Figure 10A following the formation of a gate structure 626 in the opening 625 above the mesa structure 302 and the formation of a gate structure 628 over the fin structure 102. In an embodiment, a gate dielectric layer 627A is first blanket deposited in the gate opening 623, on the polarization charge inducing layer portion 608B, in the gate opening 625 on the polarization charge inducing layer portion 608A and on the dielectric layer 622. The gate dielectric layer 627A is also disposed on sidewalls of the third dielectric layer 622 in the gate opening 623 and 625. Suitable materials and thicknesses for the gate dielectric layer 627A are the same as or substantially the same as the material and thicknesses of the gate dielectric layer 114A. In an embodiment, the gate dielectric layer 627A, is formed by an atomic layer deposition (ALD) process or a PVD process. A gate electrode layer 627B is then blanket deposited on the gate dielectric layer 627A in the gate opening 623 and 625. Examples of the gate electrode layer 627B include a material that is the same as or substantially the same as the material of the gate electrode layer 114B described in association with Figure 1 A. In an embodiment, the gate electrode 627B includes a layer of a work function metal deposited in the opening 623 and 625 on the gate dielectric layer 627A and a gate cap layer deposited on the work function metal. After deposition of the gate dielectric layer 627A and the gate electrode layer 627B, a planarization process is performed to remove the gate dielectric layer 627A and the gate electrode layer 627B from an uppermost surface of the third dielectric layer 622. In an embodiment, the planarization process includes a chemical mechanical polish process, where the CMP process forms a gate structure 626 over the fin structure 102 and a gate structure 628 over the mesa structure 302. In the illustrative embodiment, the uppermost surfaces of the gate structures 626 and 628 are substantially coplanar with the uppermost surface of the third dielectric layer 622 after the planarization process. A plan view from line A-A of the gate structure 626 formed over the fin structure 102 is depicted in the cross-sectional illustration of Figure 11B.

Figure 11C illustrates a cross-sectional view, along a line B-B’, of the gate structure 626 formed around the fin structure 102, in accordance with an embodiment of the present disclosure. In an embodiment, the gate dielectric layer 627A is formed on sidewall portions 102A of the fin structure and is contact with the 2DEG. In the illustrative embodiment, the gate electrode 627B also wraps around the sidewall portions 102A.

Figure 12A illustrates a cross-sectional view the structure of Figure 11 A following the formation of a dielectric layer 630 on the dielectric layer 622 and the formation of a gate opening 631 over a polarization charge inducing layer portion 608C above the fin structure 104. In an embodiment, the gate opening 631 is formed in a manner similar to the gate opening 623 described above in Figure 10A.

Figure 12B illustrates a plan view from line A-A of the opening 631 formed over polarization charge inducing layer portion 608C and the isolation 612 surrounding the second fin structure 104.

Figure 12C illustrates a cross-sectional view, along a line B-B’, depicting a recess, HR in the isolation 612 surrounding the second fin structure in the logic region. In an embodiment, the amount of recess HR formed by the etch process is less than during the recess formed during formation of opening 623 because of an additional etch process that will be subsequently performed to remove a portion of the polarization charge inducing layer 608.

Figure 13A illustrates a cross-sectional view the structure of Figure 12A following the formation of a recess 633 of a portion of the polarization charge inducing layer 608 on the fin structure 104. In an embodiment, a plasma etch process is utilized to selectively etch the recess 633. In an embodiment, the plasma etch process is weakly energetic in order to prevent erosion of the isolation layer 612 exposed by the opening 631 and results in a recess profile that is tapered.

Figure 13B illustrates an enhanced cross-sectional view of the recess 633 in the polarization charge inducing layer 608. The process of recessing the polarization charge inducing layer 608 results in a thinned polarization charge inducing layer portion 608C and thicker portions 608D on either side of the recess. The gate length of the transistor to be formed above fin structure 104 is determine by a width of the bottom of the recess 633. As indicated in Figure 13B, the 2DEG is absent from under the thinned polarization charge inducing layer portion 608C. Figure 14 illustrates a cross-sectional view of the structure of Figure 13A following the formation of a gate structure 632 over the fin structure 104 in to form an E-mode transistor 100B. In an embodiment, the gate structure 632 is formed in a manner similar to the gate structure 626 described above in Figure 11 A. In one such embodiment, the gate structure 632 includes a gate dielectric layer 632A on the polarization charge inducing layer 608 and a gate electrode 632B on the gate dielectric layer 632A. The gate structure 632 may include materials that are the same or substantially the same as the material of the gate structure 626. In other embodiments, the gate electrode 632B and the gate dielectric layer 632A of the gate structure 632 are different from the gate dielectric layer 627B and the gate electrode 627B. A different gate electrode 632B from the gate electrodes 626B an 628B may be utilized to tune the work function of the E-mode transistor 100B.

Figure 15 illustrates a cross-sectional view of the structure of Figure 14 following the formation of openings for source and drain contacts over source structures and drain structures in the mesa region 614 and in the logic region 616. In an embodiment, a mask is patterned over the dielectric layer 630. The mask defines relative locations of the various source and drain contacts to be formed. In an embodiment, a plasma etch process is utilized to etch the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F in dielectric layer 630 and in dielectric layer 622.

Figure 16 illustrates a cross-sectional view of the structure of Figure 14 following the formation of source contact 636A, and drain contact 636B on the mesa transistor 300, formation of source contact 636C, and drain contact 636D on the D-mode transistor 100 A and the formation of source contact 636E, and drain contact 636F on the E-mode transistor 100B. In an embodiment, one or more layers of contact metal are deposited inside each of the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F illustrated in Figure 15, on exposed surfaces of the source structures 624A, 626A and 627A and drain structures 624B 626B and 627B. In the illustrative embodiment, the one or more layers of the contact metal are also blanket deposited on the uppermost surface and on sidewalls of the dielectric layer 630 and on sidewalls of the dielectric layer 622. In an embodiment, the one or more layers of contact metal are deposited using a plasma enhanced chemical vapor deposition (PECVD) or an ALD process. In an embodiment, suitable contact metals include metals such as but not limited to Ti, Al or Ni. In an embodiment, a tungsten capping layer is deposited on the one or more layers of contact metal. In an embodiment, where the tungsten capping layer is deposited on the one or more layers of contact metal, the one or more layers of contact metal is first deposited on the bottom and on the sides of the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F and the tungsten capping layer is deposited to fill the remaining portion of the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F. In an embodiment, the one or more layers of contact metal is deposited to a thickness in the range of l0-30nm, and the tungsten capping layer is deposited to fill the remaining portion of each of the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F.

A planarization process is carried out to remove the one or more layers of contact metal from the uppermost surface of the dielectric layer 630. In one embodiment, the planarization process includes a chemical mechanical polish (CMP) process. The CMP process removes all the one or more layers of contact metal from the uppermost surfaces of the dielectric layer 630. The CMP process leaves the one or more layers of contact metal in the openings 634A, 634B, 634C, 634C, 634D, 634E, 634E and 634F to form contacts 636A, 636B, 636C, 636C, 636D,

636E, 636E and 636F. In the illustrative embodiment, the dielectric layer 630 is planarized and removed.

Figure 17 illustrates a system 1700 in which a mobile computing platform 1705 and/or a data server machine 1706 employs an IC 1750 including at least one III-N transistor, such as the transistors 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B, for example. The server machine 1706 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic IC 1750. The mobile computing platform 1705 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1705 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip- level or package-level integrated system 1710, and a battery 1715.

Whether disposed within the integrated system 1710 illustrated in the expanded view 1720, or as a stand-alone packaged chip within the server machine 1706, packaged monolithic IC 1750 includes a memory chip (e.g., RAM), or a processor chip (e.g., a microprocessor, a multi core microprocessor, graphics processor, or the like) including at least one III-N transistor, such as the transistors 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B for example, as describe elsewhere herein. The monolithic IC 1750 may be further coupled to a board, a substrate, or an interposer 1760 along with, one or more of a power management integrated circuit (PMIC) 1730, RF (wireless) integrated circuit (RF1C) 1725 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof 1735.

Functionally, PMIC 1730 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1715 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RF1C 1725 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 5G, 5G, 5G, and beyond. In alternative

implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the monolithic IC 1750 or within a single IC coupled to the package substrate of the monolithic IC 1750.

Figure 18 illustrates a computing device 1800 in accordance with embodiments of the present invention. As shown, computing device 1800 houses a motherboard 1802. Motherboard 1802 may include a number of components, including but not limited to a processor 1801 and at least one communication chip 1805. Processor 1801 is physically and electrically coupled to the motherboard 1802. In some implementations, communication chip 1805 is also physically and electrically coupled to motherboard 1802. In further implementations, communication chip 1805 is part of processor 1801.

Depending on its applications, computing device 1800 may include other components that may or may not be physically and electrically coupled to motherboard 1802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth)..

Communication chip 1805 enables wireless communications for the transfer of data to and from computing device 1800. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 1805 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 1800 may include a plurality of communication chips 1804,

1805. For instance, a first communication chip 1805 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1804 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 1801 of the computing device 1800 includes an integrated circuit die packaged within processor 1801. In some embodiments, the integrated circuit die of processor 1801 includes at least one III-N transistor, such as the transistors 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B, for example integrated with or without silicon CMOS transistors. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 1805 also includes an integrated circuit die packaged within communication chip 1805. A device or component of computing device 1800 may include transistor(s) or transistor structure(s) includes at least one III-N transistor, such as the transistors 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B, for example integrated with or without silicon CMOS transistors and at least one communication chip 1805, each of which can be physically and electrically coupled to the motherboard 1802, or otherwise integrated therein.

In various examples, one or more communication chips 1804, 1805 may also be physically and/or electrically coupled to the motherboard 1802. In further implementations, communication chips 1804 may be part of processor 1801. Depending on its applications, computing device 1800 may include other components that may or may not be physically and electrically coupled to motherboard 1802. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 1807, 1808, non-volatile memory (e.g., ROM) 1810, a graphics processor 1812, flash memory, global positioning system (GPS) device 1813, compass 1814, a chipset 1806, an antenna 1816, a power amplifier 1809, a touchscreen controller 1811, a touchscreen display 1817, a speaker 1815, a camera 1803, and a battery 1818, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device 1800 and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of transistor 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 1800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top b04, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1800 may be any other electronic device that processes data.

Figure 19 illustrates an integrated circuit structure 1900 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 1900 is an intervening structure used to bridge a first substrate 1902 to a second substrate 1904. The first substrate 1902 may be, for instance, an integrated circuit die. The second substrate 1904 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The integrated circuit die may include one or more devices such as at least one pair of III-N transistors, such as the transistors 100A and 100B, and transistors 200A and 200B, having a first fin structure and a second fin structure above a substrate and separated, where the first fin structure and the second fin structure include a III-N material and a first gate above the first fin structure and a second gate above the second fin structure. The integrated circuit die may also include one or more devices such as plurality of III-N transistors, such as transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B, having a first fin structure and a second fin structure above a substrate and separated, where the first fin structure and the second fin structure include a III-N material and a first gate above the first fin structure and a second gate above the second fin structure and large mesa transistor above a mesa region having an uppermost surface area of at least one hundred times greater than an uppermost surface area of the first fin structure or the second fin structure, for example.

Generally, the purpose of an integrated circuit (IC) structure 1900 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 1900 may couple an integrated circuit die to a ball grid array (BGA) 1906 that can subsequently be coupled to the second substrate 1904. In some

embodiments, the first and second substrates 1902/1904 are attached to opposing sides of the integrated circuit (IC) structure 1900. In other embodiments, the first and second substrates 1902/1904 are attached to the same side of the integrated circuit (IC) structure 1900. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 1900.

The integrated circuit (IC) structure 1900 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 1900 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a

semiconductor substrate, such as silicon, germanium, and other group III-N, group III-V and group IV materials.

The integrated circuit (IC) structure 1900 may include metal interconnects 1908 and via 1910, including but not limited to through-silicon vias (TSVs) 1910. The integrated circuit (IC) structure 1900 may further include embedded devices 1914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, III-N transistors such as the transistors 100A and 100B, transistors 200A and 200B, transistors 300, 100A and 100B, and/or transistors 300, 200A and 100B adjacent to electrically inactive peripheral structures, one or more magnetic tunnel junction or resistive random-access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 1900. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 1900.

As used in any implementation described herein, the term“module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein. The software may be embodied as a software package, code and/or instruction set or instructions, and“hardware”, as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), and so forth.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure Thus, embodiments of the present disclosure include group III-N logic and RF devices and their methods of fabrication.

In a first example, a device includes a substrate including a first group Ill-Nitride (III-N) material, a first fin structure and a second fin structure above the substrate, the first fin structure and the second fin structure including a second III-N material. The device further includes a first polarization layer above the first fin structure, a first gate structure on the first polarization layer, and on a sidewall of the first fin structure, a second polarization layer above the second fin structure, a second gate structure above the second polarization layer and on a sidewall of the second fin structure, where a portion of the second polarization layer under the second gate structure is thinner than a portion of the first polarization layer under the first gate structure. The device further includes a first source structure and a first drain structure on opposite sides of the first gate structure and coupled to the first fin structure and a second source structure and a second drain structure on opposite sides of the second gate structure and coupled to the second fin structure.

In second examples, for any of first examples, the second III-N material includes a doped gallium nitride (GaN) and each of the first and the second polarization layers includes a third III- N material including aluminum.

In third examples, for any of the first through second examples, the first fin structure has a width between lOnm and lOOnm and the second fin structure has a width between lOnm and lOOnm.

In fourth examples, for any of the first through third examples, the first fin structure has a height between 500nm and 2 microns and the second fin structure has a height between 500nm and 2 microns.

In fifth examples, for any of the first through fourth examples, the sidewall of first fin structure has a height between 2nm and 35nm beyond a surface of an adjacent isolation material and the sidewall of the second fin structure has a height between 2nm and 35nm beyond the surface of the isolation.

In sixth examples, for any of the first through fifth examples, first gate structure is on a portion of a sidewall of the first polarization charge inducing layer and the second gate structure is on a sidewall of the second polarization charge inducing layer.

In seventh examples, for any of the first through sixth examples, the portion of the second polarization charge inducing layer under the second gate structure is lnm-2nm.

In eighth examples, for any of the first through seventh examples, each of the first polarization charge inducing layer and the second polarization charge inducing layer has a thickness between 5nm-30nm. In ninth examples, for any of the first through eighth examples, the first polarization charge inducing layer includes a third III-N material including aluminum, and wherein the aluminum content within the first polarization charge inducing layer increases with distance away from the first fin structure.

In tenth examples, for any of the first through ninth examples, the aluminum content increases from 0.1% to 50%.

In eleventh examples, for any of the first through tenth examples, the first polarization charge inducing layer has a 3 -dimensional electron gas over a thickness of the first polarization charge inducing layer.

In twelfth examples, for any of the first through eleventh examples, the first polarization charge inducing layer has a thickness between 5nm-25nm.

In thirteenth examples, for any of the first through twelfth examples, the first gate structure includes a first gate dielectric layer above the first fin structure and a first gate electrode on the first gate dielectric layer, and wherein the second gate structure includes a second gate dielectric layer above the second fin structure and a second gate electrode on the second gate dielectric layer.

In a fourteenth example, a device includes a substrate, a first fin structure and a second fin structure above the substrate and separated from each other by an isolation region, the first fin structure and the second fin structure including a group Ill-Nitride (III-N) material. The device further includes a first polarization layer above the first fin structure, a first gate structure on the first polarization layer, and on a sidewall of the first fin structure, a second polarization layer above the second fin structure, a second gate structure above the second polarization layer and on a sidewall of the second fin structure, where a portion of the second polarization layer under the second gate structure is thinner than a portion of the first polarization layer under the first gate structure. The device further includes a first source structure and a first drain structure on opposite sides of the first gate structure and coupled to the first fin structure and a second source structure and a second drain structure on opposite sides of the second gate structure and coupled to the second fin structure. The device further includes a mesa structure above the substrate, the mesa structure including the III-N material and having an uppermost surface area of at least one hundred times greater than an uppermost surface area of the first fin structure or the second fin structure. The device further includes a third polarization layer above a portion of the mesa structure, a third gate structure on the third polarization layer and a third source structure and a third drain structure on opposite sides of the third gate structure, and coupled to the mesa structure.

In fifteenth examples, for any of the fourteenth examples, the sidewall of first fin structure has a height between 2nm and 35nm beyond a surface of an adjacent isolation material and the sidewall of the second fin structure has a height between 2nm and 35nm beyond the surface of the adjacent isolation.

In sixteenth examples, for any of the fourteenth through fifteenth examples, the first polarization layer, second polarization layer and third polarization charge inducing layer include a same material and have a same thickness.

In seventeenth examples, for any of the fourteenth through sixteenth examples, the first polarization layer has a first aluminum concentration and the second polarization layer has a second aluminum concentration and the third polarization charge inducing layer has the second aluminum concentration, wherein the first aluminum concentration increases with distance away from the first fin structure.

In eighteenth examples, for any of the fourteenth through seventeenth examples, the mesa has a width that is between 50 microns and 100 microns and the first fin structure and the second fin structure each have a width that is between lOnm and lOOnm.

In nineteenth examples, for any of the fourteenth through eighteenth examples, the portion of the second polarization layer under the second gate structure is between lnm-2nm.

In twentieth example, a method of fabricating a semiconductor structure includes forming a buffer layer above a substrate. The method further includes forming a material layer stack on the buffer layer, the material layer stack including a layer of a group Ill-nitride (III-N) material and a polarization layer on the layer of the III-N material. The method further includes patterning the material layer stack, the patterning forming a mesa structure and a plurality of fin structures adjacent the mesa structure. The method further includes forming an isolation between the mesa structure, and the plurality of fin structures. The method further includes forming a source structure and a drain structure in the mesa structure and forming a source structure and a drain structure in each of the plurality of the fin structures. The method further includes forming a first gate structure on the mesa structure. The method further includes forming a second gate structure on one of the plurality of fin structures and forming a third gate structure on a second of the plurality of fin structures. The method further includes forming a source and drain contact on the source structure and drain structure of the mesa structure and forming a source contact on the source structure and a drain contact on the drain structure on each of the plurality of fin structures.

In twenty first examples, for any of the twentieth example, forming the plurality of fin structures and the mesa structure includes a single patterning operation.

In twenty second examples, for any of the twentieth through twenty first examples, the polarization layer in the one of the plurality fin structures includes a first aluminum concentration and the polarization layer in the second of the plurality fin structures includes a second aluminum concentration, wherein the second aluminum concentration increases with distance away from the layer of the III-N material.

In twenty third examples, for any of the twentieth through twenty second examples, forming the polarization layer having the second aluminum concentration includes depositing a second III-N material and increasing the second aluminum content gradually during the deposition.

In twenty fourth examples, for any of the twentieth through twenty third examples, forming the first gate structure includes recessing a portion of the isolation adjacent to the first fin structure and forming the second gate structure includes recessing a portion of the isolation adjacent to the second fin structure and etching a portion of the polarization layer adjacent to the recess prior to forming the second gate structure.

In twenty fifth examples, for any of the twentieth through twenty through twenty fourth examples, forming the source structures and the drain structures includes a single growth operation.

Claims

Claims What is claimed is:

1. A device comprising:

a substrate comprising a first group Ill-Nitride (III-N) material;

a first fin structure and a second fin structure above the substrate, the first fin structure and the second fin structure comprising a second group III-N material;

a first polarization layer above the first fin structure;

a first gate structure on the first polarization layer, and on a sidewall of the first fin structure;

a second polarization layer above the second fin structure;

a second gate structure above the second polarization layer and on a sidewall of the second fin structure, wherein a portion of the second polarization layer under the second gate structure is thinner than a portion of the first polarization layer under the first gate structure; a first source structure and a first drain structure on opposite sides of the first gate structure and coupled to the first fin structure; and

a second source structure and a second drain structure on opposite sides of the second gate structure and coupled to the second fin structure.

2. The device of claim 1, wherein the second III-N material includes a doped gallium nitride (GaN) and wherein each of the first and the second polarization layers includes a third III-N material comprising aluminum.

3. The device of any of claims 1-2, wherein the first fin structure has a width between lOnm and lOOnm and the second fin structure has a width between lOnm and lOOnm.

4. The device of any of claims 1-3, wherein the first fin structure has a height between 500nm and 2 microns and the second fin structure has a height between 500nm and 2 microns.

5. The device of any of claims 1-4, wherein the sidewall of first fin structure has a height between 2nm and 35nm beyond a surface of an adjacent isolation material and the sidewall of the second fin structure has a height between 2nm and 35nm beyond the surface of the isolation.

6. The device of any of claims 1-5, wherein the first gate structure is on a portion of a sidewall of the first polarization charge inducing layer and the second gate structure is on a sidewall of the second polarization charge inducing layer.

7. The device of claim 6, wherein the portion of the second polarization charge inducing layer under the second gate structure is lnm-2nm.

8. The device of any of claims 1-5, wherein each of the first polarization charge inducing layer and the second polarization charge inducing layer has a thickness between 5nm-30nm.

9. The device of any of claims 1-7, wherein the first polarization charge inducing layer includes a third III-N material comprising aluminum, and wherein the aluminum content within the first polarization charge inducing layer increases with distance away from the first fin structure.

10. The device of claim 9, wherein the aluminum content increases from 0.1% to 50%.

11. The device of claim 9, wherein the first polarization charge inducing layer has a 3- dimensional electron gas over a thickness of the first polarization charge inducing layer.

12. The device of claim 11, wherein the first polarization charge inducing layer has a thickness between 5nm-25nm.

13. The device of any of claims 1-7, wherein the first gate structure comprises a first gate dielectric layer above the first fin structure and a first gate electrode on the first gate dielectric layer, and wherein the second gate structure comprises a second gate dielectric layer above the second fin structure and a second gate electrode on the second gate dielectric layer.

14. A device including:

a substrate,

a first fin structure and a second fin structure above the substrate and separated from each other by an isolation region, the first fin structure and the second fin structure including a group Ill-Nitride (III-N) material;

a first polarization layer above the first fin structure;

a second polarization layer on the second fin structure; a second gate structure on the second polarization layer and of a sidewall of the second fin structure, wherein a portion of the second polarization layer under the second gate structure is thinner than a portion of the first polarization layer under the first gate structure; and

a first source structure and a first drain structure on opposite sides of the first gate structure and coupled to the first fin structure, and a second source structure and a second drain structure on opposite sides of the second gate structure and coupled to the second fin structure; a mesa structure above the substrate, the mesa structure including the III-N material and having an uppermost surface area of at least one hundred times greater than an uppermost surface area of the first fin structure or the second fin structure;

a third polarization layer above a portion of the mesa structure;

a third gate structure on the third polarization layer; and

a third source structure and a third drain structure on opposite sides of the third gate structure, and coupled to the mesa structure.

15. The device of claim 14, wherein the sidewall of first fin structure has a height between 2nm and 35nm beyond a surface of an adjacent isolation material and the sidewall of the second fin structure has a height between 2nm and 35nm beyond the surface of the adjacent isolation.

16. The device of any of claims 14-15, wherein the first polarization layer, second polarization layer and third polarization charge inducing layer comprise a same material and have a same thickness.

17. The device of any of claims 14-16, wherein the first polarization layer has a first aluminum concentration and the second polarization layer has a second aluminum concentration and the third polarization charge inducing layer has the second aluminum concentration, wherein the first aluminum concentration increases with distance away from the first fin structure.

18. The device of any of claims 14-17, wherein the mesa has a width that is between 50 microns and 100 microns and the first fin structure and the second fin structure each have a width that is between lOnm and lOOnm.

19. The device of claim 14, wherein the portion of the second polarization layer under the second gate structure is between lnm-2nm.

20. A method of fabricating a semiconductor structure, the method comprising: forming a buffer layer above a substrate;

forming a material layer stack on the buffer layer, the material layer stack comprising a layer of a group Ill-nitride (III-N) material and a polarization layer on the layer of the III-N material;

patterning the material layer stack, the patterning forming a mesa structure and a plurality of fin structures adjacent the mesa structure;

forming an isolation between the mesa structure, and the plurality of fin structures; forming a source structure and a drain structure in the mesa structure and forming a source structure and a drain structure in each of the plurality of the fin structures; forming a first gate structure on the mesa structure;

forming a second gate structure on one of the plurality of fin structures and forming a third gate structure on a second of the plurality of fin structures,

forming a source and drain contact on the source structure and drain structure of the mesa structure; and

forming a source contact on the source structure and a drain contact on the drain structure on each of the plurality of fin structures.

21. The method of claim 20, wherein forming the plurality of fin structures and the mesa structure comprises a single patterning operation.

22. The method of any of claims 20-21, wherein the polarization layer in the one of the plurality fin structures comprises a first aluminum concentration and the polarization layer in the second of the plurality fin structures comprises a second aluminum concentration, wherein the second aluminum concentration increases with distance away from the layer of the III-N material.

23. The method of any of claims 20-22, wherein forming the polarization layer having the second aluminum concentration comprises depositing a second III-N material and increasing the second aluminum content gradually during the deposition.

24. The method of any of claims 20-23, wherein forming the first gate structure comprises recessing a portion of the isolation adjacent to the first fin structure and forming the second gate structure comprises recessing a portion of the isolation adjacent to the second fin structure and etching a portion of the polarization layer adjacent to the recess prior to forming the second gate structure.

25. The method of any of claims 20-24, wherein forming the source structures and the drain structures comprises a single growth operation.