WO2019139610A1

WO2019139610A1 - Shield structure for a group iii-nitride device and method of fabrication

Info

Publication number: WO2019139610A1
Application number: PCT/US2018/013482
Authority: WO
Inventors: Han Wui Then; Paul Fischer; Marko Radosavljevic; Sansaptak DASGUPTA
Original assignee: Intel Corporation
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2019-07-18

Abstract

A device structure, including a shield feature in a trench embedded within the one or more layers of III-N material is described. The shield feature includes a material having a higher electrical conductivity than the III-N material. A III-N device, such as III-N transistor may be above the shield feature and the one or more layers of III-N materials. The shield feature may be biased during operation of the III-N device to reduce electrical leakage between the III-N device and an underlying substrate material.

Description

SHIELD STRUCTURE FOR A GROUP III-NITRIDE DEVICE AND METHOD OF FABRICATION

BACKGROUND

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. For example, in radio frequency (RF) communication, the RF front-end is a generic term for the circuitry between an antenna and a digital baseband system. Such RF front-end components may include one or more group III-Nitride (III-N) transistors. In another example, power management applications may employ one or more high voltage devices. Such high voltage devices may include one or more group III-Nitride (III-N) transistors. A buried shield structure may likewise be employed to minimize leakage current from transistor to substrate. A buried shield structure may be employed to minimize leakage current from transistor to substrate. Embedding a shield structure under a III-N material can be advantageous not only for substrate leakage reduction, but also for potentially reducing defects arising from stress between different layers across a wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified“ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 A illustrates a cross-sectional view of a shield structure under a group III-N transistor.

Figure IB illustrates a plan view of a shield structure.

Figure 1C illustrates a plan view of an overlap between a transistor and a shield structure, in accordance with an embodiment of the present disclosure.

Figure 2A illustrates a cross-sectional view of a trench formed within a substrate.

Figure 2B illustrates a cross-sectional view of the structure of Figure 2A following the formation of a first III-N material in the trench and on an isolation, in accordance with an embodiment of the present disclosure.

Figure 2C illustrates a cross-sectional view of the structure of Figure 2B following the formation of a conductive layer on the first III-N material and the formation of a resist pattern on the conductive layer.

Figure 2D illustrates a cross-sectional view of the structure of Figure 2C, following the formation of shield features.

Figure 2E illustrates a cross-sectional view of the structure of Figure 2D, following formation of a buffer layer on the first III-N material and on the shield feature.

Figure 2F illustrates a cross-sectional view of the structure of Figure 2E, following formation of a channel layer on the buffer layer and a polarization charge inducing layer on the channel layer.

Figure 2G illustrates a cross-sectional view of a portion of the structure of Figure 2F, following formation of trenches.

Figure 2H illustrates a cross-sectional view of the structure of Figure 2G, following the formation of isolation adjacent to the polarization charge inducing layer.

Figure 21 illustrates a cross-sectional view of the structure of Figure 2H, following the formation of trenches in portions of the polarization charge inducing layer, and in portions of the third III-N material adjacent to isolation structures.

Figure 21 illustrates a cross-sectional view of the structure of Figure 21, following formation of a source structure and a drain structure in the trenches.

Figure 2K illustrates a cross-sectional view of the structure of Figure 2J, following the deposition of a dielectric layer on the source structure, drain structure, and on the polarization charge inducing layer.

Figure 2L illustrates a cross-sectional view of the structure of Figure 2K, following formation of a gate opening in the dielectric layer over a portion of the polarization charge inducing layer.

Figure 2M illustrates a cross-sectional view of the structure of Figure 2L, following formation of a gate structure in the gate opening and on a portion of the polarization charge inducing layer.

Figure 2N illustrates a cross-sectional view of the structure of Figure 2M, following the formation of a source contact and a drain contact.

Figure 20 illustrates a cross-sectional view of the structure of Figure 2N, following the formation of a lithographic pattern.

Figure 2P illustrates a plan view of the structure of Figure 20, following the formation of a shield structure contact opening. Figure 2Q illustrates a cross-sectional view of the structure of Figure 2P, following deposition of a shield structure contact material in the contact openings.

Figure 2R illustrates a plan-view of the structure of Figure 2Q, following the

planarization of the shield structure contact material to form shield structure contacts.

Figure 3 is a functional block diagram of a III-N SoC implementation of a mobile computing platform, in accordance with an embodiment of the present disclosure.

Figure 4 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 5 illustrates an integrated circuit (IC) structure that includes one or more device structures including a substrate shield under a transistor, all arranged in accordance with at least some embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Devices including a shield structure for a III-N device and methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as operations associated with a shield structure for a III-N device, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”, and“below” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present disclosure may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to“an embodiment” or“one embodiment” or“some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase“in an embodiment” or“in one embodiment” or“some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms“a”,“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term“and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms“coupled” and“connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of’ or“one or more of’ can mean any combination of the listed terms. For example, the phrase“at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. The ability to co-integrate logic devices fashioned from III-N materials alongside RF power amplifiers (PA), for example will provide enhanced capability as well as help realize significant cost savings from integrating logic and PA.

However, reducing substrate leakage continues to be a challenge for III-N devices, particularly where there remains some continuous semi conductive material between the III-N device and substrate, which is typical if III-N material of a III-N device has been (hetero)epitaxially grown from the substrate. With such material continuity, charges from a III-N device can leak into the substrate. For example, in a III-N transistor, charges from a drain and/or a gate may make their way into the substrate, which is usually maintained at ground (or some other reference) potential that may be many tens or hundreds of volts different than the gate and/or drain. Substrate leakage can result in power loss. In one example, leakage current between a III-N transistor operating at 200V and a substrate maintained at ground potential (e.g., 0V) can be in the order of 0.01-0.02A, resulting in 2W- 4W of power loss. To provide context, 4W represents an average amount of power consumed by mobile devices during operation. Even a fractional reduction in leakage current can lead to a sizable power saving when summed over a large collection of III-N devices. While fabricating III-N transistors over thick buffer layers (order of several microns) can help reduce charge leakage into an underlying substrate, thick buffer layers are expensive to fabricate and may also give rise to larger stress. For example, where a substrate is silicon, the stress from deposition of thick buffer layers can lead to formation of cracks during subsequent processing.

In accordance with some embodiments, leakage current between a III-N device and an underlying substrate is reduced by incorporating an electrical shield structure between the III-N device and some portion of the substrate. The shield structure may be positioned between a substrate material and the III-N device anywhere an isolation dielectric is absent. Such a shield structure may be embedded within III-N material that is heteroepitaxial to an underlying substrate layer. The shield structure can be advantageously biased at a desired potential to deter charge leakage through any crystalline material pathway physically coupling the III-N device to the substrate. A biased electrical shield structure may reduce substrate leakage through such a pathway by reducing the magnitude of electric field that may develop between one or more terminal of the III-N device and the substrate during operation A biased electrical shield structure may present a potential barrier between the substrate and charges traversing the III-N device.

Furthermore, incorporating a buried substrate shield in a trench of a substrate may also advantageously confine a thicker buffer layer in a trench within a substrate. Such a scheme may reduce stress between the III-N materials and an underlying substrate material over a wafer surface and/or reduce defect density within the III-N materials.

In some embodiments described further below, a device structure includes a trench within a substrate. One or more layers of a III-N material may be in the substrate trench, and a substrate shield feature may be embedded within the one or more layers of III-N material. The substrate shield feature may include a material having a higher electrical conductivity than each of the one or more III-N materials. A transistor may be directly above the shield feature and the one or more layers of III-N materials. With such an architecture, the shield feature, when biased, may screen the substrate from the transistor.

Figure 1 A illustrates a cross-sectional view of a device structure including a shield feature 106 within a trench 101 and a transistor 150 over the shield feature 106, in accordance with an embodiment of the present disclosure. In this exemplary embodiment, the trench 101 is within a substrate layer 102. The substrate layer 102 advantageously includes a group IV material, such as silicon, SiC or sapphire. A silicon substrate may have a (100) top surface 105. In another embodiment, a silicon substrate has a (111) top surface 105. The device structure 100 further includes one or more layers of group Ill-nitride (III-N) materials within the trench 101. In the illustrative embodiment, the device structure 100 includes a III-N material 104 and a shield feature 106 on the III-N material 104, within the trench 101. In the illustrative embodiment, a buffer layer 110 including one or more additional III-N materials is on the III-N material 104 and on the shield feature 106. The transistor 150 is over the buffer layer 110. The transistor 150 includes a channel layer 112 that is on the buffer layer 110 and over the shield feature 106.

In one embodiment, the shield feature 106 is one of a plurality of lines spaced apart within the trench 101, as illustrated in Figure 1A. In some embodiments, each of the plurality of lines has a width, Ws (along X-direction) that is less than 250nm, a thickness (along Y-direction) that is less than 200nm. A spacing, Ss, between adjacent one of the lines is between lOOnm- 250nm. The shield feature 106 includes a material of sufficient conductivity to permit voltage biasing of the shield. The shield feature 106 should have a higher electrical conductivity than the III-N material 104. For example, the shield feature may have an electrical conductivity that is at least 2000 times greater than the electrical conductivity of the PI-N material 104. In some embodiments, the shield feature 106 includes at least one of a compound including titanium, a compound including tantalum, a compound including aluminum. The shield feature 106 may also include group IV material. In one example, the shield feature 106 includes titanium nitride. In another example, the shield feature 106 includes doped poly silicon.

In one embodiment, a shield structure 107 includes a collection or arrangement of shield features 106. The shield structure 107 has a length, Lss, as illustrated in Figure 1A. In some embodiments, the shield structure 107 is designed so that Lss is at least equal to a length of a channel, Lc, of the transistor 150. In other examples, the length of the shield structure 107 is greater than the length of the channel Lc.

Referring still to Figure 1 A, in one exemplary embodiment, the III-N material 104 has an interior portion 104A over a bottom of trench 101, a sidewall portion 104B over a sidewall of trench 101, and a peripheral portion 104C that extends beyond the trench 101. Peripheral portion 104C is over an isolation layer 108, which is adjacent to the trench 101. In one example, the peripheral portion 104C may extend continuously to a second trench adjacent to trench 101 (not shown). In another example, the peripheral portion 104C may extend over only a portion of the isolation layer 108. In some exemplary embodiments, the III-N peripheral portion 104C has a thickness between 50nm-250nm. The III-N sidewall portion 104B is between l0nm-20nm and the III-N lateral portion 104C has a thickness between l0nm-20nm. The III-N material 104 is advantageously monocrystalline. In some exemplary embodiments, the III-N material 104 includes aluminum, such as a binary alloy of AIN. In other embodiments, the III-N material 104 is a ternary or quaternary III-N alloy, some of which may include aluminum.

In the illustrative embodiment, buffer layer 110 is between the shield structure 107, and has a peripheral buffer layer portion 110A above the III-N peripheral portion 104C. In one example, the peripheral buffer layer portion l lOA may continuously extend to a second trench adjacent to trench 101 (not shown). While buffer layer 110 may include any IP-N binary, ternary and/or quaternary alloys, in some embodiments, the buffer layer 110 includes Al_zGai__zN or Al_wIni__wN. Z may range from 0.25-0.75 while W ranges from 0.7-0.85, for example. In some embodiments, the buffer layer 110 includes a compositionally graded III-N alloy. For example, aluminum content within a Al_zGai_-zN alloy may be graded. In one example, the aluminum content in Al_zGai__zN decreases with distance vertically away (Y direction) from the III-N interior portion 104A. For example, the aluminum content may be graded from 75% to 25%. In one such embodiment, the lowermost portion of Al_zGai__zN where Z is approximately 0.75, a middle portion where Z is approximately 0.50, and a top portion where Z is approximately 0 25.

In some embodiments, the buffer layer 110 has a thickness between 500nm - lOOOnm. In one exemplary embodiment, an Al_zGai__zN buffer layer 110 has a thickness of approximately 750nm In one such embodiment, the Al_zGai__zN has three portions over the buffer layer thickness where the lowermost portion has an A1 content of 75 atomic percent, an intermediate portion where the A1 content is 50 atomic percent, and a top portion where the Al content is 25 atomic percent. In some embodiments, the peripheral buffer layer portion l lOA has a thickness between 500nm-l00nm. In some such embodiments, the peripheral buffer layer portion 110A has an Al content of approximately 25 atomic percent.

In the illustrative embodiment, the isolation layer 108 advantageously provides electrical isolation between the channel layer 112 and the substrate 102. Isolation layer 108 may include any material that has sufficient dielectric strength to provide adequate electrical isolation.

Isolation layer 108, may for example, be one or more dielectric materials known to be suitable for shallow trench isolation (STI) applications. Exemplary dielectric materials include silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

Depending on embodiments, isolation layer 108 has a thickness between lOnm and 50nm.

At least a portion of the channel layer 112 forms an active channel for transistor 150. Channel layer 112 may be any III-N material (e.g., a binary, ternary or quaternary III-N alloy). In some embodiments, channel layer 112 includes binary gallium nitride (GaN). In one such embodiment, channel layer 112 has a relatively high carrier mobility, (greater than 500 cm² V ¹). In other embodiments, channel layer 112 includes one or more ternary III-N alloys such as AlGaN, AlInN. In other embodiments, channel layer 112 includes one or more quaternary alloys of GaN, such as InxAlyGai-x-_YN, where X ranges from 0.01-0.1 and Y ranges from 0.01-0.1. The channel layer 112 may be a substantially un-doped III-N material (i.e., 0₂ impurity concentration minimized) for minimal impurity scattering. In some embodiments, channel layer 112 has a thickness approximately between 20nm to 5um.

In some embodiments, the transistor 150 includes a polarization charge inducing layer 120 above the channel layer 112, and a gate stack 114 above the polarization charge inducing layer 120. The transistor further includes a source structure 116, a drain structure 118 on recessed portions of the channel layer 112. The source structure 116 and drain structure 118 are on opposite sides of the gate electrode 114. The transistor 150 further includes a source contact 122 coupled with the source structure 116 and a drain contact 124 coupled with the drain contact 118.

In some embodiments, the polarization charge inducing layer 120 may include any binary, ternary, or quaternary III-N alloy that has a spontaneous polarization and/or piezoelectric polarization suitable for the chosen channel material. In some embodiments, the polarization charge inducing layer 120 has a thickness sufficient to introduce a polarization difference in the interface between the channel layer 112 and the polarization charge inducing layer 120, creating a 2DEG 121 below an interface between the polarization charge inducing layer 120 and the channel layer 112. In some embodiments, the polarization charge inducing layer 120 includes a material such as, but not limited to, Al_zGai__zN, Al_wIni_-wN, or AIN, where Z ranges from 0.2-0.3 and W ranges from 0.7-0.85. One combination includes a AlGaN polarization charge inducing layer 120 and a binary GaN channel layer 112. In one such combination, an AlGaN polarization charge inducing layer 120 has a bandgap (e.g., 3.7 eV) that is wider than the bandgap of a GaN III-N material 102 (e.g., 3.4 eV), facilitating a quantum well at the interface between the AlGaN polarization charge inducing layer 120 and the GaN III-N material 112. The thickness of the polarization charge inducing layer 120 may vary with material composition, for instance a layer of Al_zGai_-zN can have a thickness between 3nm-20nm depending on the A1 concentration.

The gate stack 114 includes a gate dielectric layer 114A and a gate electrode 114B. The gate dielectric layer 114A may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric embodiments, the gate dielectric layer 114A is a metal oxide (e.g., including oxygen and one or more metals, such as, but not limited to, aluminum, hafnium, zirconium, tantalum or titanium). In another embodiment, the gate dielectric layer 114A includes a silicon dioxide or a silicon nitride. In some examples, the gate dielectric layer 114A has a thickness between 2nm and 10 nm.

In some embodiments, the gate electrode 114B includes a metal such as but not limited to Pt, Ni and an alloy such as TiN or TaN. In one such embodiment, the gate electrode 114B has a length, LQ (not depicted), that is approximately in the range of l0-30nm. In some embodiments, the gate electrode 114B includes a work function metal and a gate cap. The work function metal may include a metal such as Pt, Ni, and an alloy such as TiN or TaN and the gate cap may include a metal such as W.

In some embodiments, the source structure 116, and drain structure 118 include a III-N material. This III-N source and drain material may be advantageously single crystalline, or maybe polycrystalline. In some such embodiments, the single crystalline III-N material is lattice matched to the channel layer 112. In one exemplary embodiment where the channel layer 108 includes a material such as GaN, the source structure 116, and drain structure 118 include a single crystal of InGaN. In the illustrative embodiment, the source structure 116, and drain structure 118, are crystals having faceted sidewalls, with the facets being approximately 60 degrees with respect to plane of the substrate 102. In an exemplary embodiment, the source structure 116 includes an impurity dopant such as an n-type dopant (donor impurity). Examples of an n-type dopant includes an impurity such as Si or Ge. In one embodiment, the n-type impurity is silicon. As a further example, the silicon n-type dopant may have a n-dopant density of at least lel9/cm³. Band alignment between the source structure 116, drain structure 118 and the channel layer 112 enables conduction between the drain structure 118, the channel layer 112 and the source structure 116. With improved band alignment, electrons from the source structure can flow into the 2DEG region with virtually no access resistance.

Source contact 122 and drain contact 124 may be of any material(s) known to be suitable for the purpose. In some embodiments, the source contact 122, and the drain contact 124 each include a multi-layer stack. In some embodiments, the multi-layer stack includes two or more distinct layers of metal, such as, but not limited to, a layer of Ti, Ru or A1 and a conductive cap on the layer of Ti, Ru or Al. The conductive cap may include a material such as W or Cu.

Figure IB illustrates a plan view of the shield structure 107, with the A-A’ of the cross- sectional illustration of Figure 1A further shown in dashed line. In the illustrative embodiment, the shield structure 107 includes a plurality of non-intersecting lines. In other examples, shield structure 107 may include a mesh structure including a plurality of intersecting lines. An outline 151 of the transistor 150 is also depicted to illustrate an exemplary relationship between the size of the transistor and the shield structure 107. The transistor 150 has a length L_T (including combined lengths of the source structure 116, the drain structure 118 and the region under the polarization charge inducing layer 120) and a width W₇. The shield structure has a length Lss and a width Wss, as is depicted in the plan view illustration of Figure IB. In some embodiments, the transistor 150, has a length that is less than the length of shield structure 107, and a width that is less than the width of shield structure 107. In one such embodiment, the transistor 150 is contained within a footprint the shield structure 107, which may advantageously minimize charge leakage when the shield structure is voltage biased. In another embodiment, as is depicted in Figure 1C, transistor 150 (indicated by outline 151) is offset from shield structure 107 (indicated by outline 108). In one such example, a portion of the drain structure 118 or the source structure 116 may extend over the isolation layer 108. Such an offset may not significantly impact the electrical capability of the shield structure 107.

Figures 2A-2R illustrate cross-sectional and plan views of a method to fabricate a shield structure integrated with a transistor, in accordance with embodiments of the present disclosure.

Figure 2A illustrates a cross-sectional view of the trench 101 formed within the substrate 102. In some embodiments, isolation layer 108 is blanket deposited on the substrate 102. In some embodiments, the isolation layer 108 has a thickness of at least lOnm. A thickness of lOnm may be sufficient to prevent leakage current from a transistor (to be fabricated in subsequent downstream processing operations) from penetrating into the underlying substrate 102. In some embodiments, a mask (not shown) is formed on the isolation layer 108. In one embodiment, a plasma etch process is utilized to etch an opening in the isolation layer 108 and in the substrate 102 through an exposed area in the mask to form trench 101. Trench 101 is formed sufficiently deep to enable formation of a shield structure within the trench 101, as well as to grow a sufficiently thick buffer layer. In one embodiment, trench 101 has a depth between lOOOnm- 1500nm. In some embodiments, a silicon substrate 102 with a (100) surface 200 enables co integration of silicon CMOS transistor technology with a III-N material. In a second

embodiment, the surface 200 has a 111-single crystal orientation.

Figure 2B illustrates a cross-sectional view of the structure of Figure 2A following the formation of the III-N material 104 in trench 101 and on the isolation layer 108. In some embodiments, the III-N material 104 is heteroepitaxially formed by a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process. In one such embodiment, the MOCVD process has a process temperature that is approximately in the range of 300-1100 degrees Celsius. In an exemplary embodiment, the III-N material 104 includes A1N. Depending on the depth of trench 101, a layer of AIN may be grown to a thickness between 50nm-500nm. As grown, the III-N material 104 has thicker interior portion 104A and thinner sidewall portion 104B and thinner peripheral portion 104C. In an exemplary embodiment, an A1N layer is grown to a thickness between 200nm-250nm. In embodiments, the III-N material 104 and the substrate 102 have mismatched lattice structures. The mismatch in the lattice structures may be between 15% - 50%.

Figure 2C illustrates a cross-sectional view of the structure of Figure 2B following the formation of a conductive layer 201 on the first III-N material 104 and the formation of a mask 202 on the conductive layer 201.

In some embodiments, the conductive layer 201 includes a material that is the same as the material of the shield feature 106. In one exemplary embodiment, the conductive layer includes an alloy, such as TiN, chosen for its ease in the fabrication process as well for electrical conductivity. In some embodiments, a layer of TiN is blanket deposited using a physical vapor deposition process. In some embodiments where a physical vapor deposition (PVD) process is employed a thicker layer of conductive layer 201 is deposited on the peripheral portion 104A than on sidewall portion 104B. Such a non-conformal process may be advantageous because conductive layer 201 is to be subsequently selectively removed from the sidewall portion 104B. In some exemplary embodiments, a layer of TiN is deposited by a PVD process to a thickness in the range of 150nm-200nm on the III-N surface portion 104A and to a thickness in the range of 100-120nm on the III-N sidewall portion 104B

In another exemplary embodiment, the conductive layer 201 includes a layer of polysilicon that is subsequently doped to provide electrical conductivity. For example, the polysilicon may be deposited, for example by chemical vapor deposition (CVD) and may be doped with phosphorus or arsenic to a concentration between lel8-lel9/cm³. Polysilicon may also be advantageous for ease of subsequent patterning, including removal of sidewall portions.

A mask layer (e g., photoresist) is then deposited on the conductive layer 201 and patterned (e.g., lithographically) to define a mask 202 to form one or more shield features.

Figure 2D illustrates a cross-sectional view of the structure of Figure 2C, following the formation of shield features 106. In some embodiments, a plasma etch process is utilized to pattern the conductive layer 201 to form shield feature 106. In some embodiments, the conductive layer is over etched by approximately 200% to remove the conductive layer off the sidewall portion 104B. In some embodiments, a spacer portion of a conductive layer 201 may be formed against IP-N sidewall portion 104B (not shown). In one such embodiment, the spacer portion has a height that is approximately equal to a thickness of the shield feature 106. Such a spacer portion need not impact a field created by the shield features 106 when the shield feature 106 is voltage biased. Figure 2E illustrates a cross-sectional view of the structure of Figure 2D, following the formation of a buffer layer 110 on the first III-N material 104 and on the shield feature 106. In some embodiments, the buffer layer 110 includes a III-N material such as but not limited to Al_zGai__zN or Al_wIni._wN, where Z ranges from 0.2-0.3 and W ranges from 0.7-0.85. In some embodiments, the buffer layer 110 is grown on the first III-N material 104 by a metal organic chemical vapor deposition (MOCVD) process at a temperature in the range of 1000-1100 degrees Celsius. In an exemplary embodiment, the buffer layer 110 includes AlGaN. In some embodiments, the buffer layer 110 minimizes crystal defects in a channel layer (to be formed in a subsequent process operation) that can arise from lattice mismatch between the channel layer and the underlying first III-N material 104.

In some embodiments, the MOCVD growth process fills a gap 205 between each of the plurality of shield features 106 with the buffer layer 110. Furthermore, buffer layer 110 is also formed over an uppermost surface 203 of each of the shield features 106 by lateral epitaxial overgrowth. In some embodiments, the MOCVD growth process grows buffer layer 110 to completely fill trench 101 and form a lateral buffer layer portion 110A as illustrated in Figure 2F. In some embodiments, the buffer layer 104 may be grown to a thickness, F), between 500nm- lOOOnm.

In some embodiments, the buffer layer 110 is formed by decreasing an amount of aluminum added into the buffer layer 110 during the deposition process. In one embodiment, a lowermost portion of the buffer layer 110 adjacent to shield structure 107 includes a layer of AlGaN having an aluminum content that is approximately 75 atomic percent and an uppermost portion above the lateral III-N portion 104C having an aluminum content that is approximately 25 atomic percent. An AlGaN buffer layer 110 with an aluminum content of approximately 25 atomic percent enables lattice matching to a channel layer to be formed above.

The buffer layer may be planarized after the deposition process. In some embodiments, the planarization process includes a chemical mechanical polish (CMP) process. Depending on embodiments, the buffer layer may be planarized until the peripheral buffer layer portion 110A has a thickness, T₂, in the range of l0nm-50nm, above the isolation layer 108. A peripheral buffer layer portion 110A having a thickness of only 10nm-50nm, for example, may help reduce stress on the substrate 102.

Figure 2F illustrates a cross-sectional view of the structure of Figure 2E, following the formation of channel layer 112 on buffer layer 110 and the formation of polarization charge inducing layer 120 on channel layer 112.

In some embodiments, the channel layer 112 is grown on the buffer layer 110 by a MOCVD process at a temperature in the range of 1000-1100 degrees Celsius. In some embodiments, the channel layer 112 includes GaN. In some embodiments, the GaN III-N material is grown to a thickness that is approximately in the range of 20nm-5 micrometers. The channel layer 112 may have a defect density less than (lelO/cm²) when grown to a sufficient thickness, such as a thickness of at least lOOnm.

In some embodiments, the polarization charge inducing layer 120 is grown on the channel layer 112 by a MOCVD process at a temperature in the range of 1000-1100 degrees Celsius. Depending on the embodiment, the polarization charge inducing layer 120 includes a material such as but not limited to A1N, AllnN or Al_yGai_-yN (where y is 0.24-0.36). In an exemplary embodiment, the polarization charge inducing layer 120 is AllnN. In an exemplary embodiment where the substrate 102 includes silicon, the III-N material 104 includes A1N, the buffer layer 110 includes AlGaN, and the channel layer 112 includes a single crystal GaN, the polarization charge inducing layer 120 is AllnN.

Figure 2G illustrates a cross-sectional view of a portion 160 of the structure of Figure 2F, following formation of trenches in the polarization charge inducing layer 120, and in the channel layer 112. In some embodiments, a mask (not shown) is formed on the polarization charge inducing layer 120. In one embodiment, a plasma etch process is utilized to etch the polarization charge inducing layer 120 and the channel layer 112 through an exposed area in the mask to form openings 207. The openings 207 are formed sufficiently deep to subsequently define isolation regions. In one embodiment, the openings 207 have a depth between 75nm and 200nm.

Figure 2H illustrates a cross-sectional view of the structure of Figure 2G, following the formation of isolation 126 adjacent to the polarization charge inducing layer 120. In some embodiments, an isolation layer 126 is blanket deposited on the surface of the polarization charge inducing layer 204 and on the patterned group III-N semiconductor material 202.

Examples of the isolation layer 126 may include any material that has a sufficient dielectric strength to provide electrical isolation such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide. The isolation layer 126 is subsequently planarized, for example using a chemical mechanical polish process.

Figure 21 illustrates a cross-sectional view of the structure of Figure 2H, following the formation of trenches 215 A, 215B in portions of the polarization charge inducing layer 120, and in portions of the channel layer 112 adjacent to isolation structures 126. In some embodiments, a mask 214 is formed on a portion of the polarization charge inducing layer 120. The mask 214 may include a material that can withstand high temperature processing such as a silicon oxide or a silicon nitride. In some embodiments, a plasma etch process is utilized to etch unmasked portions of the polarization charge inducing layer 120 to uncover the channel layer 112. In some embodiments, the etch is then resumed and removes portions of the uncovered channel layer 112 to form trenches 215 A and 215B. The trenches 215 A and 215B are each recessed by an amount, HR. In some embodiments, HR, is between 30nm and lOOnm. Trenches 215A and 215B may have a height and width chosen to enable subsequent epitaxial formation of source and drain structures having a contact resistance of less than 200 ohms-micron.

Figure 2J illustrates a cross-sectional view of the structure of Figure 21, following the formation of source structure 116 and drain structure 118 in the trenches 215A and 215B, respectively. In some embodiments, the source structure 116 and the drain structure 118 are grown from the exposed, undamaged surface of the channel layer 112 in the trenches 215A and 215B using a metal organic chemical vapor deposition MOCVD process. The MOCVD process may be carried out at process temperatures between 1000 and 1100 degrees Celsius and in-situ doped with an n-type dopant such as Si during the deposition process. In some embodiments, the source structure 116 and the drain structure 118, are epitaxially grown sufficiently thick to fill trenches 215 A and 215B respectively and extend vertically to have a height, H_E, as measured from the bottom of the trench 215A and 215B. The cross-sectional illustration in Figure 2F represents an embodiment of the source structure 116 and the drain structure 118 having corrugated upper surfaces 116A and 118A, respectively. In some examples, the corrugation is between 5nm-20nm. In some embodiments, when the mask 214 does not cover a portion of the isolation 126 as illustrated in Figure 3A, the source structure 116 or the drain structure 118 may extend over uncovered portions of the isolation 126 by a process of lateral epitaxial overgrowth (LEO).

Figure 2K illustrates a cross-sectional view of the structure of Figure 21, following the deposition of a dielectric layer 128 on the source structure 116, drain structure 118, on the polarization charge inducing layer 120 and on the isolation 126. In some examples, the dielectric layer 128 is blanket deposited and then planarized for subsequent processing.

Figure 2L illustrates a cross-sectional view of the structure of Figure 2K, following formation of a gate opening 221 in the dielectric layer 128 over a portion of the polarization charge inducing layer 120. In some embodiments, a photoresist mask (not shown) is patterned over the dielectric layer 128, where the pattern defines a location for an opening to be formed relative to the polarization charge inducing layer 120. In one embodiment, a plasma etch process is utilized to form the opening 221 in the dielectric layer 128, selectively to the underlying polarization charge inducing layer 120. In some embodiments, gate opening 221 has a width, at the bottom of the opening, WB, that is approximately between 20nm- 500nm as shown in the cross-sectional illustration of Figure 2L.

Figure 2M illustrates a cross-sectional view of the structure of Figure 2L, following formation of a gate structure in the opening 221 and on a portion of the polarization charge inducing layer 120. In some embodiments, a gate dielectric layer 114A is first blanket deposited on a portion of the polarization charge inducing layer 120 exposed by the gate opening 221, and on the dielectric layer 128. The gate dielectric layer 114A is also disposed on sidewalls of the dielectric layer 128 in the gate opening 221. Suitable materials and thicknesses for the gate dielectric layer 114A are the same as or substantially the same as the material and thicknesses of the gate dielectric layer 106A. In some embodiments, the gate dielectric layer 114A, is formed by an atomic layer deposition (ALD) process or a PVD process. A gate electrode layer 114B is then blanket deposited on the gate dielectric layer 114A in the gate opening 221. After deposition of the gate dielectric layer 114A and the gate electrode layer 114B, a planarization process is performed to remove the gate dielectric layer H4A and the gate electrode layer 114B from an uppermost surface of the dielectric layer 128. In some embodiments, the planarization process includes a chemical mechanical polish process, where the CMP process forms a gate 114 having an uppermost surface that is co-planar or substantially co-planar with the uppermost surface of the dielectric layer 128 as illustrated in the cross-sectional illustration of Figure 2M.

Figure 2N illustrates a cross-sectional view of the structure of Figure 2M, following the formation of source contact 122 and drain contact 124. In some embodiments, contact openings are formed in the dielectric layer 128 above the source contact 122 and above the drain contact 124 by a plasma etch process. In some embodiments, one or more layers of contact metal are deposited inside each of the contact openings on the surface of the source structure 116 and on the surface of the drain structure 118, respectively. In the illustrative embodiment, the one or more layers of the contact metal are also blanket deposited on the uppermost surface of the dielectric layer 128 and on the gate 114. In some embodiments, the one or more layers of contact metal are deposited using a plasma enhanced chemical vapor deposition (PECVD) or an ALD process. In some embodiments, suitable contact metals include metals such as but not limited to Ti, Al or Ni. In some embodiments, a tungsten capping layer is deposited on the one or more layers of contact metal. In some embodiments, where the tungsten capping layer is deposited on the one or more layers of contact metal, the one or more layers of contact metal is first deposited on the bottom and on the sides of the opening and the tungsten capping layer is deposited to fill the remaining portion of the contact openings. In some embodiments, the one or more layers of contact metal is deposited to a thickness in the range of l0-30nm, and the tungsten capping layer is deposited to fill the remaining portion of each of the contact openings.

A planarization process is carried out to remove the one or more layers of contact metal from the uppermost surface of the dielectric layer 128. In one embodiment, the planarization process includes a chemical mechanical polish (CMP) process. The CMP process removes all the one or more layers of contact metal from the uppermost surfaces of the dielectric layer 128, and from the uppermost surface of the gate 114. The CMP process leaves the one or more layers of contact metal in the contact openings to form source contact 122 and drain contact 124.

Figure 20 illustrates a cross-sectional view of the structure of Figure 2N, following the formation of a mask to define locations of openings for shield structure contacts. In some embodiments, a layer of resist is formed and patterned into a mask 153 as shown in Figure 20. The location of the openings in the shield structure contact are on a plane behind the cross- sectional plane illustrated in Fig 20. In other embodiments, mask 153 may include a patterned dielectric layer including a material such as but not limited to silicon dioxide or silicon nitride. The thickness of the mask may range from lOOnm - 2000nm.

Figure 2P illustrates a plan view of the structure of Figure 20 with the A-A’ of the cross- sectional illustration of Figure 20 further shown in dashed line, following formation of shield structure contact opening 152. In some embodiments, a plasma etch is utilized to etch through dielectric layer 128, channel layer 112 and buffer layer 110 to expose shield feature 106.

Figure 2Q illustrates a cross-sectional view of the structure of Figure 2P, with the B-B’ of the cross-sectional illustration of Figure 2P further shown in dashed line, following the deposition of shield structure contact metal 229 in the plurality of contact openings 152. In some embodiments, mask 153 is removed after the formation of the plurality of contact openings 152, as is depicted in the cross-sectional illustration of Figure 2Q. In one example, contact material 229 is deposited into the plurality of contact openings 152 and subsequently planarized to a level below an uppermost surface 231 of the dielectric layer 128. In some embodiments, contact material 229 includes one or more materials that are the same or substantially the same as the materials for source contact 122 or drain contact 124.

Figure 2R illustrates a plan view of the structure of Figure 2Q, with the C-C’ of the cross- sectional illustration of Figure 2Q further shown in dashed line, following the planarization of the contact material 229 to form a plurality of shield contact structures 230 In some

embodiments, a CMP process is utilized to planarize the contact material 229. An outline 108 of shield structure 107 is also illustrated in Figure 2R.

Figure 3 illustrates a system 300 in which a mobile computing platform 305 and/or a data server machine 306 employs an integrated circuit including at least one device structure, such as the device structure 100 including a shield feature 106 and a III-N transistor 150 (Figure 1). Functionally, a voltage source may be coupled to the shield feature through a shield contact structure, such as is illustrated in Figure 2Q-2R. In one embodiment, the voltage source is to bias the shield feature(s) to a bias voltage between a first voltage of a transistor drain structure, and a second voltage of the substrate. In exemplary embodiment, the first voltage is between 150V and 200V, the second voltage is less than 50V (e.g., 0V) and the shield feature(s) is biased to less than 150 volts, during transistor operation.

The server machine 306 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic IC 350. The mobile computing platform 305 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 305 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 310, and a battery 315.

Whether disposed within the integrated system 310 illustrated in the expanded view 320, or as a stand-alone packaged chip within the server machine 306, packaged monolithic IC 350 includes a memory chip (e.g., RAM), or a processor chip (e.g., a microprocessor, a multi -core microprocessor, graphics processor, or the like) including at least one group III-N transistor 150 integrated with a shield feature 106, for example as describe elsewhere herein. The monolithic IC 350 may be further coupled to a board, a substrate, or an interposer 360 along with, one or more of a power management integrated circuit (PMIC) 330, RF (wireless) integrated circuit (RF1C) 325 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof 335.

Functionally, PMIC 330 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 315 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC 325 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative

implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the monolithic IC 350 or within a single IC coupled to the package substrate of the monolithic IC 350.

Figure 4 illustrates a computing device 400 in accordance with embodiments of the present invention. As shown, computing device 400 houses a board 402. Board 402 may include a number of components, including but not limited to a processor 404 and at least one communication chip 406. Processor 404 is physically and electrically coupled to the board 402. In some implementations, communication chip 406 is also physically and electrically coupled to board 402. In further implementations, communication chip 406 is part of processor 404.

Depending on its applications, computing device 400 may include other components that may or may not be physically and electrically coupled to board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g.,

ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communication chip 406 enables wireless communications for the transfer of data to and from computing device 400. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 400 may include a plurality of communication chips 406. For instance, a first communication chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 404 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 404 of the computing device 400 includes an integrated circuit die packaged within processor 404. In some embodiments, the integrated circuit die of processor 404 includes at least one device structure, such as the device structure 100 including a shield feature 106 and a III-N transistor 150, built in accordance with embodiments of the present disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 406 also includes an integrated circuit die packaged within the communication chip 406. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes a memory array with memory cells including at least one device structure, such as the device structure 100 including a shield feature 106 and a III-N transistor 150 described in association with Figures 1A and 2R integrated into a logic processor, built in accordance with embodiments of the present disclosure. Memory cells may include a magnetic tunnel junction device, a resistive random access memory device or a conductive bridge random access memory device integrated with a III-N transistor.

In various examples, one or more communication chips 404, 405 may also be physically and/or electrically coupled to the motherboard 402. In further implementations, communication chips 404 may be part of processor 401. Depending on its applications, computing device 400 may include other components that may or may not be physically and electrically coupled to motherboard 402. These other components may include, but are not limited to, volatile memory (e g., DRAM) 407, 408, non-volatile memory (e.g., ROM) 410, a graphics processor 412, flash memory, global positioning system (GPS) device 413, compass 414, a chipset 406, an antenna 416, a power amplifier 409, a touchscreen controller 411, a touchscreen display 417, a speaker 415, a camera 403, and a battery 418, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device 400 and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of memory cells 300 and/or transistor 100, built in accordance with embodiments of the present invention.

In various implementations, the computing device 400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 400 may be any other electronic device that processes data.

Figure 5 illustrates an integrated circuit (IC) structure that includes one or more transistors and memory cells described in embodiments of the present disclosure. The integrated circuit (IC) structure 500 is an intervening substrate used to bridge a first substrate 502 to a second substrate 504. The first substrate 502 may be, for instance, an integrated circuit die. The second substrate 504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. In some embodiments, the integrated circuit die includes one or more device structures, such as device structure 100, including a shield feature 106 and a III-N transistor 150 as described in association with Figures 1A-1C and 2A-2R above. In some embodiments, the memory module includes memory cells with one or more transistors having device structure 100 (Figure 1), including a shield feature and a III-N transistor. An integrated circuit (IC) structure 500 may couple an integrated circuit die to a ball grid array (BGA) 506 that can subsequently be coupled to the second substrate 504. In some embodiments, the first and second substrates 502/504 are attached to opposing sides of the integrated circuit (IC) structure 500. In other embodiments, the first and second substrates 502/504 are attached to the same side of the integrated circuit (IC) structure 500. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 500.

The integrated circuit (IC) structure 500 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects 508 and vias 510, including but not limited to through-silicon vias (TSVs) 510. The integrated circuit (IC) structure 500 may further include embedded devices 514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, one or more device structures, such as device structure 100, including a shield feature 106 and a III-N transistor 150, memory modules including at least one memory cell having a non-volatile memory element coupled to a drain structure 124 of the device structure 100, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 500. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 500.

Thus, embodiments of the present invention include a shield feature for a III-N device and method of fabrication.

In first examples, a device structure includes a trench in a substrate layer and one or more layers of group Ill-nitride (III-N) material within the trench. A shield feature is within the trench, where the shield feature is embedded within the III-N material and has a higher electrical conductivity than the III-N material and a transistor over the shield feature and the III-N material.

In second examples, for any of first examples, the shield feature is one of a plurality of lines spaced apart within the trench, and having III-N material between the lines.

In third examples, for any of the first through second examples, the plurality of lines includes a shield structure of a first width and a first length, and where the transistor has a channel of a second width, parallel to the first width, and a second length, parallel to the first length. The first width is greater than the second width and the first length is greater than the second length.

In fourth examples, for any of the first through third examples, each of the plurality of lines has a width less than 250nm and a thickness less than 200nm, and where spacing between adjacent one of the lines is between l00nm-250nm.

In fifth examples, for any of the first through fourth examples, the shield structure includes at least 10 lines.

In sixth examples, for any of the first through fifth examples, the shield feature includes at least one of a compound including titanium, a compound including tantalum, a compound including aluminum, or a group IV material.

In seventh examples, for any of the first through sixth examples, the III-N material includes aluminum.

In eighth examples, for any of the first example, the III-N material within the trench is a first III-N material and the device structure further includes the shield feature on the first PI-N material and a buffer layer including a second III-N material over the first III-N material, on the shield feature and extending laterally beyond a sidewall of the trench and beyond an isolation layer on the substrate adjacent to the trench.

In ninth examples, for any of the eighth example, the aluminum content within the buffer layer decreases with distance from the shield feature toward the transistor.

In tenth examples, for any of the eight through ninth examples, the aluminum content decreases from 75% to 25% atomic percent.

In eleventh examples, for any of the eight through tenth examples, the buffer layer has a first portion having an Al content that is 75 atomic percent, a second portion above the first portion having an Al content that is 50 atomic percent, and a third portion above the second portion having an Al content that is 25 atomic percent.

In twelfth examples, for any of the eleventh example, the first portion has a thickness between 200-3 OOnm, wherein the second portion has a thickness between 200-3 OOnm and wherein the third portion has a thickness between 200-300nm.

In thirteenth examples, for any of the first through twelfth examples, the III-N material in the trench has a thickness between 750nm-l250nm.

In fourteenth examples, for any of the first through eight examples, the device structure further includes a channel layer including a third III-N material over the buffer layer and extending laterally beyond the sidewall of the trench, the channel layer having a thickness of at least 0.75pm. In fifteenth examples, for any of the first example, the transistor includes a polarization charge inducing layer above the channel layer and the polarization charge inducing layer includes a fourth III-N material. The transistor further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode and a source contact coupled with the source structure and a drain contact coupled with the drain contact.

In sixteenth examples, for any of the fifteenth example, the polarization charge inducing layer has a thickness between 3nm-20nm, where the source structure and the drain structure each include a material that is lattice matched to the third III-N material and include n-type impurity dopants and where the transistor further includes a gate dielectric layer between the gate electrode and the polarization charge inducing layer, where the gate dielectric layer is a Hi-K dielectric layer.

In seventeenth examples, a method of fabricating a device structure includes forming a trench in a substrate. The method further includes forming a first layer including a first group Ill-nitride (III-N) material in the trench and forming a shield feature on the first III-N material, where forming the shield feature further includes. The method is continued with forming a layer of a conductive material on the first III-N material, where the conductive material has a higher electrical conductivity than the first III-N material, and patterning the layer of conductive material into the conductive feature. The method further includes forming a second layer including a second III-N material over the first layer and over the plurality of conductive fins and concludes by forming a transistor over the shield feature and the second III-N material.

In eighteenth examples, for any of the seventeenth example the method further includes forming a buffer layer including a third III-N material, between the first III-N material and the second III-N material.

In nineteenth examples, for any of the seventeenth through eighteenth examples, forming the third III-N material includes epitaxially growing the third III-N material on the first III-N material and laterally overgrowing the shield feature.

In twentieth examples, for any of the seventeenth through nineteenth examples, forming the third III-N material includes depositing a third III-N material and decreasing the atomic percent of the aluminum content gradually during the deposition.

In twenty-first examples, for any of the seventeenth through twentieth examples, the method further includes forming the second layer over an isolation on the substrate.

In twenty-second examples, for any of the seventeenth through twenty-first examples, forming the substrate shield structure further includes removing the conductive material from a sidewall of the trench. In twenty -third examples, for any of the seventeenth example, forming the transistor includes forming a polarization charge inducing layer including a fourth III-N material above the second III-N material and forming a first recess and a second recess, laterally separated from the first recess, in the second III-N semiconductor material. The method further includes forming a source structure in the first recess and a drain structure in the second recess where forming the source structure and the drain structure includes doping the source structure and the drain structure with an n-type impurity. The method concludes with forming a gate dielectric layer on the polarization charge inducing layer and forming a gate electrode on the gate dielectric layer.

In twenty-fourth examples, an integrated circuit (IC), includes a transistor over a substrate, where the transistor includes a source and drain coupled through a channel including a III-N material, a shield feature between the channel and the substrate and a voltage source coupled to the shield feature, where the voltage source is to bias the shield feature to a bias voltage between a first voltage of the drain and a second voltage of the substrate.

In twenty-fifth examples, for any of the twenty-fourth examples, the first voltage is between 150V and 200V, the second voltage is 0V and the shield feature is biased to a voltage of less than 150V.

Claims

Claims What is claimed is:

1. A device structure comprising:

a trench in a substrate layer;

one or more layers of group Ill-nitride (III-N) material within the trench;

a shield feature within the trench, wherein the shield feature is embedded within the III-N material and has a higher electrical conductivity than the III-N material; and

a transistor over the shield feature and the III-N material.

2. The device structure of claim 1, wherein the shield feature is one of a plurality of lines spaced apart within the trench, and with III-N material between the lines.

3. The device structure of any of claims 1-2, wherein the plurality of lines comprise a shield structure of a first width and a first length, and wherein the transistor has a channel of a second width, parallel to the first width, and a second length, parallel to the first length, and wherein the first width is greater than the second width and the first length is greater than the second length.

4. The device structure of any of claims 1-3, wherein each of the plurality of lines has a width less than 250nm and a thickness less than 200nm, and wherein spacing between adjacent one of the lines is between l00nm-250nm.

5. The device structure of any of claims 1-4, wherein the shield structure comprises at least 10 lines.

6. The device structure of any of claims 1-5, wherein the shield feature comprises at least one of a compound comprising titanium, a compound comprising tantalum, a compound comprising aluminum, or a group IV material.

7. The device structure of any of claims 1-6, wherein the III-N material comprises aluminum.

8. The device structure of claim 1, wherein:

the III-N material within the trench is a first III-N material; and

the device structure further comprises; the shield feature on the first III-N material; and

a buffer layer comprising a second III-N material over the first III-N material, on the shield feature and extending laterally beyond a sidewall of the trench and beyond an isolation layer on the substrate adjacent to the trench.

9. The device structure of claim 8, wherein the aluminum content within the buffer layer decreases with distance from the shield feature toward the transistor.

10. The device structure of any of claims 8-9, wherein the aluminum content decreases from 75% to 25% atomic percent.

11. The device structure of any of claims 8-10, wherein the buffer layer has a first portion having an A1 content that is 75 atomic percent, a second portion above the first portion having an A1 content that is 50 atomic percent, and a third portion above the second portion having an A1 content that is 25 atomic percent.

12. The device structure of claim 11, wherein the first portion has a thickness between l50nm- 300nm, wherein the second portion has a thickness between 150nm-300nm and wherein the third portion has a thickness between l50nm-300nm.

13. The device structure of any of claims 1-12, wherein the III-N material in the trench has a thickness between 750nm-1250nm

14. The device structure of claim 8, wherein the device structure further comprises a channel layer comprising a third III-N material over the buffer layer and extending laterally beyond the sidewall of the trench, the channel layer having a thickness of at least 0.75pm.

15. The device structure of claim 1, wherein the transistor comprises:

a polarization charge inducing layer above the channel layer, the polarization charge inducing layer comprising a fourth III-N material;

a gate electrode above the polarization charge inducing layer; and

a source structure and a drain structure on opposite sides of the gate electrode and a source contact coupled with the source structure and a drain contact coupled with the drain contact.

16. The semiconductor structure of claim 15, wherein the polarization charge inducing layer has a thickness between 3nm-20nm, wherein the source structure and the drain structure each comprise a material that is lattice matched to the third III-N material and include n-type impurity dopants and wherein the transistor further comprises a gate dielectric layer between the gate electrode and the polarization charge inducing layer, wherein the gate dielectric layer is a Hi-K dielectric layer.

17. A method of fabricating a device structure, the method comprising:

forming a trench in a substrate;

forming a first layer comprising a first group Ill-nitride (III-N) material in the trench; forming a shield feature on the first III-N material, wherein forming the shield feature further comprises:

forming a layer of a conductive material on the first PI-N material, wherein the conductive material has a higher electrical conductivity than the first III-N material; and

patterning the layer of conductive material into the conductive feature;

forming a second layer comprising a second III-N material over the first layer and over the plurality of conductive fins; and

forming a transistor over the shield feature and the second III-N material.

18. The method of claim 17, further comprises forming a buffer layer comprising a third III-N material, between the first III-N material and the second III-N material.

19. The method any of claims 17- 18, wherein forming the third III-N material comprises epitaxially growing the third III-N material on the first III-N material and laterally overgrowing the shield feature.

20. The method any of claims 17- 19, wherein forming the third III-N material comprises depositing a third III-N material and decreasing the atomic percent of the aluminum content gradually during the deposition.

21. The method of any of claims 17-20, further comprises forming the second layer over an isolation on the substrate.

22. The method of any of claims 17-21, wherein forming the substrate shield structure further comprises removing the conductive material from a sidewall of the trench

23. The method of claim 17, wherein forming the transistor comprises:

forming a polarization charge inducing layer comprising a fourth III-N material above the second III-N material;

forming a first recess and a second recess, laterally separated from the first recess, in the second III-N semiconductor material;

forming a source structure in the first recess and a drain structure in the second recess wherein forming the source structure and the drain structure comprises doping the source structure and the drain structure with an n-type impurity;

forming a gate dielectric layer on the polarization charge inducing layer; and forming a gate electrode on the gate dielectric layer.

24. An integrated circuit (IC), comprising:

a transistor over a substrate, wherein the transistor comprises a source and drain coupled through a channel comprising a III-N material;

a shield feature between the channel and the substrate; and

a voltage source coupled to the shield feature, wherein the voltage source is to bias the shield feature to a bias voltage between a first voltage of the drain and a second voltage of the substrate.

25. The IC of claim 24, wherein the first voltage is between 150V and 200V, the second voltage is 0V and the shield feature is biased to a voltage of less than 150V.