WO2018182605A1

WO2018182605A1 - Iii-n semiconductor devices with raised doped crystalline substrate taps

Info

Publication number: WO2018182605A1
Application number: PCT/US2017/024961
Authority: WO
Inventors: Han Wui Then; Paul B. FISCHER; Marko Radosavljevic; Sansaptak DASGUPTA
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

Semiconductor devices including III-N transistors adjacent to III-N substrate taps extending from a group IV heteroepitaxial growth substrate are described. In embodiments, GaN mesas that are to host conductive substrate taps are grown concurrently with GaN mesas that are to host transistors. A GaN mesa for a substrate tap is then selectively doped, for example with a masked implant. An intrinsic GaN mesa for a transistor is then selectively processed, for example to form a transistor channel. Heavily doped semiconductor may then be grown on all GaN mesas and contact metallization landed on the heavily doped semiconductor. Backend interconnect levels may then be successively landed on the substrate tap to maintain an electrical path to the substrate sufficient to mitigate charging-related damage to the transistors during backend processing.

Description

III-N Semiconductor Devices With Raised Doped Crystalline Substrate Taps

BACKGROUND

Many advanced semiconductor devices in development leverage non-silicon semiconductor materials, including III-N materials, as well as other materials with wurtzite crystallinity, which show particular promise for high voltage and high frequency applications like power management ICs and RF power amplifiers. III-N heteroepitaxial (heterostructure) field effect transistors (HFETs), such as high electron mobility transistors (HEMTs) and metal oxide semiconductor (MOS) HEMTs, employ a semiconductor heterostructure with one or more heteroj unction. GaN-based HFET devices benefit from a relatively wide bandgap (~3.4eV), enabling higher breakdown voltages than Si-based MOSFETs, as well as high carrier mobility. The III-N material system is also useful for photonics (e.g., LEDs), photovoltaics, and sensors, one or more of which may be useful to integrate into an electronic device platform.

For high frequency (e.g., GHz band) devices (e.g., RFICs), electrical resistance of the substrate material upon which an IC is fabricated is often important. As an IC's operating frequency increases, parasitic losses associated with the substrate become more substantial unless the resistivity of the substrate material is increased. However, high- resistivity substrates can cause complications during the IC fabrication process. Plasma etching and plasma enhanced chemical vapor deposition (PECVD), for example, may induce a local build-up of electrical charges. These charges, if discharged through a device such as a transistor, can cause catastrophic damage to an IC.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:

FIG. 1 A is a cross-sectional view of a semiconductor device structure including a transistor and a substrate tap, in accordance with some embodiments; FIG. IB is a top-down plan view of the semiconductor device structure shown in FIG. 1A, in accordance with some embodiments;

FIG. 2 and 3 are flow diagrams illustrating methods of forming the semiconductor device structure shown in FIG. 1A, in accordance with some embodiments; FIG. 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are cross-sectional views of a semiconductor device structure evolving as selected operations in the methods illustrated in FIG. 3 are performed, in accordance with embodiments;

FIG. 15 illustrates a mobile computing platform and a data server machine employing an IC having GaN HFETs and GaN substrate tap structures, in accordance with embodiments of the present invention; and

FIG. 16 is a functional block diagram of an electronic computing device, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.

Reference is made in the following detailed description to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Further, it is to be understood that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of claimed subject matter. It should also be noted that directions and references, for example, up, down, top, bottom, and so on, may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be taken in a limiting sense and the scope of claimed subject matter is defined solely by the appended claims and their equivalents.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms "over," "under," "between," and "on" as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

As used throughout this description, and in the claims, a list of items joined by the term "at least one of or "one or more of can mean any combination of the listed terms. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

Described herein are heteroepitaxial substrate tap structures including one or more raised doped semiconductor material grown on a crystalline seeding surface. These substrate tap structures may be able to reduce charge build-up on adjacent transistor structures that would otherwise provide the most likely conduit for various discharge mechanisms. The substrate tap structures described herein may thereby mitigate one or more manufacturing difficulties associated with fabricating III-N ICs on a high-resistivity substrate. Similar difficulties may face SOI substrates where the device semiconductor is a floating body and the buried insulator provides a highly resistive discharge path. However, because the buried insulator of an SOI substrate is typically thin, it is relatively straightforward and inexpensive to form a conductive via (trench) through the buried insulator as a conductive path to the underlying semiconductor. For III-N ICs fabricated on a silicon substrate (e.g., GaN-on-Si, or "GOS" technology), a similar approach might necessitate a very deep conductive via (trench) to contact the substrate, which would be technically challenging and add considerable cost to the III-N IC fabrication process. As described further below, substrate tap structures in accordance with some embodiments may be fabricated along with devices of an IC and may therefore be present in the final IC structure albeit inactive within the IC. In some embodiments, a substrate tap structure comprises a mesa of III-N material grown upon a silicon substrate. At least a portion of the III-N mesa may be doped to have higher conductivity than adjacent structures employed by active devices. A substrate tap structure may, for example, include an III-N mesa that has been doped n-type, for example through a selective implant. A tap structure may, for example, include a III-N mesa with a heavily doped region suitable for making a contact junction with interconnect metallization. A substrate tap structure may, for example, include a III-N mesa with a heavily doped n-type region having the same composition as a source or drain of an adjacent transistor. A tap structure may, for example, include one or more levels of metallization electrically coupled to the III-N mesa through a metal- semiconductor junction. In some embodiments, a substrate tap structure may be fabricated concurrently with the fabrication of a transistor such that the tap structure may mitigate charge build up on the transistor during fabrication of the IC. In some embodiments, a III-N transistor is on a III-N mesa heteroepitaxially grown on an underlying substrate, such as a group IV semiconductor material. A III-N substrate tap is on a second III-N mesa heteroepitaxially grown on the underlying substrate. Conductive interconnect structures in one or more overlying metallization levels are coupled to the transistor and/or to the substrate tap. FIG. 1A is a cross-sectional view of a semiconductor device structure 100 including a transistor 101 and a substrate tap 102, in accordance with some embodiments. FIG. IB is a top-down plan view of semiconductor device structure 100, in accordance with some embodiments. The cross-sectional view shown in FIG. 1A is along the A-A' line shown in FIG. IB, for example.

Transistor 101 is on a non-silicon crystalline mesa 115 heteroepitaxially grown on a surface of a growth substrate 105. Substrate tap 102 is also on a non-silicon crystalline mesa 120 heteroepitaxially grown on a surface of a growth substrate 105. In some exemplary embodiments, growth substrate 105 is a (100) cubic semiconductor, such as monocrystalline silicon. In some further embodiments, growth substrate 105 is a high-resistivity substrate having a resistivity of at least 500 ohm-cm. In some such embodiments, the resistivity is between 1,000 and 10,000 ohm-cm. In some embodiments, crystalline mesa 115 is a III-N material, such as, but not limited to A1N, GaN, AlGaN, or InAlGaN. Mesa 120 may also be a III-N material, such as, but not limited to A1N, GaN, AlGaN, or InAlGaN. In some embodiments, mesas 115 and 120 comprise the same III-N material. For example, both mesas 115 and 120 may be GaN. Notably, although structures and techniques are described in detail in the context of exemplary III-N materials, they may be more generally applicable to the family of wurtzite semiconductors further including at least Agl, ZnO, CdS, CdSe, a-SiC, and BN, and may also be further applicable to other non-silicon material systems, such as, but not limited to GaAs, InP, InAs, InGaAs, InGaP, etc. Hence, one of skill in the art familiar with the characteristics of these alternate semiconductor material systems will may successfully apply the techniques described herein absent some specific knowledge of a salient incompatibility between the exemplary III-N material system described in detail herein and the alternate material system.

In some embodiments, mesas 115 and 120 have monocrystalline microstructure. Crystal quality of mesas 115 and 120 may vary dramatically as a function of the material composition and techniques employed to form the mesas. As shown in FIG. 1 A, mesas 115 and 120 are laterally overgrown from windows or trenches patterned in an amorphous material 110. Amorphous material 110 may be alumina (AI2O3), silica (SiO), silicon nitrides (SiN), silicon oxynitrides (SiON), or silicon carbonitrides (SiCN), for example. Amorphous material 110 prevents nucleation of crystalline mesa material such that the much of growth of mesas 115, 120 lateral overgrowth. Lateral overgrowth maintains the crystallinity established at the seeding surface of substrate 105 exposed within template trenches. In exemplary embodiments, the seeding surface is a (100) cubic surface. Mesas of GaN grown in this manner may have a dislocation density of 10⁸-10ⁿ/cm². In some III-N embodiments, the oaxis of the III-N crystal is aligned approximately normal to a top surface of mesas 1 15 and 120. Practically however, the oaxis may be slightly tilted, for example a few degrees less than normal, for example as a result of imperfect epitaxial growth on an offcut or off- axis substrate, etc. In some embodiments, the {000-1 } plane is more proximate a backside surface of mesas 1 15 and 120. Such embodiments may be referred to as Ga polarity (+c) because the three bonds of Ga (or other group III element) point towards substrate 105. For alternate embodiments where the three bonds of Ga (or other group III element) point in the opposite direction, mesas 1 15, 120 would be referred to as N polarity (-c). Dimensions of mesas 1 15, 120 may vary as a function of the dimensions of the template trenches patterned in amorphous material 1 10. These template trenches may, for example, extend in a <1 10> direction of the substrate exposing stripes of a (100) silicon surface and have a smallest width W of a few micrometers to tens of micrometers, for example. In some embodiments, mesas 1 15 and 120 have substantially the same z- dimension, with both mesas 115 and 120 having a mesa height H as measured from a surface of amorphous material 1 10. Mesa height H may vary, but is advantageously less than 5 micrometers. For some embodiments where trench width W is 10-15 μιτι, mesa height H is 2-3μηι. As further shown in FIG. 1A, dummy mesas 125 may be present between mesa 1 15, 120. Dummy mesas 115 are physically smaller than mesas 115, 120 as limited by their smaller window dimensions. Mesas 120 and 115 are embedded within an isolation dielectric material 130, which may be any flowable dielectric for example. Dielectric material 130 may be planar with a top surface of mesas 1 15, 120, or planar with a top surface of a semiconductor layer covering mesas 115, 120. Isolation dielectric material 130 may completely cover dummy mesas 125. In some embodiments, the electrically active impurity concentration(s) in a III-N mesa of a substrate tap is higher than the electrically active impurity concentration(s) in a III-N mesa hosting a transistor. Hence, even where mesas 115 and 120 comprise the same majority lattice constituents (e.g., both are GaN), mesa 120 may be doped to a higher level. In the example shown in FIG. 1A, mesa 120 is doped n-type while mesa 1 15 is intrinsic (i.e., not intentionally doped n-type). Exemplary n-type dopants include, but are not limited to, silicon (Si) and germanium (Ge). In some exemplary embodiments, mesa 120 is doped to an impurity concentration of at least lel 7 atoms/cm³ (e.g., I el7-lel 8) atoms/cm³. In contrast, intrinsic impurity (e.g., Si) levels in mesa 1 15 may be less than l el 7 atoms/cm³, and in some exemplary embodiments is between l el4 and lel 6 atoms/cm³. The more heavily doped mesa 120 improves conductivity of the III-N material, providing a less resistive tap to substrate 105. A transistor employs one or more semiconductor material layer embedded in or located on the mesa. A substrate tap may also employ one or more semiconductor material layer embedded in or located on the mesa. A transistor and substrate tap may comprise different semiconductor layers embedded in or located on the mesa. In exemplary embodiments, these semiconductor material layers are crystalline and may be disposed over a sidewall or a top surface of the underlying mesa. In some embodiments, these

semiconductor material layers materials are epitaxial having a microstructure and orientation derived from that of the underlying mesa. In some embodiments, these semiconductor material layers may form a heterostructure comprising one or more heteroj unction.

For transistor 101 , in the context of an exemplary GaN crystalline mesa, these semiconductor material layers may include one or more polarization layers (e.g., A1N, and/or AlInN, and/or AlGaN, and/or InGaN). A polarization layer 1 16 creates a two- dimensional electron gas (2DEG) within the GaN near the heterojunction. A gate stack 140 may be recessed into such a polarization layer to tune threshold voltage (Vt) of the transistor. For example, a recessed gate stack 104 may ensure a positive Vt for an enhancement mode n-type transistor. Gate stack 104 may include a gate electrode that may be any metal or semiconductor known to have suitable conductivity and work function. The gate stack may further include a gate dielectric, such as any high-k or conventional dielectric material known to be suitable for III-N FETs.

For transistor 101 semiconductor layers on mesa 1 15 further include source and drain semiconductor 135. Source and drain semiconductor 135 may be electrically coupled with the 2DEG present within mesa 115. Source and drain semiconductor 135 is advantageously heavily doped (e.g., with Si for n-type) and may include a raised impurity-doped material in physical contact with at least a oplane of the first mesa. The impurity doping level may be any typically employed for an N+ source/drain of a GaN device. Advantageously, source and drain semiconductor 135 has a dopant (e.g., Si) concentration exceeding the dopant (e.g., Si) concentration in mesa 115 and in mesa 120. For example, source and drain semiconductor 135 may have a dopant concentration of at least l ei 8 atoms/cm³. For some embodiments, the raised doped N+ material is substantially monocrystalline. Dislocation density within source and drain semiconductor 135 may be between 10⁹ cm^"2 and 10¹² cm^"2, for example. Material having many orders of magnitude higher dislocation density is also possible, and in some embodiments source and drain semiconductor 135 may be polycrystalline. Source and drain semiconductor 135 may be of any composition known to be suitable for the device layer material compositions. In one exemplary embodiment where mesa 1 15 is GaN, source and drain semiconductor 135 comprises InGaN.

For substrate tap 102, semiconductor layers on mesa 120 may include a tap contact semiconductor 136. Tap contact semiconductor 136 is advantageously heavily doped (e.g., with Si for n-type), and facilitates a low resistance metal-semiconductor junction. Tap contact semiconductor 136 may be a raised impurity-doped material in physical contact with mesa 120. The doping level may be any typically employed for an N+ source/drain of a GaN transistor. Advantageously, tap contact semiconductor 136 has an impurity concentration exceeding that of mesa 120. For example, tap contact semiconductor 136 may have an n- type dopant concentration of at least lel 8 atoms/cm³. For some embodiments, the raised doped N+ material is substantially monocrystalline. Dislocation density within tap contact semiconductor 136 may be between 10⁹ cm^"2 and 10¹² cm^"2, for example. Material having many orders of magnitude higher dislocation density is also possible, and in some embodiments tap contact semiconductor 136 is polycrystalline. Tap contact semiconductor 136 may be of any composition known to be suitable for the device layer material compositions. In one exemplary embodiment where mesa 120 is GaN, tap contact semiconductor 136 comprises a single crystal of InGaN.

In some exemplary embodiments, tap contact semiconductor 136 has substantially the same majority lattice constituents as source and drain semiconductor 135. In some further embodiments, tap contact semiconductor 136 has substantially the same

microstructure as source and drain semiconductor 135. In some further embodiments, tap contact semiconductor 136 has substantially the same impurity concentration as source and drain semiconductor 135. In some embodiments, tap contact semiconductor 136 is substantially the same material and has substantially the same material thickness as source and drain semiconductor 135. As illustrated in FIG. 1A, substrate tap 102 lacks a gate stack 140 and also lacks polarization layer 116. Hence tap contact semiconductor 136 covers the top surface of mesa 120, as further illustrated in FIG. IB. Whereas, source and drain semiconductor 135 is separated by at least gate stack 140. The large area of tap contact semiconductor 136 may form a metal-semiconductor junction with one contact of larger dimension and/or with many contacts of smaller dimension. Such metal-semiconductor junctions may be ohmic or rectifying. Interconnect structures of one or more conductive routing levels are electrically coupled to source and drain semiconductor 135 through one or more metal-semiconductor junctions. In the example shown in FIG. 1A and IB, interconnect levels 150 include conductive structures interconnecting any number of transistors 101 into an integrated circuit (IC). Interconnect levels 150 include conductive structures (e.g., metallization 190) embedded in trenches and/or vias dielectric 180. Metallization 190 may be any metal or metal alloy (e.g., predominantly copper), or even heavily-doped semiconductor. Dielectric 180 may be any electrical insulator, such as, but not limited to SiOC(H), HSQ, MSQ, or other low-k materials.

In the embodiment illustrated in FIG. 1A and IB, interconnect levels 150 include two interconnect structures 155, each with contact metallization, that are separately landed on source and drain semiconductor 135. Separate interconnect structures 155 may be insulated from gate stack 140 by a dielectric sidewall spacer (not depicted). Other portions of interconnect levels 150 are also electrically coupled to substrate tap contact

semiconductor 135 through one or more metal-semiconductor junctions. Interconnect levels 150 further include two interconnect structures 156, each with contact metallization, that are landed on tap contact semiconductor 136. In some embodiments interconnect structures 156 are substantially the same as interconnect structures 155. For example, interconnect structures 156 may have the same lateral dimensions, the same vertical depth, and the same composition as interconnect structures 155. As such, substrate tap 102 may be considered a dummy transistor 101, lacking only some of the structural elements (e.g., gate and/or channel) of an operational transistor.

Features of one or more interconnect levels may be electrically coupled to a substrate-tap through one or more metal-semiconductor junctions. In the example shown in FIG. 1A and IB, two interconnect structures 155 are landed on tap contact semiconductor 136. Substrate tap 102 may be electrically interconnected with transistor 101 through interconnect levels 150. Alternatively, substrate tap 102 may be electrically connected to portions of interconnect levels 150 that are not further electrically interconnected with transistor 101. Advantageously, every interconnect level employed in the interconnection of transistor 101 is also present in the interconnect structures coupled to substrate tap 102 to ensure an antenna structure of substrate tap 102 is exposed to the same charging mechanisms as transistor 101 throughout the fabrication of all the interconnect levels. In some embodiments, a plurality of substrate taps 102 is adjacent to transistor 101, increasing the tap area and/or tap antenna area relative to the transistor area and/or transistor antenna area. As shown in FIG. IB, many substrate taps 102 are located about a perimeter surrounding transistor 101.

The semiconductor heterostructures and semiconductor devices described above may be fabricated using a variety of methods. FIG. 2 is a flow diagram illustrating methods of forming a semiconductor device structure including substrate taps and transistors, in accordance with some embodiments. Methods 201 (FIG. 2) begin at operation 205 where a substrate including a crystalline seed layer is received. The substrate received at operation 205 may be any of those described above, for example. At operation 210, a III-N epitaxial growth process is employed to form crystal mesas on the substrate seeding surface. Method 201 continues at operation 215 where a subset of the III-N mesas grown at operation 210 that are to become substrate taps are impurity doped while the remainder that are to host a transistor are protected from such doping. In some embodiments, a masked impurity implantation is performed at operation 215 to implant the impurities deep with the III-N mesa.

At operation 220, a field effect transistor (FET) is fabricated on intrinsic III-N mesas that were not implanted. During operation 220, the III-N mesas impurity doped at operation 215 may be masked, for example with an amorphous hardmask while a polarization material layer is epitaxially grown over exposed surfaces of the intrinsic III-N mesas. Other FET structures, such as a gate stack (sacrificial or permanent), may also be fabricated at operation 220. At operation 225, heavily-doped (e.g. N+) III-N material is epitaxially grown on exposed surfaces of III-N material. In some embodiments, the heavily-doped material is formed on both the intrinsic III-N mesas and impurity -doped III-N mesas. Any known epitaxial or non-epitaxial deposition process may be employed at operation 225 to form the in-situ doped III-N semiconductor material. At operation 230, back-end of line (BEOL) interconnect structures are fabricated over the FET mesas and substrate tap mesas. The BEOL interconnect structures may contact the heavily-doped semiconductor formed on each mesa. Any known BEOL processing may be performed at operation 230 to complete the IC. The presence of substrate taps thus formed may reduce charging damage to transistors, for example during the BEOL processing. Following operation 230, the IC is substantially complete and it may be singulated and packaged following any conventional techniques. FIG. 3 is a flow diagram illustrating methods 301 of forming the semiconductor device structure 100, in accordance with some embodiments. Methods 301 further illustrate some specific embodiments of methods 201. FIG. 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are cross-sectional views of semiconductor device structure 100 evolving as selected operations in the methods 301 are performed, in accordance with some embodiments. In FIG. 3, methods 301 begin at operation 305 where an amorphous material is deposited over a resistive substrate. The resistive substrate, may for example be a silicon substrate with a resistivity over 500 ohm-cm. The amorphous material may be a dielectric deposited with any technique known to be suitable for the material. At operation 305, the amorphous material is patterned, for example to form trenches in the amorphous material that expose a crystalline seeding surface of the substrate. The crystalline seeding surface may be a surface of the bulk substrate or of some interfacial material of the substrate. The amorphous material is patterned as a template for subsequent non-silicon epitaxial growth. Any pattern transfer technique may be utilized at operation 310. While any template structure known to be suitable for heteroepitaxial growth of a non-silicon crystal may be employed at operation 310, in exemplary embodiments a (100) cubic semiconductor surface is exposed within trenches extending in a <110> direction of the substrate. FIG. 4 further illustrates one exemplary embodiment where substrate 105 includes amorphous material 110 patterned into a template structure.

Returning to FIG. 3, methods 301 continue at operation 315 where III-N crystal is epitaxially grown from the crystalline seeding surfaces unprotected by the amorphous material. Operation 315 may include deposition of a seed layer (e.g., A1N) and further rely on first epitaxial GaN growth conditions (e.g., a first GaN growth pressure, a first GaN growth temperature, and a first V/III growth precursor ratio). Following an initial growth period, growth conditions may be changed at operation 320 to a second GaN growth temperature, and/or a second V/III growth precursor ratio favoring lateral epitaxial overgrowth (LEO) of GaN to extend GaN mesa crystals over a top surface of amorphous material 110. Material growth may be by any known technique, such as, but not limited to metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), or molecular beam epitaxy (MBE). In some embodiments, elevated temperatures of 900 °C, or more, are employed at operation 315 to epitaxially grow a GaN crystalline structure. When the template structure is substantially backfilled (e.g., amorphous material planarized), growth conditions may be changed at operation 320. In some embodiments, the LEO process employed at operation 320 favors formation of inclined sidewall facets. Overgrowth at rates that favor wurtzite crystal facets non-parallel and non-normal to the c-plane have been found to bend defects away from the c-plane and toward the sidewalls such that quality of a top surface of the III-N crystalline structure improves with overgrowth time. In the exemplary embodiment further illustrated in FIG. 5, upon termination of operation 320, GaN mesas 115 and 120 have trapezoidal profiles, which continue expand with growth time. Notably the GaN growths during operations 315 and 320 include no intentional (in-situ) impurity doping. Hence, at this point in methods 301, GaN mesas 115 and 120 are substantially identical with an intrinsic impurity level. Returning to FIG. 3, methods 301 continue at operation 325 where mesas are planarized with a dielectric material and those that are to host a transistor (e.g., FET) are masked off with a masking material suitable for blocking a subsequent impurity

implantation. A gap-filling dielectric deposition process, such as a flowable oxide deposition (PECVD and/or spin-on) process may be employed to backfill the GaN mesas with an electrically insulating dielectric (e.g., SiO, SiNO, SiOC(H)). Planarization may also entail chemical-mechanical polishing of the gap-filling dielectric, stopping on a top surface of the GaN mesas. Following planarization, a hardmask material (e.g., a SiO, SiN, or SiON mask) or a photoresist mask is patterned to protect a subset of the GaN mesas. At operation 330, an n-type impurity dopant, such as Si or Ge, is implanted in the exposed (unmasked) GaN mesas. Any ion implantation process known to be suitable for the impurity may be employed at operation 330. The ion implantation may be performed at sufficient energy to achieve a given dose throughout the entire mesa height. In some embodiment the energy is sufficient to dope the GaN/Si heteroj unction n-type. Notably, because of the trapezoidal cross-sectional shape of the GaN mesas, the mesas exposed to the impurity implant may be partially masked by the gap-filling dielectric.

In the exemplary embodiment further illustrated in FIG. 6, top surfaces of GaN mesas 115, 120 have been planarized with isolation dielectric material 130. Si impurities are implanted in GaN mesas 120 while GaN mesa 115 is protected by a hardmask 605. As shown in FIG. 6, dashed lines 610 highlight peripheral edges of GaN mesa 120 that are masked from the Si implant by isolation dielectric material 130. In some embodiments, following the Si implant a thermal anneal is performed to electrically activate the Si impurities, rendering mesas 120 n-type. Any thermal processing known to be suitable for the purpose of activation may be employed as embodiments are not limited in this respect. In other embodiments, the Si impurities are activated during subsequent processing.

Returning to FIG. 3, methods 301 continue at operation 335 where the masking polarity is reversed to facilitate further processing of the subset of GaN mesas that are to host a transistor. Masking material from operation 325 may be stripped off and another masking material (e.g., a hardmask dielectric material) is patterned over the substrate tap mesas. In the exemplary embodiment further illustrated in FIG. 7, a mask 705 has been patterned to expose a top surface of GaN mesa 115 while protecting GaN mesa 120.

In FIG. 3, methods 301 continue at operation 340 where a III-N polarization layer is epitaxially grown on the exposed surface of the subset of GaN mesas that are to host a transistor. No polarization layer is grown on the substrate tap mesas that are masked. Any epitaxial process known to be suitable for growing a III-N polarization layer (e.g., AIN) may be employed at operation 340 as embodiments are not limited in this respect. Gate and/or channel processing may then be performed following polarization layer growth. In some embodiments, a recessed gate process is performed at operation 345 where a portion of the polarization layer grown at operation 340 is etched to define a channel recess. Various masking techniques may be employed to recess the channel. For example, one or more spacer dielectric may be deposited within openings in the hardmask protecting the substrate tap mesas. The spacer dielectric(s) may be of any composition, such as, but not limited to, SiO, SiON, or SiN. The spacer dielectric(s) may then be anisotropically etched to expose a portion of the underlying polarization layer. This exposed portion of the polarization layer may then be etched (e.g., with a wet chemical etchant) to a desired thickness. A gate stack, which may be sacrificial, may then be formed over the channel recess. In some

embodiments, a sacrificial gate stack includes one or more hardmask materials that may be subsequently removed selectively to the spacer dielectric(s). In the example shown in FIG. 8, a sacrificial gate stack 810 has been formed over a recessed channel region 805 of polarization layer 116. In FIG. 3, methods 301 continue at operation 350 where the mask formed at operation 335 is removed to expose the subset of GaN mesas that are to become substrate taps. Additionally, source/drain regions of the GaN mesas that are to be transistors are exposed, for example by removing one or more spacer dielectrics selectively to the

(sacrificial) gate stack. At operation 355, in-situ doped III-N semiconductor material, such as n+ doped source/drain material and n+ doped contact semiconductor, is epitaxially grown at nucleation sites on an exposed oplane of the GaN mesas and/or III-N polarization layer material. In some specific embodiments, at an epitaxial process may be employed to grow raised n+ doped InGaN source/drain material over portions of transistor mesas and grow raised n+ doped InGaN contact semiconductor material over the substrate tap mesas. If desired, a recess etch may be performed prior to forming the n+ doped III-N semiconductor material, for example to remove some, or all, of the polarization layer in the source/drain regions of the transistor mesa. The n+ doped semiconductor growth process may further serve to activate the impurities implanted into the substrate tap mesas at operation 330. With the high-temperature semiconductor material processing now complete, if a sacrificial gate was formed during methods 301 it may now be replaced with a permanent gate stack.

In an exemplary embodiment further illustrated in Fig. 9, hardmask 705 has been stripped exposing top surfaces of GaN mesa 120. Sacrificial gate stack 810 and, optionally, a dielectric spacer along sidewalls of gate stack 810 are retained to protect a channel region of GaN mesa 115. FIG. 10 further illustrates a recess etch of source/drain regions of GaN mesa 115. A plasma etch or wet etch may be employed to etch the III-N polarization layer and/or GaN mesa surfaces. A top surface of GaN mesa 120 may be recessed during such processing. FIG. 11 illustrates n+ doped III-N (e.g., InGaN) source and drain semiconductor 135 grown or deposited on either side of gate stack 810. The same n+ doped III-N material is concurrently grown as contact semiconductor 136 over GaN mesa 120. In some embodiments, n+ (Si) doped InGaN is grown by MOCVD, VPE, MBE, or the like. At this point, due to the thermal processing performed thus far, at least a portion of GaN mesa 120 is n-type down to the junction of substrate 105. As further shown in FIG. 11, a first ILD 1105 has be deposited and planarized with a top surface sacrificial gate stack 810. The sacrificial gate stack 810 is then replaced with a permanent gate stack 140, as shown in FIG. 12, using any known gate replacement techniques and methods. Returning to Fig. 3, methods 301 continue at operation 360 where source/drain contact metallization is deposited onto the n+ doped III-N material grown on the substrate tap and transistor mesas. Interconnect trenches or openings may be etched into the ILD overlying the source and drain regions of the transistor mesa and one or more region of the substrate tap mesa. Contact metallization may then be deposited with any suitable process and planarized with the ILD. In the exemplary embodiments shown in FIG. 13, interconnect structures 155 landing on the source and drain, and interconnect structures 156 landing on the substrate tap have been formed concurrently.

Completing the discussion of FIG. 3, methods 301 end with landing successive interconnect layers on the tap mesas as the field effect transistors are interconnected into an IC. Each successive interconnect layer maintains an antenna connected to the substrate tap and exposed to the BEOL processing performed at operation 365. FIG. 14 shows the device structure 100 following the BEOL processing and is substantially as introduced above in the context of FIG. 1A. FIG. 15 illustrates a system 1500 in which a mobile computing platform 1505 and/or a data server machine 1506 employs an IC including at least one GaN HFET and GaN substrate tap, in accordance with some embodiments. The server machine 1506 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic IC 1550. The mobile computing platform 1505 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1505 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 1510, and a battery 1515.

Whether disposed within the integrated system 1510 illustrated in the expanded view 1520, or as a stand-alone packaged chip within the server machine 1506, the a IC includes at least one III-N HFET adjacent to a substrate tap, for example as describe elsewhere herein. The IC 1550 may be further coupled to a board, a substrate, or an interposer 1560 along with a power management integrated circuit (PMIC). Functionally, PMIC 1530 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 1515 and with an output providing a current supply to other functional modules.

IC 1550, in some embodiments, includes RF (wireless) integrated circuitry (RFIC) further including a wideband RF (wireless) transmitter and/or receiver (TX/RX including a digital baseband and an analog front end module comprising a power amplifier on a transmit path and a low noise amplifier on a receive path). The RFIC includes at least one III-N HFET adjacent to a substrate tap, for example as describe elsewhere herein. The RFIC has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.

FIG. 16 is a functional block diagram of a computing device 1600, arranged in accordance with at least some implementations of the present disclosure. Computing device 1600 may be found inside platform 1505 or server machine 1506, for example. Device 1600 further includes a motherboard 1602 hosting a number of components, such as, but not limited to, a processor 1604 (e.g., an applications processor), which may further incorporate at least one III-N HFET including raised crystalline contact material, in accordance with embodiments of the present invention. Processor 1604 may be physically and/or electrically coupled to motherboard 1602. In some examples, processor 1604 includes an integrated circuit die packaged within the processor 1604. In general, the term "processor" or

"microprocessor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory. In various examples, one or more communication chips 1606 may also be physically and/or electrically coupled to the motherboard 1602. In further implementations, communication chips 1606 may be part of processor 1604. Depending on its applications, computing device 1600 may include other components that may or may not be physically and electrically coupled to motherboard 1602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips 1606 may enable wireless communications for the transfer of data to and from the computing device 1600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips 1606 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 1600 may include a plurality of communication chips 1606. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless

communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

It will be recognized that the invention is not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below. In one or more first embodiments, a semiconductor device structure comprises A semiconductor device structure comprises a transistor on a first mesa, the first mesa comprising a crystalline III-N material and over a first region of a crystalline group IV material. The structure comprises a substrate tap on a second mesa comprising the crystalline III-N material. The second mesa is over a second region of the crystalline group IV material, and the second mesa has a higher n-type impurity dopant concentration than the first mesa. The structure comprises one or more interconnect levels comprising first interconnect structures coupling the transistor to other portions of an integrated circuit, and one or more second interconnect structures coupled to the substrate tap.

In one or more second embodiments, for any of the first embodiments the transistor further comprises a gate stack disposed over the first mesa, and source and drain

semiconductor on the first mesa and separated by the gate stack, the source and drain semiconductor comprising heavily-doped III-N material having a higher n-type impurity dopant concentration than the second mesa. The substrate tap further comprises the heavily doped III-N material on a surface of the second mesa.

In one or more third embodiments, for any of the second embodiments the first interconnect structures comprise separate metal contacts coupled to the source

semiconductor and drain semiconductor, and the second interconnect structures comprise two or more separate metal contacts coupled to the heavily doped III-N material of the substrate tap.

In one or more fourth embodiments, for any of the second or third embodiments the separate metal contacts to the substrate tap have substantially the same dimensions as the separate metal contacts to the source and drain semiconductor.

In one or more fifth embodiments, for any of the first through fourth embodiments the crystalline group IV material comprises silicon and has a resistivity at least 500 ohm-cm, the first and second mesas comprise GaN, and the heavily doped III-N material on the second mesa has the same composition as the source and drain semiconductor.

In one or more sixth embodiments, for any of the fifth embodiments the crystalline group IV material comprises silicon and has a resistivity at least 1000 ohm-cm, the first mesa comprises GaN having an impurity concentration lower than l el6 atoms/cm³, and the second mesa comprises GaN having an impurity concentration of at least l ei 7 atoms/cm³.

In one or more seventh embodiments, for any of the first through the sixth embodiments the heavily-doped III-N material comprises InGaN with an impurity concentration of at least lei 8 atoms/cm³. In one or more eighth embodiments, or any of the first through the seventh embodiments the area of the heavily-doped III-N material on the second mesa is larger than the total area of the source and drain.

In one or more ninth embodiments, for any of the first through the eighth embodiments, the structure comprises a plurality of n-type substrate taps with the corresponding mesas forming a perimeter around the first mesa.

In one or more tenth embodiments, for any of the first through the ninth

embodiments, the transistor comprises a III-N heteroj unction that forms a 2DEG within a portion of the first mesa below the gate stack, and the heavily-doped III-N material comprises n+ doped III-N crystal disposed on c-plane of the first mesa and electrically coupled with the 2DEG.

In one or more eleventh embodiments, for any of the tenth embodiments, the III-N heteroj unction includes a polarization layer comprising A1N, and the polarization layer is absent from the second mesa.

In one or more twelfth embodiments, for any of the first through the eleventh embodiments, the substrate comprises silicon, the mesas are on a (100), (111), or (110) surface of the substrate, and the gate stack comprises a gate electrode disposed on a gate dielectric.

In one or more thirteenth embodiments, a computer platform includes one or more RF transceiver, and an antenna coupled to the RF transceiver, wherein the RF transceiver comprises the IC of any one of the first through twelfth embodiments.

In one or more fourteenth embodiments, for any of the thirteenth embodiments the platforms further comprises a processor communicatively coupled to the RF transceiver, and a battery coupled to at least one of the processor and RF transceiver.

In one or more fifteenth embodiments, a method of forming a semiconductor device, the method comprises epitaxially growing a first mesa over a first region of a crystalline group IV material and a second mesa over a second region of the crystalline group IV material. The first and second mesas comprise a crystalline III-N material. The method comprises doping the second mesa to a higher n-type impurity dopant concentration than the first mesa. The method comprises epitaxially growing heavily-doped III-N material on both the first mesa and the second mesa, the heavily-doped III-N material having a higher n-type impurity dopant concentration than the second mesa. The method comprises forming one or more first interconnect structures coupling at least a source and drain of a transistor formed in the first mesa to other portions of an integrated circuit. The method comprises forming one or more second interconnect structures contacting the heavily-doped III-N material on the second mesa.

In one or more sixteenth embodiments, for any of the fifteenth embodiments doping the second mesa to a higher n-type impurity dopant concentration than the first mesa further comprises planarizing the first and second mesas with a dielectric material, forming a mask over the first mesa, an opening in the mask exposing a top surface of the second mesa, implanting at least one of silicon or germanium impurities through the mask opening and into the second mesa, and activating the impurities.

In one or more seventeenth embodiments, for any of the sixteenth embodiments the method further comprises removing the mask from the first mesa, forming a second mask over the second mesa, the second mask having an opening over the first mesa. The method comprises forming a channel region of the transistor over the first mesa while the second mesa is protected by the second mask. The method comprises removing the second mask from the second mesa before epitaxially growing the heavily-doped III-N material on both the first and second mesas.

In one or more eighteenth embodiments, for any of the seventeenth embodiments the method comprises forming an interlay er dielectric over the second mesa, forming a gate stack over the channel region while the second mesa is protected by the interlay er dielectric, and forming the first and second contact metallization through the interlay er dielectric. In one or more nineteenth embodiments, for any of the fifteenth through seventeenth embodiments the transistor comprises a III-N heteroj unction that forms a 2DEG within a portion of the first mesa below a gate stack. The heavily-doped III-N material comprises n+ doped III-N crystal disposed on c-plane of the first mesa and electrically coupled with the 2DEG. In one or more twentieth embodiments, for any of the fifteenth through eighteenth embodiments crystalline group IV material is silicon having a resistivity of at least 500 ohm- cm. The first mesa comprises GaN having an impurity concentration of less than lei 6 atoms/cm³. The second mesa comprises GaN having an impurity concentration of at least lel7 atoms/cm³. The heavily-doped III-N material is InGaN having an impurity concentration of at least lei 8 atoms/cm³. However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:

1. A semiconductor device structure, comprising:

a transistor on a first mesa, the first mesa comprising a crystalline III-N material and over a first region of a crystalline group IV material;

a substrate tap on a second mesa comprising the crystalline III-N material, wherein the second mesa is over a second region of the crystalline group IV material, and the second mesa has a higher n-type impurity dopant concentration than the first mesa; and

one or more interconnect levels comprising first interconnect structures coupling the transistor to other portions of an integrated circuit, and one or more second interconnect structures coupled to the substrate tap.

2. The semiconductor device structure of claim 1, wherein:

the transistor further comprises:

a gate stack disposed over the first mesa; and

source and drain semiconductor on the first mesa and separated by the gate stack, the source and drain semiconductor comprising heavily-doped III-N material having a higher n-type impurity dopant concentration than the second mesa; the substrate tap further comprises the heavily doped III-N material on a surface of the second mesa.

3. The semiconductor device structure of claim 2, wherein:

the first interconnect structures comprise separate metal contacts coupled to the source semiconductor and drain semiconductor; and

the second interconnect structures comprise two or more separate metal contacts coupled to the heavily doped III-N material of the substrate tap.

4. The semiconductor device structure of claim 3, wherein the separate metal contacts to the substrate tap have substantially the same dimensions as the separate metal contacts to the source and drain semiconductor.

5. The semiconductor device structure of claim 1, wherein:

the crystalline group IV material comprises silicon and has a resistivity at least 500 ohm-cm; the first and second mesas comprise GaN; and

the heavily doped III-N material on the second mesa has the same composition as the source and drain semiconductor.

6. The semiconductor device structure of claim 5, wherein:

the crystalline group IV material comprises silicon and has a resistivity at least 1000 ohm- cm;

the first mesa comprises GaN having an impurity concentration lower than lei 6 atoms/cm³; and

the second mesa comprises GaN having an impurity concentration of at least lel7

atoms/cm³.

7. The semiconductor device structure of claim 6, wherein the heavily-doped III-N material comprises InGaN with an impurity concentration of at least lei 8 atoms/cm³.

8. The semiconductor device structure of claim 2, wherein the area of the heavily-doped III- N material on the second mesa is larger than the area of the source added to the area of the drain.

9. The semiconductor device structure of claim 1, further comprising a plurality of n-type substrate taps with the corresponding mesas forming a perimeter around the first mesa.

10. The semiconductor device structure of any one of claims 1-9, wherein:

the transistor comprises a III-N heteroj unction that forms a 2DEG within a portion of the first mesa below the gate stack; and

the heavily-doped III-N material comprises n+ doped III-N crystal disposed on c-plane of the first mesa and electrically coupled with the 2DEG.

11. The semiconductor device structure of claim 10, wherein:

the III-N heteroj unction includes a polarization layer comprising A1N; and

the polarization layer is absent from the second mesa.

12. The semiconductor device structure of any one of claims 1 -9, wherein: the substrate comprises silicon;

the mesas are on a (100), (1 11), or (110) surface of the substrate; and

the gate stack comprises a gate electrode disposed on a gate dielectric.

13. A computer platform including:

one or more RF transceiver; and

an antenna coupled to the RF transceiver, wherein the RF transceiver comprises the

semiconductor device of any one of claims 1-12.

14. The computer platform of claim 13, comprising:

a processor communicatively coupled to the RF transceiver; and

a battery coupled to at least one of the processor and RF transceiver.

15. A method of forming a semiconductor device, the method comprising:

epitaxially growing a first mesa over a first region of a crystalline group IV material and a second mesa over a second region of the crystalline group IV material; wherein the first and second mesas comprise a crystalline III-N material;

doping the second mesa to a higher n-type impurity dopant concentration than the first mesa; epitaxially growing heavily-doped III-N material on both the first mesa and the second

mesa, the heavily-doped III-N material having a higher n-type impurity dopant concentration than the second mesa;

forming one or more first interconnect structures coupling at least a source and drain of a transistor formed in the first mesa to other portions of an integrated circuit; and forming one or more second interconnect structures contacting the heavily-doped III-N

material on the second mesa.

16. The method of claim 15, wherein doping the second mesa to a higher n-type impurity dopant concentration than the first mesa further comprises:

planarizing the first and second mesas with a dielectric material;

forming a mask over the first mesa, an opening in the mask exposing a top surface of the second mesa; implanting at least one of silicon or germanium impurities through the mask opening and into the second mesa; and

activating the impurities.

17. The method of claim 16, further comprising:

removing the mask from the first mesa;

forming a second mask over the second mesa, the second mask having an opening over the first mesa;

forming a channel region of the transistor over the first mesa while the second mesa is

protected by the second mask; and

removing the second mask from the second mesa before epitaxially growing the heavily- doped III-N material on both the first and second mesas.

18. The method of claim 17, further comprising:

forming an interlay er dielectric over the second mesa;

forming a gate stack over the channel region while the second mesa is protected by the

interlayer dielectric; and

forming the first and second interconnect structures through the interlayer dielectric.

19. The method of any one of claims 15-18, wherein:

the transistor comprises a III-N heteroj unction that forms a 2DEG within a portion of the first mesa below a gate stack;

20. The method of any one of claims 15-18, wherein:

the crystalline group IV material is silicon having a resistivity of at least 500 ohm-cm;

the first mesa comprises GaN having an impurity concentration of less than l ei 6 atoms/cm³; the second mesa comprises GaN having an impurity concentration of at least l el7

atoms/cm³; and

the heavily-doped III-N material is InGaN having an impurity concentration of at least l ei 8 atoms/cm³.