CN114530417A - Manufacturing method of semiconductor structure - Google Patents
Manufacturing method of semiconductor structure Download PDFInfo
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- CN114530417A CN114530417A CN202210433054.1A CN202210433054A CN114530417A CN 114530417 A CN114530417 A CN 114530417A CN 202210433054 A CN202210433054 A CN 202210433054A CN 114530417 A CN114530417 A CN 114530417A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 102
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 38
- 230000008569 process Effects 0.000 claims description 15
- 239000000945 filler Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
The invention provides a manufacturing method of a semiconductor structure. In the manufacturing method of the semiconductor structure, a plurality of fin parts distributed at intervals are formed on a provided substrate, and the fin parts comprise a first fin part positioned in a first element region and a second fin part positioned in a second element region; then forming a filling material layer, wherein the filling material layer fills the grooves among the plurality of fin parts; and etching to remove the filling material layer with partial thickness, wherein the remaining filling material layer is used as an isolation material layer, the thicknesses of the isolation material layers on the first element region and the second element region are different, and the exposed height of the first fin part from the upper surface of the isolation material layer is not equal to the exposed height of the second fin part from the upper surface of the isolation material layer, so that fin parts with different exposed heights can be formed on the same substrate to form FinFETs with different characteristics, the goal of coexistence of different FinFETs is realized, diversification of semiconductor structure functions is realized, and the use area of a semiconductor structure is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
With the continuous development of semiconductor technology, the conventional planar device has not been able to meet the demand of people for high performance devices. A Fin-Field-Effect Transistor (FinFET) is a three-dimensional device that includes a Fin vertically formed on a substrate and a stacked gate intersecting the Fin. This design can greatly improve circuit control and reduce leakage current (leakage), and can also greatly shorten the gate length of the transistor.
Currently, the exposed height of all fins on the same substrate is generally the same in FinFET semiconductor fabrication. Although increasing the exposed height of the fin portion helps to improve the characteristics of the logic device (logic device), it increases the parasitic capacitance of the device. According to the cut-off frequency
It is known that, when the parasitic capacitance C of the FinFET increases, the cutoff frequency fc decreases, and thus increasing the exposed height of the fin portion affects the performance of some finfets in which the cutoff frequency is expected to be large (i.e., larger and better). Therefore, the semiconductor structure formed in the current FinFET semiconductor process cannot satisfy the requirement of function diversification.
Disclosure of Invention
One of the objectives of the present invention is to provide a method for fabricating a semiconductor structure, which can realize diversification of functions of the semiconductor structure.
In order to achieve the above object, the present invention provides a method for fabricating a semiconductor structure. The manufacturing method of the semiconductor structure comprises the following steps:
providing a substrate, wherein the substrate comprises a first element region and a second element region, a plurality of fin parts distributed at intervals are formed on the substrate, the plurality of fin parts comprise a first fin part and a second fin part, the first fin part is located in the first element region, and the second fin part is located in the second element region;
forming a filling material layer, wherein the filling material layer is filled among the plurality of fins and fills the grooves among the plurality of fins;
etching to remove the filling material layer with partial thickness, wherein the rest filling material layer is used as an isolation material layer, and the upper parts of the plurality of fin parts are exposed out of the upper surface of the isolation material layer; the thicknesses of the isolation material layers on the first element region and the second element region are different, the height of the first fin portion exposed from the upper surface of the isolation material layer is a first height, the height of the second fin portion exposed from the upper surface of the isolation material layer is a second height, and the first height is not equal to the second height.
Optionally, the method for forming the first fin portion in the first element region and the second fin portion in the second element region includes:
forming a first patterned mask layer on a substrate, and performing a first etching process to etch the substrate by using the first mask layer as a mask to form the first fin portion in the first element region;
removing the first mask layer, forming a patterned second mask layer on the substrate, and performing a second etching process to etch the substrate by using the second mask layer as a mask so as to form the second fin part in the second element region;
the first etching process and the second etching process have different etching conditions, and the first fin portion and the second fin portion have different cross-sectional shapes.
Optionally, the method for removing a part of the thickness of the filling material layer by etching includes:
forming a third mask layer that exposes the fill material layer on the first element region and covers the second element region;
etching and removing part of the thickness of the filling material layer on the first element region by taking the third mask layer as a mask so as to expose part of the height of the first fin part, wherein the exposed height of the first fin part is a first height;
removing the third mask layer to form a fourth mask layer, wherein the fourth mask layer exposes the filling material layer on the second element region and covers the first element region;
and etching and removing part of the thickness of the filling material layer on the second element region by taking the fourth mask layer as a mask so as to expose part of the height of the second fin part, wherein the exposed height of the second fin part is a second height.
Optionally, the substrate includes a third element region, the plurality of fins include a third fin located in the third element region, a thickness of an isolation material layer of the third element region is different from thicknesses of isolation material layers of the first element region and the second element region, a height of the third fin exposed from an upper surface of the isolation material layer is a third height, and the third height is not equal to the first height and not equal to the second height.
Optionally, the first element area is a low-speed logic element area, and the first height is 40nm to 50 nm; the second element area is a high-speed logic element area, and the second height is 50 nm-65 nm; the third element area is a radio frequency element area, and the third height is 30 nm-40 nm.
Optionally, the working voltage of the first element region is 1.1V-1.8V; the working voltage of the second element area is 0.6-1V; the working voltage of the third element area is 0.9-1.2V, and the working frequency of the third element area is 60-100 Hz.
Optionally, the first fin portion is wide at the bottom and narrow at the top; the second fin part is in a shape with the same width from top to bottom; the third fin portion is wide in upper portion and narrow in lower portion.
Optionally, the heights of the first fin portion and the second fin portion are the same.
In the manufacturing method of the semiconductor structure, the provided substrate comprises a first element region and a second element region, and a plurality of fin parts are formed at intervals, wherein the plurality of fin parts comprise a first fin part and a second fin part, the first fin part is positioned in the first element region, and the second fin part is positioned in the second element region; then, forming a filling material layer which is filled among the plurality of fin parts and fills the grooves among the plurality of fin parts; and then, etching to remove the filling material layer with partial thickness, wherein the rest filling material layer is used as an isolation material layer, the upper parts of the multiple fin parts are exposed out of the upper surface of the isolation material layer, the thicknesses of the isolation material layer on the first element region and the second element region are different, and the exposed height of the first fin part from the upper surface of the isolation material layer is not equal to the exposed height of the second fin part from the upper surface of the isolation material layer, so that fin parts with different exposed heights can be formed on the same substrate to form FinFETs with different characteristics, the coexistence goal of different FinFETs is realized, further the diversification of the functions of the semiconductor structure is realized, and the use area of the semiconductor structure is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention.
Fig. 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Fig. 3 to 9 are schematic views of a step structure of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Description of reference numerals: 10-a substrate; 10 a-a first element region; 10 b-a second component area; 10 c-a third element region; 11-a first fin portion; 12-a second fin portion; 13-a third fin portion; 14-a layer of isolating material; 14 a-a layer of filler material; 15-a first mask layer; 16-a second mask layer; 17-a third mask layer; 18-a fourth mask layer; 19-a fifth mask layer; 20-sixth mask layer.
Detailed Description
The semiconductor structure and the method for fabricating the same according to the present invention are further described in detail with reference to the drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or imply that there is a number of the indicated technical features. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
The invention provides a semiconductor structure for realizing diversification of functions of the semiconductor structure. Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, the semiconductor structure includes a substrate 10 and a layer of spacer material 14.
The substrate 10 includes a first element region 10a and a second element region 10b, a plurality of fin portions distributed at intervals are formed on the substrate 10, the plurality of fin portions include a first fin portion 11 and a second fin portion 12, the first fin portion 11 is located in the first element region 10a, and the second fin portion 12 is located in the second element region 10 b.
The substrate 10 may be a silicon substrate. In other embodiments, the substrate 10 may also be a semiconductor substrate such as a germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the heights of the plurality of fin portions may be the same, and the bottom surfaces of the plurality of fin portions are located in the same plane, that is, the starting points of the plurality of fin portions are located at the same height. As shown in fig. 1, the heights of the first fin portion 11 and the second fin portion 12 are both d. But not limited thereto, in other embodiments, the protrusion heights of the plurality of fins may be different.
The isolation material layer 14 is filled between the plurality of fins, specifically, the isolation material layer 14 is filled at the bottoms of two adjacent fins, and the upper portions of the plurality of fins are exposed from the upper surface of the isolation material layer 14. The upper surface of the spacer material layer 14 is stepped, that is, the thickness of the spacer material layer 14 on the first device region 10a and the second device region 10b is different. The material of the isolation material layer 14 may include, but is not limited to, silicon oxide and/or silicon nitride.
As shown in fig. 1, the first fin 11 is exposed from the upper surface of the isolation material layer 14 to a first height d1, the second fin 12 is exposed from the upper surface of the isolation material layer 14 to a second height d2, and the first height d1 is not equal to the second height d 2. In this embodiment, by forming the step-shaped isolation material layer 14, the thickness of the isolation material layer on the first device region 10a is not equal to the thickness of the isolation material layer on the second device region 10b, so that the first fin 11 and the second fin 12 with different exposed heights are obtained, which is beneficial to realizing diversification of functions of the semiconductor structure.
As shown in fig. 1, the substrate 10 may include a third element region 10c, the plurality of fins may include third fins 13 located in the third element region 10c, a thickness of an isolation material layer on the third element region 10c is different from a thickness of an isolation material layer on each of the first element region 10a and the second element region 10b, a height of the third fins 13 exposed from an upper surface of the isolation material layer 14 is a third height d3, and the third height d3 is not equal to the first height d1 and not equal to the second height d 2.
In this embodiment, the cross-sectional shapes of the first fin portion 11, the second fin portion 12, and the third fin portion 13 may be different, so that different characteristic requirements of different finfets can be met, diversification of functions of a semiconductor structure is facilitated, and performance of the semiconductor structure is improved. It should be noted that the cross sections of the fins described in the present application are all cross sections parallel to the thickness direction of the substrate 10, and the thickness direction of the substrate 10 is, for example, the vertical direction in fig. 1.
As an example, the first element region 10a is a low-speed logic element region for forming a low-speed logic device, and the low-speed logic device includes a first fin portion 11; the second element region 10b is a high-speed logic element region for forming a high-speed logic device, and the high-speed logic device includes the second fin portion 12, wherein the operation speed of the high-speed logic device is higher than that of the low-speed logic device, that is, the low-speed logic device is relative to the high-speed logic device; the third element region 10c is a radio frequency element region, and is configured to form a radio frequency device, where the radio frequency device includes the third fin portion 13. That is to say, the semiconductor structure of the embodiment can enable a low-speed logic device, a high-speed logic device and a radio frequency device to coexist, thereby realizing diversification of functions of the semiconductor structure.
Specifically, the operating voltage of the first device region 10a may be 1.1V to 1.8V, that is, the operating voltage (threshold voltage) of the low-speed logic device may be 1.1V to 1.8V. The working voltage of the second element area 10b is 0.6V-1V, namely the working voltage of the high-speed logic device can be 0.6V-1V. The working voltage of the third element area 10c can be 0.9V-1.2V, and the working frequency of the third element area is 60 Hz-100 Hz, namely the working voltage of the radio frequency device is 0.9V-1.2V, and the working frequency is 60 Hz-100 Hz.
In order to meet different characteristic requirements of different finfets on a semiconductor structure, that is, different characteristic requirements of a low-speed logic device, a high-speed logic device and a radio frequency device, the first height d1 may be 40nm to 50nm, the second height d2 may be 50nm to 65nm, and the third height d3 may be 30nm to 40 nm.
In order to meet different characteristic requirements of different finfets on a semiconductor structure, further, as shown in fig. 1, the first fin portion 11 has a shape with a wide bottom and a narrow top, for example, the cross-sectional shape of the first fin portion 11 is a regular trapezoid; the second fin portion 12 has a shape with an equal width from top to bottom, for example, the cross section of the second fin portion 12 is rectangular; the third fin portion 13 is shaped to be wider at the top and narrower at the bottom, for example, the third fin portion 13 is an inverted trapezoid.
In the semiconductor structure provided in this embodiment, the substrate 10 includes a first element region 10a and a second element region 10b, and a plurality of fin portions are formed at intervals, where the plurality of fin portions include a first fin portion 11 and a second fin portion 12, the first fin portion 11 is located in the first element region 10a, and the second fin portion 12 is located in the second element region 10 b; the isolation material layer 14 is filled between the plurality of fins, wherein the thicknesses of the isolation material layer 14 on the first element region 10a and the second element region 10b are different, and the height (i.e., d 1) of the first fin 11 exposed from the upper surface of the isolation material layer 14 is not equal to the height (i.e., d 2) of the second fin 12 exposed from the upper surface of the isolation material layer 14, so that fins with different exposed heights can be formed on the same substrate 10 to form finfets with different characteristics, thereby achieving the goal of different concurrent finfets and realizing the diversification of the functions of the semiconductor structure.
In an existing chip, only one FinFET is usually formed on a chip, and in order to meet functional requirements, for example, three chips respectively including a low-speed logic device, a high-speed logic device, and a radio frequency device need to be provided, so that an area occupied by the chip is large. The semiconductor structure of the embodiment can enable different finfets to coexist, and is beneficial to reducing the use area (occupied area) of the semiconductor structure.
The embodiment also provides a manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure can be used for manufacturing the semiconductor structure.
Fig. 2 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the invention. Fig. 3 to 9 are schematic views of a step structure of a method for fabricating a semiconductor structure according to an embodiment of the invention. Referring to fig. 1 to 9, the method for manufacturing the semiconductor structure includes:
s1, providing a substrate 10, where the substrate 10 includes a first element region 10a and a second element region 10b, and a plurality of fin portions are formed on the substrate 10 at intervals, where the fin portions include a first fin portion 11 and a second fin portion 12, the first fin portion 11 is located in the first element region 10a, and the second fin portion 12 is located in the second element region 10 b;
s2, forming a filling material layer 14a, where the filling material layer 14a fills the plurality of fins and fills the grooves between the plurality of fins;
s3, etching to remove a part of the thickness of the filling material layer 14a, using the remaining filling material layer as an isolation material layer 14, and exposing the upper portions of the plurality of fins from the upper surface of the isolation material layer 14; the thicknesses of the isolation material layer 14 on the first element region 10a and the second element region 10b are different, the height of the first fin portion 11 exposed from the upper surface of the isolation material layer 14 is a first height d1, the height of the second fin portion 12 exposed from the upper surface of the isolation material layer 14 is a second height d2, and the first height d1 is not equal to the second height d 2.
In this embodiment, in step S1, the method of forming the first fin 11 in the first element region 10a and forming the second fin 12 in the second element region 10b may include: as shown in fig. 3, a patterned first mask layer 15 is formed on a substrate 10, and a first etching process is performed to etch the substrate 10 by using the first mask layer 15 as a mask, so as to form the first fin portion 11 in the first element region 10 a; as shown in fig. 4, the first mask layer 15 is removed, a patterned second mask layer 16 is formed on the substrate 10, and a second etching process is performed to etch the substrate 10 by using the second mask layer 16 as a mask, so as to form the second fin portion 12 in the second element region 10 b.
The etching conditions of the first etching process and the second etching process may be different, so that the cross-sectional shapes of the first fin portion 11 and the second fin portion 12 may be different. For example, by adjusting the etching gas (including Cl) during the first etching process and the second etching process2HBr and CF4) The first fin portion 11 and the second fin portion 12 may be formed to have different cross-sectional shapes.
As shown in fig. 1, the substrate 10 may further include a third-element region 10c, and the plurality of fins may include a third fin 13 located in the third-element region 10 c. The third fin 13 may be formed after forming the second fin 12 and before forming a layer of filler material.
Specifically, the method for forming the third fin portion 13 in the third element region 10c of the substrate 10 may include: as shown in fig. 5, the second mask layer 16 is removed, a fifth mask layer 19 is formed, and a third etching process is performed to etch the substrate 10 by using the fifth mask layer 19 as a mask, so as to form a third fin 13 in the third element region 10 c. The cross-sectional shape of the third fin 13 may be different from the cross-sectional shapes of the first and second fins 11 and 12. But not limited thereto, the cross-sectional shape of the third fin 13 may be the same as the cross-sectional shape of one of the first and second fins 11 and 12. As an example, the first fin portion 11 has a shape that is wide at the bottom and narrow at the top, the second fin portion 12 has a shape that is equal in width at the top and narrow at the bottom, and the third fin portion 13 has a shape that is wide at the top and narrow at the bottom.
Note that, when the substrate 10 includes the third element region 10c, the first mask layer 15 and the second mask layer 16 also cover the third element region 10 c.
In this embodiment, in step S2, referring to fig. 6, the method for forming the filling material layer 14a may include: forming an original filling material layer, wherein the original filling material layer covers the substrate 10 and the plurality of fin portions, and fills the groove between every two adjacent fin portions; and performing planarization treatment on the original filling material layer to form the filling material layer 14a, wherein the upper surface of the filling material layer 14a can be flush with the top surfaces of the plurality of fins. Note that, here, "flush" means that the difference in height between the upper surface of the filler material layer 14a and the upper surface of the fin portion is within a small set range.
In this embodiment, the method for removing the filling material layer 14a with a partial thickness by etching may include: forming a third mask layer 17, as shown in fig. 7, the third mask layer 17 exposing the filler material layer 14a on the first element region 10a and covering the second element region 10b and the third element region 10 c; etching and removing a part of the thickness of the filling material layer 14a in the first element region 10a by using the third mask layer 17 as a mask to expose a part of the height of the first fin portion 11, where the exposed height of the first fin portion 11 is a first height d 1; as shown in fig. 8, the third mask layer 17 is removed, and a fourth mask layer 18 is formed, wherein the fourth mask layer 18 exposes the filling material layer on the second element region 10b and covers the first element region 10a and the third element region 10 c; etching and removing a part of the thickness of the filling material layer 14a on the second element region 10b by using the fourth mask layer 18 as a mask to expose a part of the height of the second fin portion 12, where the exposed height of the second fin portion 12 is a second height d 2; as shown in fig. 9, the fourth mask layer 18 is removed, a sixth mask layer 20 is formed, the sixth mask layer 20 exposes the filling material layer on the third device region 10c and covers the first device region 10a and the second device region 10b, a partial thickness of the filling material layer on the third device region 10c is removed by etching using the sixth mask layer 20 as a mask, so as to expose a partial height of the third fin 13, the exposed height of the third fin 13 is a third height d3, the third height d3 is not equal to the first height d1 but not equal to the second height d2, and the remaining filling material layer serves as the isolation material layer 14.
As shown in fig. 1, the thickness of the isolation material layer 14 on the third element region 10c is different from the thickness of the isolation material layer 14 on the first element region 10a and the second element region 10b, the height of the third fin 13 exposed from the upper surface of the isolation material layer 14 is a third height d3, and the third height d3 is not equal to the first height d1 and not equal to the second height d 2. The heights of the first fin 11, the second fin 12 and the third fin 13 may be equal, for example, d.
In this embodiment, the first element region 10a is a low-speed logic element region, and is used for forming a low-speed logic device; the second element area 10b is a high-speed logic element area, and is used for forming a high-speed logic device; the third element region 10c is a radio frequency element region for forming a radio frequency device. The operating voltage of the first device region 10a may be 1.1V to 1.8V, that is, the operating voltage (threshold voltage) of the low-speed logic device may be 1.1V to 1.8V. The working voltage of the second element area 10b is 0.6V-1V, namely the working voltage of the high-speed logic device can be 0.6V-1V. The working voltage of the third element area 10c can be 0.9V-1.2V, and the working frequency of the third element area is 60 Hz-100 Hz, namely the working voltage of the radio frequency device is 0.9V-1.2V, and the working frequency is 60 Hz-100 Hz.
In order to meet different characteristic requirements of different finfets on a semiconductor structure, that is, different characteristic requirements of a low-speed logic device, a high-speed logic device and a radio frequency device, the first height d1 may be 40nm to 50nm, the second height d2 may be 50nm to 65nm, and the third height d3 may be 30nm to 40 nm.
It should be noted that, the present specification is described in a progressive manner, and the manufacturing method of the semiconductor structure described later mainly illustrates the differences from the semiconductor structure described earlier, and the same and similar parts may be referred to each other.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (8)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first element region and a second element region, a plurality of fin parts distributed at intervals are formed on the substrate, the plurality of fin parts comprise a first fin part and a second fin part, the first fin part is located in the first element region, and the second fin part is located in the second element region;
forming a filling material layer, wherein the filling material layer is filled among the plurality of fins and fills the grooves among the plurality of fins;
etching to remove the filling material layer with partial thickness, wherein the rest filling material layer is used as an isolation material layer, and the upper parts of the plurality of fin parts are exposed out of the upper surface of the isolation material layer; the thicknesses of the isolation material layers on the first element region and the second element region are different, the height of the first fin portion exposed from the upper surface of the isolation material layer is a first height, the height of the second fin portion exposed from the upper surface of the isolation material layer is a second height, and the first height is not equal to the second height.
2. The method of fabricating a semiconductor structure of claim 1, wherein the method of forming the first fin in the first element region and the second fin in the second element region comprises:
forming a first patterned mask layer on a substrate, and performing a first etching process to etch the substrate by using the first mask layer as a mask to form the first fin portion in the first element region;
removing the first mask layer, forming a patterned second mask layer on the substrate, and performing a second etching process to etch the substrate by using the second mask layer as a mask so as to form the second fin part in the second element region;
the first etching process and the second etching process have different etching conditions, and the first fin portion and the second fin portion have different cross-sectional shapes.
3. The method of fabricating a semiconductor structure according to claim 1, wherein the step of removing a portion of the thickness of the layer of fill material by etching comprises:
forming a third mask layer that exposes the fill material layer on the first element region and covers the second element region;
etching and removing part of the thickness of the filling material layer on the first element region by taking the third mask layer as a mask so as to expose part of the height of the first fin part, wherein the exposed height of the first fin part is a first height;
removing the third mask layer to form a fourth mask layer, wherein the fourth mask layer exposes the filling material layer on the second element region and covers the first element region;
and etching and removing part of the thickness of the filling material layer on the second element region by taking the fourth mask layer as a mask so as to expose part of the height of the second fin part, wherein the exposed height of the second fin part is a second height.
4. The method of claim 1, wherein the substrate comprises a third element region, wherein the plurality of fins comprises a third fin portion in the third element region, wherein a thickness of the isolation material layer in the third element region is different from a thickness of the isolation material layer in the first element region and a thickness of the isolation material layer in the second element region, wherein a height of the third fin portion exposed from an upper surface of the isolation material layer is a third height, and wherein the third height is not equal to the first height and not equal to the second height.
5. The method of claim 4, wherein the first device region is a low-speed logic device region, and the first height is 40nm to 50 nm; the second element area is a high-speed logic element area, and the second height is 50 nm-65 nm; the third element area is a radio frequency element area, and the third height is 30 nm-40 nm.
6. The method according to claim 4, wherein the first device region has an operating voltage of 1.1V to 1.8V; the working voltage of the second element area is 0.6-1V; the working voltage of the third element area is 0.9-1.2V, and the working frequency of the third element area is 60-100 Hz.
7. The method of claim 4, wherein the first fin portion has a shape with a wider bottom and a narrower top; the second fin part is in a shape with the same width from top to bottom; the third fin portion is wide in upper portion and narrow in lower portion.
8. The method of claim 1, wherein the first fin and the second fin have the same height.
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