CN113782441A - FinFET manufacturing method - Google Patents

FinFET manufacturing method Download PDF

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Publication number
CN113782441A
CN113782441A CN202111010817.3A CN202111010817A CN113782441A CN 113782441 A CN113782441 A CN 113782441A CN 202111010817 A CN202111010817 A CN 202111010817A CN 113782441 A CN113782441 A CN 113782441A
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layer
hard mask
fin body
finfet
mask layer
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CN113782441B (en
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周真真
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a manufacturing method of a FinFET, which comprises the following steps: step one, carrying out graphical etching on a semiconductor substrate to form a first fin body. And secondly, filling an isolation dielectric layer in the interval area of the first fin body. And step three, etching the first fin body by taking the isolation medium layer as a self-alignment condition to form a fin body groove. And step four, extending a second semiconductor material layer in the fin body groove and forming a second fin body, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate. And step five, etching the isolation medium layer to expose the top part of the second fin body. The invention can improve the mobility of channel carriers of the device, thereby improving the performance of the device.

Description

FinFET manufacturing method
Technical Field
The present invention relates to the Field of semiconductor integrated circuit fabrication, and more particularly, to a method for fabricating a Fin Field Effect Transistor (FinFET).
Background
A semiconductor device in a semiconductor integrated circuit is in a planar structure, the semiconductor device is directly formed on the surface of bulk silicon and comprises a gate oxide layer formed on the surface of the bulk silicon and a grid structure of a polysilicon gate, a source region and a drain region are formed in the bulk silicon on two sides of the grid structure in a self-aligning mode, an area between the source region and the drain region and covered by the grid structure is a channel region, and when the semiconductor device is conducted, a conducting channel for connecting the source region and the drain region is formed on the surface of the channel region. As the size of the device is reduced in an equal proportion, the channel length is reduced, and in order to reduce the short channel effect, the doping concentration of the channel region needs to be increased, and when the doping concentration of the channel region is increased, the mobility of carriers in the conductive channel is reduced, which finally affects the performance of the device.
In order to overcome the above defects of the planar device, two new device structures are developed, which are an ultra-thin-body silicon-on-insulator (UTB SOI) device and a FinFET, respectively, on an insulating layer of an ultra-thin body region, where the UTB SOI device and the FinFET have good electrical characteristics, so that the doping concentrations of channel regions of the two devices can be reduced and a short-channel effect can be prevented, and the mobility of carriers can be improved after the doping concentration of the channel region is reduced, thereby finally improving the performance of the device.
As the evolution of moore's law continues, the improvement in device performance never ends, and therefore we need to find higher mobility channel materials and fabrication processes that are compatible with finfets.
Disclosure of Invention
The invention aims to provide a manufacturing method of a FinFET, which can improve the mobility of channel carriers of a device, thereby improving the performance of the device.
In order to solve the above technical problem, the method for manufacturing a FinFET provided in the present invention includes the following steps:
step one, providing a semiconductor substrate, and carrying out graphical etching on the semiconductor substrate to form a first fin body.
And secondly, filling an isolation dielectric layer in the interval area of the first fin body.
And step three, etching the first fin body by taking the isolation medium layer as a self-alignment condition to form a fin body groove, wherein the bottom surface of the fin body groove is higher than the bottom surface of the isolation medium layer.
And step four, extending a second semiconductor material layer in the fin body groove and forming a second fin body, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate.
And fifthly, etching the isolation medium layer to expose the top part of the second fin body, wherein the top part of the second fin body is used for forming a channel region of the FinFET so as to improve the electrical performance of the FinFET.
In a further improvement, the material of the semiconductor substrate is silicon.
In a further improvement, the material of the second semiconductor material layer comprises silicon germanium or germanium.
In a further improvement, the step one comprises the following sub-steps:
step 11, forming a first hard mask layer on the surface of the semiconductor substrate;
step 12, carrying out photoetching definition and etching to pattern the first hard mask layer;
and step 13, etching the semiconductor substrate by taking the patterned first hard mask layer as a mask to form the first fin body.
The further improvement is that the step two comprises the following steps:
step 21, performing a deposition process of the isolation dielectric layer, wherein the deposited isolation dielectric layer completely fills the spacing region between the first fin bodies and extends to the surface of the first hard mask layer on the top of the first fin body;
and step 22, performing a chemical mechanical polishing process with the first hard mask layer as a stop layer to remove the isolation dielectric layer on the surface of the first hard mask layer on the top of the first fin body and to level the top surface of the isolation dielectric layer in the spacing area between the first fin bodies with the top surface of the first hard mask layer.
The further improvement is that the third step comprises the following sub-steps:
step 31, etching the isolation medium layer by taking the first hard mask layer as a self-alignment condition to enable the top surface of the isolation medium layer to be positioned between the top surface of the first fin body and the top surface of the first hard mask layer;
step 32, forming a second hard mask layer on the top surface of the isolation dielectric layer;
and step 33, removing the first hard mask layer by taking the second hard mask layer as a mask, and etching the exposed first fin body to form the fin body groove.
In a further improvement, the material of the isolation dielectric layer comprises an oxide layer.
In a further improvement, in step 21, a deposition process of the isolation dielectric layer adopts flow type chemical vapor deposition (FCVD).
In a further improvement, the material of the first hard mask layer comprises silicon nitride.
In a further refinement, the material of the second hard mask layer comprises silicon carbide.
The further improvement is that the etching depth of the isolation medium layer in the step 31 is 10 nm-20 nm.
In a further improvement, in step 32, the second hard mask layer is formed by a deposition process and a chemical mechanical polishing process in which the first hard mask layer is a stop layer.
The further improvement is that the step four comprises the following sub-steps:
step 41, performing an epitaxial growth process of the second semiconductor material layer, wherein the second semiconductor material layer grows upwards from the bottom surface of the fin body trench, and after the epitaxial growth is completed, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer and the second semiconductor material layer also extends transversely to the surface of the second hard mask layer;
and 42, carrying out a chemical mechanical polishing process to enable the top surface of the second semiconductor material layer to be flush with the surface of the second hard mask layer.
In a further improvement, step 42 is followed by:
43, removing the second hard mask layer with a part of thickness to expose the top angle of the second fin body;
step 44, rounding the top angle of the second fin body, wherein the rounding process comprises the following steps:
oxidizing the exposed second fin body to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
and step 45, completely removing the residual second hard mask layer.
In a further improvement, after the fifth step, the first gate oxide layer is formed by the following steps:
depositing an amorphous silicon cap layer by adopting an ALD (atomic layer deposition) process;
and seventhly, oxidizing the amorphous silicon cap layer to form the first gate oxide layer.
In a further improvement, the first gate oxide layer is used as a gate oxide layer of an input-output FinFET.
According to the method, after the first fin body is formed by carrying out graphical etching on the semiconductor substrate, the first fin body is not adopted to form the channel region of the FinFET, the isolation medium layer is filled in the interval region between the first fin bodies, the isolation medium layer is used as a self-alignment condition to etch the first fin body to form the fin body groove, then the second fin body formed by the second semiconductor material layer with higher carrier mobility is filled in the fin body groove, and after the isolation medium layer is etched, the top part of the second fin body can be used as the channel region of the FinFET.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a flow chart of a method of fabricating a FinFET in accordance with an embodiment of the present invention;
fig. 2A-2L are schematic views of device structures in various steps of a method according to an embodiment of the invention.
Detailed Description
Fig. 1 is a flow chart illustrating a method of manufacturing a FinFET in accordance with an embodiment of the present invention; fig. 2A to 2L are schematic diagrams of device structures in the steps of the method according to the embodiment of the present invention; the manufacturing method of the FinFET comprises the following steps:
step one, as shown in fig. 2A, a semiconductor substrate 101a is provided, and the semiconductor substrate 101a is subjected to a patterned etching to form a first fin body 101.
In the method of the embodiment of the invention, the first step comprises the following sub-steps:
step 11, forming a first hard mask layer 201 on the surface of the semiconductor substrate 101 a.
The material of the semiconductor substrate 101a is silicon.
The material of the first hard mask layer 201 includes silicon nitride.
Step 12, performing photolithography definition and etching to pattern the first hard mask layer 201;
and step 13, etching the semiconductor substrate 101a by using the patterned first hard mask layer 201 as a mask to form the first fin body 101.
Step two, as shown in fig. 2B, an isolation dielectric layer 102 is filled in the spaced region of the first fin 101.
In the method of the embodiment of the invention, the second step comprises the following sub-steps:
step 21, performing a deposition process of the isolation dielectric layer 102, wherein the deposited isolation dielectric layer 102 completely fills the space region between the first fin bodies 101 and extends to the surface of the first hard mask layer 201 on the top of the first fin body 101.
The material of the isolation dielectric layer 102 includes an oxide layer.
The deposition process of the isolation dielectric layer 102 adopts FCVD.
Step 22, performing a chemical mechanical polishing process using the first hard mask layer 201 as a stop layer to remove the isolation dielectric layer 102 on the surface of the first hard mask layer 201 on the top of the first fin 101 and to level the top surface of the isolation dielectric layer 102 in the spaced area between the first fins 101 with the top surface of the first hard mask layer 201.
And thirdly, etching the first fin body 101 by taking the isolation medium layer 102 as a self-alignment condition to form a fin body groove 103, wherein the bottom surface of the fin body groove 103 is higher than the bottom surface of the isolation medium layer 102.
In the method of the embodiment of the invention, the third step comprises the following sub-steps:
step 31, as shown in fig. 2C, the isolation dielectric layer 102 is etched under the self-aligned condition of the first hard mask layer 201, so that the top surface of the isolation dielectric layer 102 is located between the top surface of the first fin 101 and the top surface of the first hard mask layer 201.
Preferably, the etching depth of the isolation dielectric layer 102 in step 31 is 10nm to 20 nm.
In step 32, as shown in fig. 2D, a second hard mask layer 202 is formed on the top surface of the isolation dielectric layer 102.
The material of the second hard mask layer 202 comprises silicon carbide.
In step 32, the second hard mask layer 202 is formed by a deposition process and a chemical mechanical polishing process using the first hard mask layer 201 as a stop layer.
Step 33, as shown in fig. 2E, removing the first hard mask layer 201 by using the second hard mask layer 202 as a mask, and etching the exposed first fin 101 to form the fin trench 103.
Filling a second semiconductor material layer in the fin body trench 103 and forming a second fin body 104, wherein the carrier mobility of the second semiconductor material layer is greater than that of the material of the semiconductor substrate 101 a.
In the method of the embodiment of the invention, the step four comprises the following sub-steps:
step 41, as shown in fig. 2F, an epitaxial growth process of the second semiconductor material layer is performed, the second semiconductor material layer grows upward from the bottom surface of the fin body trench 103, after the epitaxial growth is completed, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer 202, and the second semiconductor material layer also extends laterally onto the surface of the second hard mask layer 202.
Preferably, the material of the second semiconductor material layer includes silicon germanium or germanium.
Step 42, as shown in fig. 2G, a chemical mechanical polishing process is performed to level the top surface of the second semiconductor material layer and the surface of the second hard mask layer 202.
Step 42 is followed by:
step 43, as shown in fig. 2H, the second hard mask layer 202 is removed to expose the top corners of the second fin 104.
Step 44, as shown in fig. 2I, rounding the top corner of the second fin 104, where the rounding process includes:
oxidizing the exposed second fin body 104 to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
step 45, as shown in fig. 2J, the remaining second hard mask layer 202 is completely removed.
Step five, as shown in fig. 2J, the isolation dielectric layer 102 is etched to expose the top portion of the second fin body 104, and the top portion of the second fin body 104 is used for forming a channel region of the FinFET, so as to improve the electrical performance of the FinFET.
After the fifth step, the first gate oxide layer 105 is formed by the following steps:
step six, as shown in fig. 2K, an ALD process is used to deposit an amorphous silicon capping layer 203. The amorphous silicon capping layer 203 can protect the surface of the second fin 104.
Seventhly, as shown in fig. 2L, oxidizing the amorphous silicon cap layer 203 to form the first gate oxide layer 105.
The first gate oxide layer 105 serves as a gate oxide layer of an input-output FinFET.
The subsequent process further comprises the steps of forming a polycrystalline silicon pseudo gate, forming side walls on the side faces of the polycrystalline silicon pseudo gate, forming an embedded epitaxial layer in the second fin bodies 104 on the two layers of the polycrystalline silicon pseudo gate, performing source and drain injection to form a source region and a drain region, forming a zero layer interlayer film, performing metal gate replacement, and forming a metal interconnection structure. These processes are the same as the prior art and are not described in detail.
In the embodiment of the invention, after the first fin body 101 is formed by performing the patterned etching on the semiconductor substrate 101a, the first fin body 101 is not used for forming the channel region of the FinFET, but the isolation dielectric layer 102 is used for filling the interval region between the first fin bodies 101, the isolation dielectric layer 102 is used for performing the etching on the first fin body 101 under the self-alignment condition to form the fin body groove 103, then the second fin body 104 formed by the second semiconductor material layer with higher carrier mobility is filled in the fin body groove 103, and after the isolation dielectric layer 102 is etched, the top part of the second fin body 104 can be used as the channel region of the FinFET, so that the mobility of channel carriers of the device can be improved, and the performance of the device can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A method of manufacturing a FinFET, comprising:
providing a semiconductor substrate, and carrying out graphical etching on the semiconductor substrate to form a first fin body;
filling an isolation dielectric layer in the interval area of the first fin body;
etching the first fin body by taking the isolation medium layer as a self-alignment condition to form a fin body groove, wherein the bottom surface of the fin body groove is higher than that of the isolation medium layer;
extending a second semiconductor material layer in the fin body groove in an epitaxial manner and forming a second fin body, wherein the carrier mobility of the second semiconductor material layer is greater than that of the material of the semiconductor substrate;
and fifthly, etching the isolation medium layer to expose the top part of the second fin body, wherein the top part of the second fin body is used for forming a channel region of the FinFET so as to improve the electrical performance of the FinFET.
2. The method of fabricating the FinFET of claim 1, wherein: the material of the semiconductor substrate is silicon.
3. The method of fabricating the FinFET of claim 2, wherein: the material of the second semiconductor material layer comprises silicon germanium or germanium.
4. The method of fabricating the FinFET of claim 2, wherein: the first step comprises the following sub-steps:
step 11, forming a first hard mask layer on the surface of the semiconductor substrate;
step 12, carrying out photoetching definition and etching to pattern the first hard mask layer;
and step 13, etching the semiconductor substrate by taking the patterned first hard mask layer as a mask to form the first fin body.
5. The method of fabricating the FinFET of claim 4, wherein: the second step comprises the following sub-steps:
step 21, performing a deposition process of the isolation dielectric layer, wherein the deposited isolation dielectric layer completely fills the spacing region between the first fin bodies and extends to the surface of the first hard mask layer on the top of the first fin body;
and step 22, performing a chemical mechanical polishing process with the first hard mask layer as a stop layer to remove the isolation dielectric layer on the surface of the first hard mask layer on the top of the first fin body and to level the top surface of the isolation dielectric layer in the spacing area between the first fin bodies with the top surface of the first hard mask layer.
6. The method of fabricating the FinFET of claim 5, wherein: the third step comprises the following sub-steps:
step 31, etching the isolation medium layer by taking the first hard mask layer as a self-alignment condition to enable the top surface of the isolation medium layer to be positioned between the top surface of the first fin body and the top surface of the first hard mask layer;
step 32, forming a second hard mask layer on the top surface of the isolation dielectric layer;
and step 33, removing the first hard mask layer by taking the second hard mask layer as a mask, and etching the exposed first fin body to form the fin body groove.
7. The method of fabricating the FinFET of claim 6, wherein: the material of the isolation dielectric layer comprises an oxide layer.
8. The method of fabricating the FinFET of claim 7, wherein: in step 21, FCVD is used as the deposition process of the isolation dielectric layer.
9. The method of fabricating the FinFET of claim 7, wherein: the material of the first hard mask layer comprises silicon nitride.
10. The method of fabricating the FinFET of claim 9, wherein: the material of the second hard mask layer comprises silicon carbide.
11. The method of fabricating the FinFET of claim 6, wherein: and in the step 31, the etching depth of the isolation medium layer is 10 nm-20 nm.
12. The method of manufacturing a FinFET of claim 6 or 11, wherein: in step 32, a deposition process and a chemical mechanical polishing process using the first hard mask layer as a stop layer are used to form the second hard mask layer.
13. The method of fabricating the FinFET of claim 6, wherein: the fourth step comprises the following sub-steps:
step 41, performing an epitaxial growth process of the second semiconductor material layer, wherein the second semiconductor material layer grows upwards from the bottom surface of the fin body trench, and after the epitaxial growth is completed, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer and the second semiconductor material layer also extends transversely to the surface of the second hard mask layer;
and 42, carrying out a chemical mechanical polishing process to enable the top surface of the second semiconductor material layer to be flush with the surface of the second hard mask layer.
14. The method of fabricating the FinFET of claim 13, wherein: step 42 is followed by:
43, removing the second hard mask layer with a part of thickness to expose the top angle of the second fin body;
step 44, rounding the top angle of the second fin body, wherein the rounding process comprises the following steps:
oxidizing the exposed second fin body to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
and step 45, completely removing the residual second hard mask layer.
15. The method of fabricating the FinFET of claim 1, wherein: after the fifth step, forming a first gate oxide layer by adopting the following steps:
depositing an amorphous silicon cap layer by adopting an ALD (atomic layer deposition) process;
and seventhly, oxidizing the amorphous silicon cap layer to form the first gate oxide layer.
16. The method of fabricating the FinFET of claim 15, wherein: the first gate oxide layer is used as a gate oxide layer of the input-output FinFET.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210257462A1 (en) * 2020-02-19 2021-08-19 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors
CN114530417A (en) * 2022-04-24 2022-05-24 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure

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CN103094089A (en) * 2011-11-03 2013-05-08 台湾积体电路制造股份有限公司 Fin field effect transistor gate oxide
CN109148580A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 A kind of FinFET and preparation method thereof
CN109962017A (en) * 2017-12-22 2019-07-02 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN111052391A (en) * 2017-09-29 2020-04-21 英特尔公司 Doped insulator cap for reducing source/drain diffusion of germanium NMOS transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103094089A (en) * 2011-11-03 2013-05-08 台湾积体电路制造股份有限公司 Fin field effect transistor gate oxide
CN109148580A (en) * 2017-06-28 2019-01-04 中芯国际集成电路制造(上海)有限公司 A kind of FinFET and preparation method thereof
CN111052391A (en) * 2017-09-29 2020-04-21 英特尔公司 Doped insulator cap for reducing source/drain diffusion of germanium NMOS transistors
CN109962017A (en) * 2017-12-22 2019-07-02 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210257462A1 (en) * 2020-02-19 2021-08-19 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors
CN114530417A (en) * 2022-04-24 2022-05-24 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure

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