CN113782441B - FinFET manufacturing method - Google Patents
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- CN113782441B CN113782441B CN202111010817.3A CN202111010817A CN113782441B CN 113782441 B CN113782441 B CN 113782441B CN 202111010817 A CN202111010817 A CN 202111010817A CN 113782441 B CN113782441 B CN 113782441B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 20
- 238000005137 deposition process Methods 0.000 claims description 9
- 238000007517 polishing process Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims description 2
- 239000000969 carrier Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 121
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of FinFETs, which comprises the following steps: and step one, performing patterned etching on the semiconductor substrate to form a first fin body. And secondly, filling an isolation medium layer in the interval region of the first fin body. And thirdly, etching the first fin body by taking the isolation medium layer as a self-alignment condition to form a fin body groove. And fourthly, extending a second semiconductor material layer in the fin body groove and forming a second fin body, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate. And fifthly, etching the isolation dielectric layer to expose the top part of the second fin body. The invention can improve the mobility of channel carriers of the device, thereby improving the performance of the device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a fin field effect transistor (Fin Field Effect Transistor, finFET).
Background
The semiconductor device in the semiconductor integrated circuit adopts a plane structure at the beginning, the semiconductor device is directly formed on the surface of bulk silicon in the plane structure, the semiconductor device comprises a gate oxide layer and a gate structure of a polysilicon gate, which are formed on the surface of the bulk silicon, a source region and a drain region are formed in the bulk silicon on two sides of the gate structure in a self-aligned manner, a region covered by the gate structure between the source region and the drain region is a channel region, and when the semiconductor device is conducted, a conduction channel connecting the source region and the drain region is formed on the surface of the channel region. As the device size is reduced in constant proportion, the channel length is reduced, and in order to reduce short channel effects, the doping concentration of the channel region needs to be increased, and when the doping concentration of the channel region is increased, the carrier mobility in the conductive channel is reduced, and finally the performance of the device is affected.
In order to overcome the above-mentioned defects of planar devices, two new device structures, namely, an ultra-thin-body silicon-on-insulator (UTB SOI) device and a FinFET on an insulating layer of an ultra-thin body region, are developed, and the UTB SOI device and the FinFET have good electrical characteristics, so that the doping concentrations of the channel regions of the two devices can be reduced and short channel effects can be prevented at the same time, and the mobility of carriers can be improved after the doping concentration of the channel region is reduced, thereby finally improving the performance of the device.
With continued development in accordance with moore's law, the improvement in device performance never ends, and so we need to find channel materials and fabrication processes of higher mobility that are compatible with finfets.
Disclosure of Invention
The invention aims to provide a manufacturing method of a FinFET, which can improve the mobility of channel carriers of a device, thereby improving the performance of the device.
In order to solve the technical problems, the manufacturing method of the FinFET provided by the invention comprises the following steps:
step one, providing a semiconductor substrate, and performing patterned etching on the semiconductor substrate to form a first fin body.
And secondly, filling an isolation medium layer in the interval region of the first fin body.
And thirdly, etching the first fin body to form a fin body groove by taking the isolation medium layer as a self-alignment condition, wherein the bottom surface of the fin body groove is higher than the bottom surface of the isolation medium layer.
And step four, extending a second semiconductor material layer in the fin body groove and forming a second fin body, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate.
And fifthly, etching the isolation medium layer to expose the top part of the second fin body, wherein the top part of the second fin body is used for forming a channel region of the FinFET so as to improve the electrical performance of the FinFET.
A further improvement is that the semiconductor substrate is made of silicon.
A further improvement is that the material of the second semiconductor material layer comprises silicon germanium or germanium.
A further improvement is that step one comprises the following sub-steps:
step 11, forming a first hard mask layer on the surface of the semiconductor substrate;
step 12, carrying out photoetching definition and etching to pattern the first hard mask layer;
and step 13, etching the semiconductor substrate by taking the patterned first hard mask layer as a mask to form the first fin body.
The further improvement is that the step two comprises the following sub-steps:
step 21, performing a deposition process of the isolation medium layer, wherein the deposited isolation medium layer completely fills the interval area between the first fin bodies and extends to the surface of the first hard mask layer on the top of the first fin bodies;
step 22, performing a chemical mechanical polishing process using the first hard mask layer as a stop layer to remove the isolation dielectric layer on the surface of the first hard mask layer on the top of the first fin body and to level the top surface of the isolation dielectric layer and the top surface of the first hard mask layer in the interval region between the first fin bodies.
The further improvement is that the third step comprises the following sub-steps:
step 31, etching the isolation medium layer by taking the first hard mask layer as a self-alignment condition so that the top surface of the isolation medium layer is positioned between the top surface of the first fin body and the top surface of the first hard mask layer;
step 32, forming a second hard mask layer on the top surface of the isolation medium layer;
and 33, removing the first hard mask layer by taking the second hard mask layer as a mask, and etching the exposed first fin body to form the fin body groove.
In a further improvement, the material of the isolation dielectric layer comprises an oxide layer.
In a further improvement, in step 21, a deposition process of the isolation medium layer adopts a Flowable Chemical Vapor Deposition (FCVD).
A further improvement is that the material of the first hard mask layer comprises silicon nitride.
A further improvement is that the material of the second hard mask layer comprises silicon carbide.
The further improvement is that the etching depth of the isolation medium layer in the step 31 is 10 nm-20 nm.
In a further improvement, in step 32, the second hard mask layer is formed by a chemical mechanical polishing process using the deposition process with the first hard mask layer as a stop layer.
The further improvement is that the fourth step comprises the following sub-steps:
step 41, performing an epitaxial growth process of the second semiconductor material layer, wherein the second semiconductor material layer starts to grow upwards from the bottom surface of the fin body groove, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer after epitaxial growth is completed, and the second semiconductor material layer also transversely extends to the surface of the second hard mask layer;
and 42, performing a chemical mechanical polishing process to level the top surface of the second semiconductor material layer and the surface of the second hard mask layer.
Further improvement is that step 42 further comprises, after:
step 43, removing a part of the second hard mask layer to expose the top angle of the second fin body;
step 44, rounding the top angle of the second fin body, where the rounding process includes:
oxidizing the exposed second fin body to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
and step 45, completely removing the remaining second hard mask layer.
After the fifth step, the first gate oxide layer is formed by the following steps:
step six, depositing an amorphous silicon cap layer by adopting an ALD process;
and seventh, oxidizing the amorphous silicon cap layer to form the first gate oxide layer.
A further improvement is that the first gate oxide layer serves as a gate oxide layer of an input-output FinFET.
After the first fin body is formed by carrying out patterned etching on the semiconductor substrate, the first fin body is not used for forming a channel region of the FinFET, but after the isolation medium layer is filled in a spacing region between the first fin bodies, the first fin body is etched to form a fin body groove by taking the isolation medium layer as a self-aligned condition, then a second fin body is filled in the fin body groove and is formed by a second semiconductor material layer with higher carrier mobility, and after the isolation medium layer is etched, the top part of the second fin body can be used as the channel region of the FinFET.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a flowchart of a method of manufacturing a FinFET in an embodiment of the present invention;
fig. 2A-2L are schematic views of a device structure in steps of a method according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a flowchart of a method for manufacturing a FinFET in an embodiment of the present invention is shown; fig. 2A to 2L are schematic views of device structures in steps of a method according to an embodiment of the present invention; the manufacturing method of the FinFET comprises the following steps:
step one, as shown in fig. 2A, a semiconductor substrate 101a is provided, and the semiconductor substrate 101a is subjected to patterned etching to form a first fin body 101.
In the method of the embodiment of the invention, the first step comprises the following sub-steps:
step 11, forming a first hard mask layer 201 on the surface of the semiconductor substrate 101 a.
The material of the semiconductor substrate 101a is silicon.
The material of the first hard mask layer 201 includes silicon nitride.
Step 12, performing photolithography definition and etching to pattern the first hard mask layer 201;
and step 13, etching the semiconductor substrate 101a by using the patterned first hard mask layer 201 as a mask to form the first fin body 101.
Step two, as shown in fig. 2B, an isolation medium layer 102 is filled in the spaced area of the first fin body 101.
In the method of the embodiment of the invention, the second step comprises the following sub-steps:
step 21, performing a deposition process of the isolation dielectric layer 102, where the deposited isolation dielectric layer 102 completely fills and extends the space region between the first fins 101 onto the surface of the first hard mask layer 201 on the top of the first fins 101.
The material of the isolation dielectric layer 102 includes an oxide layer.
The deposition process of the isolation medium layer 102 adopts FCVD.
Step 22, performing a chemical mechanical polishing process using the first hard mask layer 201 as a stop layer to remove the isolation dielectric layer 102 on the surface of the first hard mask layer 201 on top of the first fin 101 and planarize the top surface of the isolation dielectric layer 102 and the top surface of the first hard mask layer 201 in the spacer region between the first fins 101.
And thirdly, etching the first fin body 101 to form a fin body groove 103 by taking the isolation medium layer 102 as a self-alignment condition, wherein the bottom surface of the fin body groove 103 is higher than the bottom surface of the isolation medium layer 102.
In the method of the embodiment of the invention, the third step comprises the following sub-steps:
in step 31, as shown in fig. 2C, the first hard mask layer 201 is used as a self-aligned condition to etch the isolation dielectric layer 102, so that the top surface of the isolation dielectric layer 102 is located between the top surface of the first fin body 101 and the top surface of the first hard mask layer 201.
Preferably, the etching depth of the isolation dielectric layer 102 in step 31 is 10nm to 20nm.
In step 32, as shown in fig. 2D, a second hard mask layer 202 is formed on the top surface of the isolation dielectric layer 102.
The material of the second hard mask layer 202 comprises silicon carbide.
In step 32, the second hard mask layer 202 is formed by a chemical mechanical polishing process using the first hard mask layer 201 as a stop layer by a deposition process.
In step 33, as shown in fig. 2E, the first hard mask layer 201 is removed by using the second hard mask layer 202 as a mask, and the exposed first fin 101 is etched to form the fin trench 103.
And step four, filling a second semiconductor material layer in the fin body groove 103 and forming a second fin body 104, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate 101 a.
In the method of the embodiment of the invention, the fourth step comprises the following sub-steps:
in step 41, as shown in fig. 2F, an epitaxial growth process of the second semiconductor material layer is performed, where the second semiconductor material layer starts to grow upwards from the bottom surface of the fin body trench 103, and after the epitaxial growth is completed, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer 202 and the second semiconductor material layer also extends laterally onto the surface of the second hard mask layer 202.
Preferably, the material of the second semiconductor material layer includes silicon germanium or germanium.
In step 42, as shown in fig. 2G, a chemical mechanical polishing process is performed to planarize a top surface of the second semiconductor material layer and a surface of the second hard mask layer 202.
Step 42 is followed by:
step 43, as shown in fig. 2H, removing a portion of the second hard mask layer 202 to expose the top corners of the second fin 104.
Step 44, as shown in fig. 2I, rounding the top angle of the second fin body 104, where the rounding process includes:
oxidizing the exposed second fin 104 to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
step 45, as shown in fig. 2J, the remaining second hard mask layer 202 is completely removed.
Step five, as shown in fig. 2J, etching the isolation medium layer 102 exposes a top portion of the second fin body 104, where the top portion of the second fin body 104 is used to form a channel region of the FinFET, so as to improve electrical performance of the FinFET.
After the fifth step, the first gate oxide layer 105 is formed by the following steps:
step six, as shown in fig. 2K, an ALD process is used to deposit an amorphous silicon cap layer 203. The amorphous silicon cap layer 203 can protect the surface of the second fin 104.
Step seven, as shown in fig. 2L, the amorphous silicon cap layer 203 is oxidized to form the first gate oxide layer 105.
The first gate oxide layer 105 serves as a gate oxide layer of an input-output FinFET.
The subsequent process further comprises forming a polysilicon dummy gate, forming a side wall on the side surface of the polysilicon dummy gate, forming an embedded epitaxial layer in the second fin body 104 of the two layers of the polysilicon dummy gate, performing source-drain injection to form a source region and a drain region, forming a zeroth interlayer film, and performing metal gate replacement to form a metal interconnection structure. These processes are identical to the existing processes and will not be described in detail.
In the embodiment of the invention, after the first fin body 101 is formed by performing patterned etching on the semiconductor substrate 101a, instead of forming the channel region of the FinFET by using the first fin body 101, after the isolation dielectric layer 102 fills the space region between the first fin bodies 101, the first fin body 101 is etched to form the fin body trench 103 by taking the isolation dielectric layer 102 as a self-aligned condition, then the second fin body 104 composed of the second semiconductor material layer with higher carrier mobility is filled in the fin body trench 103, and after the isolation dielectric layer 102 is etched, the top portion of the second fin body 104 can be used as the channel region of the FinFET, so that the embodiment of the invention can improve the mobility of channel carriers of the device, thereby improving the device performance.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (12)
1. A method of manufacturing a FinFET, comprising the steps of:
step one, providing a semiconductor substrate, and performing patterned etching on the semiconductor substrate to form a first fin body;
step one comprises the following sub-steps:
step 11, forming a first hard mask layer on the surface of the semiconductor substrate;
step 12, carrying out photoetching definition and etching to pattern the first hard mask layer;
step 13, etching the semiconductor substrate by taking the patterned first hard mask layer as a mask to form the first fin body;
filling an isolation medium layer in the interval region of the first fin body;
step three, etching the first fin body by taking the isolation medium layer as a self-alignment condition to form a fin body groove, wherein the bottom surface of the fin body groove is higher than the bottom surface of the isolation medium layer;
the third step comprises the following sub-steps:
step 31, etching the isolation medium layer by taking the first hard mask layer as a self-alignment condition so that the top surface of the isolation medium layer is positioned between the top surface of the first fin body and the top surface of the first hard mask layer;
step 32, forming a second hard mask layer on the top surface of the isolation medium layer;
step 33, removing the first hard mask layer by taking the second hard mask layer as a mask, and etching the exposed first fin body to form the fin body groove;
step four, a second semiconductor material layer is epitaxially grown in the fin body groove, and a second fin body is formed, wherein the carrier mobility of the second semiconductor material layer is larger than that of the material of the semiconductor substrate;
step four comprises the following sub-steps:
step 41, performing an epitaxial growth process of the second semiconductor material layer, wherein the second semiconductor material layer starts to grow upwards from the bottom surface of the fin body groove, the top surface of the second semiconductor material layer is higher than the top surface of the second hard mask layer after epitaxial growth is completed, and the second semiconductor material layer also transversely extends to the surface of the second hard mask layer;
step 42, performing a chemical mechanical polishing process to level the top surface of the second semiconductor material layer and the surface of the second hard mask layer;
step 43, removing a part of the second hard mask layer to expose the top angle of the second fin body;
step 44, rounding the top angle of the second fin body, where the rounding process includes:
oxidizing the exposed second fin body to form a sacrificial oxide layer;
removing the sacrificial oxide layer;
step 45, completely removing the remaining second hard mask layer;
and fifthly, etching the isolation medium layer to expose the top part of the second fin body, wherein the top part of the second fin body is used for forming a channel region of the FinFET so as to improve the electrical performance of the FinFET.
2. The method of manufacturing a FinFET of claim 1, wherein: the semiconductor substrate is made of silicon.
3. The method of manufacturing a FinFET of claim 2, wherein: the material of the second semiconductor material layer comprises germanium-silicon or germanium.
4. The method of manufacturing a FinFET of claim 2, wherein: the second step comprises the following sub-steps:
step 21, performing a deposition process of the isolation medium layer, wherein the deposited isolation medium layer completely fills the interval area between the first fin bodies and extends to the surface of the first hard mask layer on the top of the first fin bodies;
step 22, performing a chemical mechanical polishing process using the first hard mask layer as a stop layer to remove the isolation dielectric layer on the surface of the first hard mask layer on the top of the first fin body and to level the top surface of the isolation dielectric layer and the top surface of the first hard mask layer in the interval region between the first fin bodies.
5. The method of manufacturing a FinFET of claim 1, wherein: the material of the isolation dielectric layer comprises an oxide layer.
6. The method of manufacturing a FinFET in claim 4, wherein: in step 21, FCVD is used for the deposition process of the isolation medium layer.
7. The method of manufacturing a FinFET in claim 5, wherein: the material of the first hard mask layer comprises silicon nitride.
8. The method of manufacturing a FinFET of claim 7, wherein: the material of the second hard mask layer comprises silicon carbide.
9. The method of manufacturing a FinFET of claim 1, wherein: and in the step 31, the etching depth of the isolation medium layer is 10 nm-20 nm.
10. The method of manufacturing a FinFET in claim 1 or 9, wherein: in step 32, a chemical mechanical polishing process is performed using the deposition process to form the second hard mask layer using the first hard mask layer as a stop layer.
11. The method of manufacturing a FinFET of claim 1, wherein: after the fifth step, the first gate oxide layer is formed by the following steps:
step six, depositing an amorphous silicon cap layer by adopting an ALD process;
and seventh, oxidizing the amorphous silicon cap layer to form the first gate oxide layer.
12. The method of manufacturing a FinFET in claim 11, wherein: the first gate oxide layer is used as a gate oxide layer of the input-output FinFET.
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| CN114530417A (en) * | 2022-04-24 | 2022-05-24 | 合肥晶合集成电路股份有限公司 | Manufacturing method of semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094089A (en) * | 2011-11-03 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Fin field effect transistor gate oxide |
| CN109148580A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and preparation method thereof |
| CN109962017A (en) * | 2017-12-22 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111052391A (en) * | 2017-09-29 | 2020-04-21 | 英特尔公司 | Doped insulator cap for reducing source/drain diffusion of germanium NMOS transistors |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094089A (en) * | 2011-11-03 | 2013-05-08 | 台湾积体电路制造股份有限公司 | Fin field effect transistor gate oxide |
| CN109148580A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and preparation method thereof |
| CN111052391A (en) * | 2017-09-29 | 2020-04-21 | 英特尔公司 | Doped insulator cap for reducing source/drain diffusion of germanium NMOS transistors |
| CN109962017A (en) * | 2017-12-22 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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