CN108630547B

CN108630547B - FINFET device and preparation method thereof

Info

Publication number: CN108630547B
Application number: CN201710161651.2A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-17
Filing date: 2017-03-17
Publication date: 2021-03-19
Anticipated expiration: 2037-03-17
Also published as: CN108630547A

Abstract

The invention provides a FINFET device and a preparation method thereof, wherein the preparation method comprises the following steps: before the etching process is carried out on the fin, an ion doping process is carried out on the isolation structures on the two sides of the fin, so that the etching rate of the doped isolation structures is smaller than that of the isolation structures before doping; and then, performing an etching process on the fins, removing part of the fins and growing stress layers on the etched fins. In the preparation method provided by the invention, when the fin is etched, the isolation structure can be prevented from being greatly consumed, so that cavities can be prevented from being generated at the bottoms of the side walls at the two sides of the grid structure, the bridging phenomenon between the grid structure and the stress layer can be avoided, and the leakage current phenomenon of the formed FINFET device is effectively improved.

Description

FINFET device and preparation method thereof

Technical Field

The invention relates to the technical field of image sensors, in particular to a FINFET device and a forming method thereof.

Background

As semiconductor technology advances, the feature size of metal oxide semiconductor transistors (MOSFETs) continues to scale down in accordance with moore's law, and the circuit integration, performance, and power consumption of Integrated Circuits (ICs) using semiconductor devices as elements are increasing. In order to further increase the speed of semiconductor devices, MOSFETs of three-dimensional structures or non-planar structures different from conventional planar MOSFETs, that is, horizontal multi-faced gate structures, vertical multi-faced gate structures, and the like have been proposed in recent years. Including fin-field effect transistors (FINFETs), the critical dimensions of FinFET devices are simultaneously structured by two factors, the height and width of the gate structure, as compared to planar fets

Existing FINFET devices include multiple fins and a gate structure overlying and on both sides of the fins. That is, the portions of the sidewalls at the top and sides of the fin in contact with the gate structure form channel regions, so that the one FINFET device can simultaneously achieve multiple gate effects, thereby effectively increasing the drive current, which has better performance than planar transistors. However, the electrical performance of FINFET devices formed according to prior art methods is still unstable and affects the performance of FINFET devices, such as leakage current, which is common in prior art FINFET devices.

Disclosure of Invention

The invention aims to provide a FINFET device and a preparation method thereof, and aims to solve the problem that the conventional FINFET device formed according to the conventional preparation method of the FINFET device has large leakage current.

In order to solve the technical problem, the invention provides a preparation method of a FINFET device, which comprises the following steps:

providing a substrate, forming at least one fin and isolation structures positioned on two sides of the fin on the substrate, forming a gate structure above and on two sides of the fin, and forming a side wall on the side wall of the gate structure;

performing an ion doping process on the isolation structure, wherein the etching rate of the doped isolation structure is less than that of the isolation structure before doping;

and after the ion doping process is carried out, an etching process is carried out on the fin, part of the fin is removed, and a stress layer grows on the etched fin.

Optionally, the ions doped in the ion doping process are nitrogen ions.

Optionally, a plurality of fins are formed on the substrate, and the fins include a first fin and a second fin, the first fin corresponds to a transistor with a first conductivity type, and the second fin corresponds to a transistor with a second conductivity type opposite to the first conductivity type.

Optionally, the stress layer grown on the first fin and the stress layer grown on the second fin have opposite stress types.

Optionally, the first conductivity type transistor is a P-type transistor, and the stress layer grown on the first fin is a compressive stress layer; the transistor of the second conduction type is an N-type transistor, and the stress layer grown on the second fin is a tensile stress layer.

Optionally, the compressive stress layer is a germanium-silicon layer; the tensile stress layer is a phosphorus silicon layer.

Optionally, the method for growing stress layers on the first fin and the second fin includes:

forming a first mask layer on the substrate, wherein the first mask layer covers the second fins and exposes the first fins;

performing an etching process on the first fin by taking the first mask layer as a mask, and growing a first stress layer on the etched first fin;

forming a second mask layer on the substrate, wherein the second mask layer covers the first fins and exposes the second fins;

and performing an etching process on the second fin by taking the second mask layer as a mask, and growing a second stress layer on the etched second fin.

Optionally, the first mask layer further exposes the isolation structures on two sides of the first fin, and before performing an etching process on the first fin, an ion doping process is performed on the exposed isolation structures; the second mask layer further comprises an isolation structure exposing two sides of the second fin, and an ion doping process is performed on the exposed isolation structure before the etching process is performed on the second fin.

Optionally, the method for growing stress layers on the first fin and the second fin further includes:

covering a first shielding layer on the first fin before etching and the second fin before etching;

forming the first mask layer on the first shielding layer, wherein the first mask layer exposes the first shielding layer on the first fin;

performing an etching process on the first shielding layer and the first fin by taking the first mask layer as a mask, removing the first fin and the first shielding layer on corresponding heights, exposing the first fin and growing the first stress layer on the etched first fin;

covering a second shielding layer on the first stress layer;

forming a second mask layer on the second shielding layer, wherein the second mask layer exposes the first shielding layer on the second fin;

and performing an etching process on the first shielding layer and the second fin by taking the second mask layer as a mask, removing the second fin and the first shielding layer at corresponding heights, exposing the second fin and growing the second stress layer on the etched second fin.

Optionally, the first shielding layer, the second shielding layer and the sidewall are made of the same material.

Optionally, the stress layer is formed by an epitaxial process or a chemical vapor deposition process.

It is a further object of the present invention to provide a FINFET device comprising:

a substrate;

at least one fin formed on the substrate, a stress layer grown on the fin;

the isolation structures are positioned on two sides of the fin, ions are doped in the isolation structures, and the etching rate of the doped isolation structures is less than that of the undoped isolation structures;

and the grid structures are formed above and on two sides of the fins, and the side walls are positioned on the side walls of the grid structures.

Optionally, the doped ions in the isolation structure are nitrogen ions.

Optionally, a plurality of fins are formed on the substrate, and the fins include a first fin and a second fin, the first fin corresponds to a transistor of a first conductivity type, and the second fin corresponds to a transistor of a second conductivity type opposite to the first conductivity type.

Optionally, the stress layer grown on the first fin is opposite to the stress layer grown on the second fin in stress type.

In the preparation method of the FINFET device, before etching the fin, the ion doping process is carried out on the isolation structures exposed at the two sides of the fin to reduce the etching rate of the isolation structures in the subsequent etching process, so that the consumption of the isolation structures in the etching process can be reduced or even avoided, further, the bottom of the side wall on the side wall of the grid structure cannot generate a cavity to expose the grid region, the problem that the stress layer formed subsequently is bridged with the grid structure is avoided, and the leakage current phenomenon of the FinFET device formed finally is effectively improved. Furthermore, the ion doping process for the isolation structure and the etching process for the fin can be combined with each other, that is, the same photoetching process is utilized to define the region to be subjected to ion doping and the fin to be etched, so that an additional preparation step is not required to be added, the process flow is optimized, the cost is saved,

drawings

FIG. 1 is a schematic diagram of a FINFET device;

FIG. 2 is a schematic flow chart of a method of fabricating a FINFET device in accordance with an embodiment of the present invention;

FIGS. 3a-3g are top views of a FINFET device during its fabrication in one embodiment of the present invention;

FIGS. 4a-4j are schematic cross-sectional views of the FINFET device of FIGS. 3a-3g taken along the A-A 'and B-B' directions during fabrication thereof in accordance with one embodiment of the present invention;

FIG. 5 is a schematic diagram of a FINFET device in accordance with an embodiment of the present invention;

fig. 6 is a schematic cross-sectional view of the FINFET device of fig. 5 in an embodiment of the invention, taken along the directions C-C 'and D-D'.

Detailed Description

As described in the background art, the FINFET device formed according to the conventional fabrication method has a problem of large leakage current, thereby affecting the device performance.

Fig. 1 is a schematic structural diagram of a FINFET device, and as shown in fig. 1, the FINFET device includes a substrate 10, a fin 11 and isolation structures 12 located on two sides of the fin 11 are formed on the substrate 10, a gate 13 is formed above and on two sides of the fin 11, and a sidewall 14 covers a surface of the gate 13. Furthermore, to improve the electron mobility of the resulting FINFET device, it is common to etch away portions of the fin and grow a stress layer 15 over the etched fin, which stress layer 15 can apply stress to the channel, thereby affecting the carrier mobility of the transistor.

The inventors of the present application found through research that, when the stress layer 15 is prepared, the grown stress layer 15 may cross the bottom of the sidewall spacer 14, so as to bridge the gate 13, thereby causing leakage current in the formed FINFET device. Specifically, before the stress layer is grown, a cavity 12A appears at the bottom of the sidewall 14 located at two sides of the gate 13, and the cavity 12A exposes the gate 13; in the process of epitaxially growing the stress layer, the stress layer formed on the fin 11 has a certain shape and structure and extends the projection region of the fin 11 due to the crystal orientation of the fin 11 and the crystal orientation of the epitaxial material forming the stress layer. In this way, the extended epitaxial layer may extend to the gate region through the void 12A at the bottom of the sidewall spacer 14, resulting in bridging with the formed gate. The inventors have further found that the reason for forming the cavity 12A at the bottom of the sidewall 14 is that during the etching process for removing part of the fin, the isolation structure 12 is also etched away by a small amount, thereby exposing the gate region.

To this end, the present invention provides a method for manufacturing a FINFET device, and fig. 2 is a schematic flow chart of a method for manufacturing a FINFET device according to an embodiment of the present invention, and as shown in fig. 2, the method for manufacturing a FINFET device includes:

step S100, providing a substrate, forming at least one fin and isolation structures positioned on two sides of the fin on the substrate, forming a gate structure above and on two sides of the fin, and forming a side wall on the side wall of the gate structure;

step S200, performing an ion doping process on the isolation structure, wherein the etching rate of the doped isolation structure is less than that of the isolation structure before doping;

step S300, after the ion doping process is performed, an etching process is performed on the fins, a part of the fins are removed, and a stress layer grows on the etched fins.

In the preparation method of the FINFET device, before removing part of the fins, the ion doping is carried out on the isolation structure to reduce the etching rate of the isolation structure in the subsequent etching process, so that the etching amount of the isolation structure can be reduced when the etching process is carried out subsequently, and the formation of a cavity at the bottom of the side wall on the side wall of the grid electrode is avoided, therefore, a stress layer grown subsequently can be prevented from extending to the grid electrode area through the cavity, an isolation state is kept between the epitaxial layer and the grid electrode, and the leakage current phenomenon of the FINFET device is effectively improved.

The FINFET device and the method for fabricating the FINFET device according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

In this embodiment, a method for manufacturing a FINFET device will be described with reference to a FINFET device formed by a gate last process. FIGS. 3a-3d are top views of a FINFET device during its fabrication in one embodiment of the present invention; fig. 4a-4h are schematic cross-sectional views of the FINFET device of fig. 3a-3d in an embodiment of the invention, taken along the a-a 'and B-B' directions during its fabrication.

In step S100, as shown in fig. 3a and fig. 4a, a substrate 100 is provided, at least one fin and isolation structures 120 located at two sides of the fin are formed on the substrate 100, a gate structure 130 is formed above and on two sides of the fin, and sidewalls 140 cover sidewalls of the gate structure 130. In this embodiment, a plurality of fins (only two fins are shown in fig. 4 a) are formed on the substrate 100, and the plurality of fins are sequentially arranged and may be arranged at the same distance, and adjacent fins are isolated from each other by the isolation structure 120. The substrate 100 may be a silicon substrate, and the isolation structure 120 may be made of silicon dioxide.

As a specific example, the plurality of fins in this embodiment correspond to transistors with different conductivity types, that is, a part of the fins correspond to the transistors with N-type conductivity, and another part of the fins correspond to the transistors with P-type conductivity. As shown in fig. 3a and 4a, in the present embodiment, the region for forming the N-type transistor is defined as an N region 100N, and the region for forming the P-type transistor is defined as a P region 100P; and the corresponding fin to form a P-type transistor is defined as a first fin 110P and the corresponding fin to form an N-type transistor is defined as a second fin 100N. Of course, in other embodiments, the conductivity types of the transistors formed by the fins may be the same, and the transistors of the corresponding conductivity types may be prepared according to the formed device.

The specific process of step S100 can be illustrated with reference to fig. 3a and 4a-4 b.

In a first step, as shown in fig. 3a and 4a, a first fin 100P and a second fin 100N are formed on a substrate 100, and isolation structures 120 are formed on both sides of the first fin 100P and the second fin 100N. The specific forming method comprises the following steps: firstly, defining a region where a fin and an isolation structure are required to be formed by performing a photoetching process; then, performing an etching process to form a plurality of grooves and fins on the substrate 100, wherein the grooves are used for forming the isolation structures subsequently; then, an isolation material is filled in the groove to form an isolation structure 120. Of course, in a specific manufacturing process, when the isolation material is filled, the isolation material may cover the fin, so that the isolation material may be polished by a chemical mechanical polishing process to expose the fin, and the isolation material is further etched in combination with an etching process, so as to manufacture the fin with the first height.

In a second step, continuing to refer to fig. 3a and 4a, a gate dielectric layer 131 is formed over the surface of the fin and a gate electrode layer 132 is formed over the top and sides of a portion of the fin. This embodiment exemplifies the formation of a FINFET device by a gate process, and thus, the gate dielectric layer 131 and the gate electrode layer 132 herein form a dummy gate structure. Specifically, the gate dielectric layer 131 may be formed by a thermal oxidation process. In the formation of the gate electrode layer 132, a hard mask layer 140 may be used to perform a patterning process, and in addition, the hard mask layer 140 may also protect the gate electrode layer 132 thereunder in a subsequent process flow, so as to avoid a problem that the gate electrode layer 132 is damaged in the subsequent process and the pattern of the gate electrode layer 132 is deviated.

In a third step, referring to fig. 4b, a sidewall spacer 150 is formed on the sidewall of the dummy gate structure 130. When the dummy gate structure 130 is subsequently removed to form a back gate structure, the morphology of the back gate structure may be defined by the sidewall spacers 150.

In step S200, as shown in fig. 4b-4c and 4g, an ion doping process is performed on the isolation structure 120, and the etching rate of the doped isolation structure 121 is less than that of the isolation structure 120 before doping. Namely, the problem that the isolation structure is consumed in the subsequent etching process is reduced or even avoided by doping the isolation structure. Specifically, the ion doping process may be an ion implantation process. Further, the ions doped in the isolation structure 120 may be nitrogen ions.

As described above, the substrate 100 in this embodiment has the first fin 110P and the second fin 110N formed thereon, which respectively correspond to transistors having opposite conductivity types, and adjacent fins are isolated from each other by the isolation structure. The ion doping process of the isolation structures on both sides of the first fin 110P and the doping process of the isolation structures on both sides of the second fin 110N may be performed simultaneously, that is, after the sidewall 150 is formed on the sidewall of the gate structure 130, the isolation structures 120 on both sides of the first fin 110P and the second fin 110N are exposed at the same time, and then the isolation structures 120 on both sides of all the fins may be doped simultaneously in the same ion doping process. Of course, the ion doping process of the isolation structures 120 on the two sides of the first fin 110P may also be combined with the subsequent etching process of the first fin 110P, so that one photolithography process may be reduced, and the process flow may be simplified. The specific formation steps of the combination of the ion doping process and the etching process will be described in detail later.

In step S300, referring to fig. 4c-4e and 4g-4h, after the ion doping process is performed, an etching process is performed on the fin, a portion of the fin is removed, and a stress layer 160N and a stress layer 160P are grown on the etched fin, where the stress layer can apply stress to a conductive channel of the formed transistor, so as to improve the electron mobility of the transistor.

Since the ion doping is performed on the isolation structure 120 in the step S200, the doped isolation structure 121 has a lower etching rate in the etching process of the step S300, and the consumption of the doped isolation structure 121 in the etching process is effectively alleviated or even avoided, so that a cavity can be prevented from being formed at the bottoms of the side walls 150 at the two sides of the dummy gate structure 130, and thus, the phenomenon that a stress layer grown subsequently does not extend to the projection region of the gate structure to bridge with the gate can be ensured, and the leakage current of the formed FINFET device can be effectively improved.

The height of the fin is reduced through an etching process, so that on one hand, a certain growth space can be provided for a stress layer formed subsequently; on the other hand, by removing part of the fins, the fins close to the channel region can be exposed, so that the stress layer formed subsequently can be closer to the channel, and the electron mobility of the formed transistor can be further improved. The first height of the fin before etching and the second height of the fin after etching can be adjusted according to actual requirements, and specific data are not listed here.

In this embodiment, a first fin 110P and a second fin 110N are formed on the substrate 100, and transistors with different conductivity types are correspondingly formed on the first fin 110P and the second fin 110N, so that stress layers with opposite stress types need to be formed on the first fin 110P and the second fin 110N. Specifically, a P-type transistor is correspondingly formed on the first fin 110P, and a compressive stress layer is correspondingly formed on the etched first fin 110P; and correspondingly forming an N-type transistor on the second fin 110N, and correspondingly forming a tensile stress layer on the etched second fin 110N. The tensile stress layer may be a phosphorus silicon layer, and the compressive stress layer may be a germanium silicon layer.

Therefore, when the compressive stress layer is prepared on the first fins 110P, the second fins 110N can be covered with a shielding layer to prevent the second fins 110N from being affected; and vice versa. In an optional scheme, the sidewall material 151 forming the sidewall 150 may be directly used as a shielding layer, so that a preparation process of the shielding layer may be reduced, which is beneficial to simplifying the process flow.

Further, the stress layer may be formed by an epitaxial process or a deposition process. The stress layer additionally formed on the fin usually has a certain shape due to the dynamic influence of the epitaxial process or the deposition process and the fin crystal orientation, for example, in the embodiment, the formed silicon germanium layer and the formed silicon phosphorus layer usually have a diamond structure.

In this embodiment, when step S100 is executed, a shielding layer is formed on a part of the fins while forming the sidewalls 150 on both sides of the gate structure 130; and the related processes in step S200 and step S300 are combined with each other, that is, the ion doping process performed on the isolation structure and the etching process performed on the first fin and the second fin are combined with each other, so as to further simplify the process flow and save the manufacturing cost.

First, referring to fig. 3a and 4a, a plurality of fins having a first height, including a first fin 110P and a second fin 110N, are formed on the substrate 100, isolation structures 120 are formed on both sides of the plurality of fins, and gate structures 130 are formed above and on both sides of the fins.

Next, referring to fig. 4b, depositing a sidewall material 151 on the substrate 100, and forming a patterned first mask layer 153 on the sidewall material 151, where the patterned first mask layer 153 covers the N region 100N corresponding to the second fin 110N and exposes the P region 100P corresponding to the first fin 110P; thereby, the sidewall materials 151 on both sides of the first fin 110P may be removed according to the patterned first mask layer 153 to expose the isolation structure 120. It should be understood that when the sidewall material 151 on the isolation structures 120 is removed, the sidewall material on the top of the first fins 110P is also removed. The first mask layer 153 is, for example, photoresist.

Next, referring to fig. 3b and 4c, an ion doping process is performed on the isolation structures 120 exposing the two sides of the first fin 110P by using the first mask layer 153 as a mask, so as to form doped isolation structures 121.

Next, referring to fig. 4d, continuing to perform an etching process on the first fins 110P by using the first mask layer 153 as a mask, and removing a portion of the first fins to form etched first fins 111P with a second height. It should be appreciated that when etching the first fin to reduce the height thereof, the other film layers covering the corresponding height position of the first fin are also removed, for example, when the surface of the fin is covered with the sidewall material, the sidewall material and the fin at the corresponding height are simultaneously removed.

Next, referring to fig. 3c and fig. 4e, the patterned first mask layer is removed, and a compressive stress layer 160P is epitaxially grown on the etched first fin 111P. In this process, since the second fin 110N is covered with the sidewall material 151, a shielding layer is formed, so that a compressive stress layer can be prevented from growing on the second fin 110N.

Next, referring to fig. 4f, a shielding layer 152 is covered on the surface of the compressive stress layer 160P, and the shielding layer 152 may be made of the same material as the sidewall spacer 150. Similarly, the shielding layer 152 is used to protect the compressive stress layer 160P, so as to avoid the influence on the compressive stress layer 160P when the stress layer is grown on the N region 100N in the following step.

Next, referring to fig. 3d, fig. 3e and fig. 4g, a patterned second mask layer 154 is formed on the substrate 100, the second mask layer 154 covers the P-type region 100P and exposes the N-type region 100N corresponding to the second fin 110N, and the second mask layer 154 is used as a mask layer when the second fin 110N is subsequently etched. Similarly, prior to performing the etching process, an ion doping process is preferentially performed on the exposed isolation structures 120 to form doped isolation structures 121; next, an etching process is performed on the second fin 110N to form a second fin 111N with a second height.

Next, referring to fig. 3f and fig. 4h, the second mask layer is removed, and a tensile stress layer 160N is grown on the etched second fin 111N. After the formation of the tensile stress layer 160N, the shielding layer covering the P region 100P may be removed, but the shielding layer may also be remained, which is not limited herein.

At this point, a compressive stress layer 160P and a tensile stress layer 160N are respectively formed on the first fin 110P and the second fin 110N. In this embodiment, a FINFET device is formed by a gate last process, so after forming the stress layer, the dummy gate structure is removed, and a gate last structure is formed.

Referring specifically to fig. 4i, a dielectric layer 170 is formed on the substrate 100, and the dielectric layer 170 fills the gaps between the fins and completely covers the fins and the dummy gate structure. The dielectric layer 170 may be polished by a chemical mechanical polishing process to expose the dummy gate structure, so that the dummy gate structure may be removed and a gate window 130a may be formed.

Referring next to fig. 3g and 4j, a back gate structure is formed in the gate window 130 a. Specifically, the back gate structure includes a high-K dielectric layer 131 ' formed on the bottom and the sidewall of the gate window, and a metal gate 132 ' formed on the high-K dielectric layer 131 ' and filling the gate window. For convenience of understanding, fig. 3g does not show the dielectric layer covering the fin, but only shows the fin on which the stress layer 160P and the stress layer 160N are grown, the back gate structure, and the sidewalls 150 located at two sides of the back gate structure.

In addition, the invention also provides a FINFET device according to the preparation method of the FINFET device provided by the invention. Fig. 5 is a schematic structural view of a FINFET device in an embodiment of the invention, and fig. 6 is a cross-sectional view of the FINFET device in an embodiment of the invention shown in fig. 5, taken along the directions C-C 'and D-D', in conjunction with fig. 5 and 6, the FINFET device including:

a substrate 200;

at least one fin formed on the substrate 200, on which a stress layer is grown;

the isolation structures 220 are positioned on two sides of the fin, ions are doped in the isolation structures 220, and the etching rate of the doped isolation structures is less than that of the undoped isolation structures;

a gate structure formed over and on both sides of the fin, and a sidewall 250 on the sidewall of the gate structure.

In this embodiment, a plurality of fins are formed on the substrate 200, including a first fin 211P and a second fin 211N, where the first fin 211P corresponds to a transistor of a first conductivity type, and the second fin 211N corresponds to a transistor of a second conductivity type opposite to the first conductivity type. For example, the first conductive type transistor is a P-type transistor, and the second conductive type transistor is an N-type transistor. In this embodiment, a region where a P-type transistor is formed is defined as a P region 200P, and a region where an N-type transistor is formed is defined as an N region 200N.

In the transistors with different conductive types, stress layers with different stress types are correspondingly formed, that is, the stress types of the stress layers formed on the first fin 211P and the second fin 211N are opposite. In this embodiment, the stress layer 160P formed on the first fin 211P in the P region 200P is a compressive stress layer, and the compressive stress layer 160P is, for example, a sige layer; the stress layer 160N formed on the second fin 211N in the N region 200N is a tensile stress layer, and the tensile stress layer 160N is, for example, a phosphorus silicon layer.

As shown in fig. 5 and 6, the isolation structures 220 formed on both sides of the fin are doped with ions, so that in the etching process of the fin, the doped isolation structures have a lower etching rate, the isolation structures are prevented from being consumed in the etching process, it is ensured that no void is generated at the bottoms of the side walls 250 on both sides of the gate structure, and no bridging phenomenon is generated between the gate structure and the stress layer in the finally formed FINFET device, thereby effectively improving the leakage current of the FINFET device. Specifically, the ions doped in the isolation structure may be nitrogen ions. Specifically, a doped region 221 may be formed in the isolation structure 220 through an ion implantation process, where the doped region 221 extends to an upper surface of the isolation structure 220, that is, the doped region 221 is the doped isolation structure.

Further, the FINFET device in this embodiment is formed by a gate last process, that is, first, a sidewall 250 is formed, a gate window is defined by the sidewall 250, and then a high-K dielectric layer 231 is formed on the bottom and the sidewall of the gate window; and forming a metal gate 232 on the high-K dielectric layer 231, wherein the high-K dielectric layer 231 and the metal gate 232 form the gate structure. In addition, when the gate structure is formed, a dielectric layer is further formed on the substrate, which is specifically shown in fig. 4i and 4j, and is shown in fig. 5 and 6 in this embodiment for ease of understanding.

In summary, in the method for manufacturing a FINFET device provided by the present invention, before etching the fin to form the stress layer, an ion doping process is performed on the isolation structures exposed at two sides of the fin to reduce the etching rate of the isolation structures in a subsequent etching process, so that the consumption of the isolation structures in the etching process can be reduced or even avoided, and further, the gate region is prevented from being exposed due to the formation of a void at the bottom of the sidewall. Namely, the FinFET device finally formed by the preparation method provided by the invention greatly reduces the probability of bridging between the grid structure and the stress layer, and effectively improves the leakage current phenomenon of the FinFET device.

Furthermore, the ion doping process for the isolation structure and the etching process for the fin can be combined with each other, that is, the ion doping process and the etching process are performed by using the same photoetching process, so that the process flow is reduced, and the cost is saved. In addition, when the side walls on the two sides of the gate structure are formed, the side wall material can be further used as a shielding layer to cover the first fin or the second fin, so that a non-predetermined stress layer is prevented from growing on the first fin or the second fin, and the process flow can be further optimized.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A method of fabricating a FINFET device, comprising:

after the ion doping process is carried out, an etching process is carried out on the fin, part of the fin is removed, and a stress layer grows on the etched fin;

a first fin and a second fin are formed on the substrate, the first fin correspondingly forms a transistor of a first conductivity type, and the second fin correspondingly forms a transistor of a second conductivity type opposite to the first conductivity type; and a method of growing a stress layer over the first fin and the second fin, comprising: forming a first mask layer on the substrate, wherein the first mask layer covers the second fins and exposes the first fins; performing an etching process on the first fin by taking the first mask layer as a mask, and growing a first stress layer on the etched first fin; forming a second mask layer on the substrate, wherein the second mask layer covers the first fins and exposes the second fins; and performing an etching process on the second fin by taking the second mask layer as a mask, and growing a second stress layer on the etched second fin.

2. The method of fabricating a FINFET device according to claim 1, wherein the ions doped in the ion doping process are nitrogen ions.

3. The method of fabricating a FINFET device according to claim 1, wherein the stress layer grown on the first fin is of an opposite stress type to the stress layer grown on the second fin.

4. The method of fabricating a FINFET device of claim 1, wherein the transistor of the first conductivity type is a P-type transistor and the stress layer grown on the first fin is a compressive stress layer; the transistor of the second conduction type is an N-type transistor, and the stress layer grown on the second fin is a tensile stress layer.

5. The method of fabricating a FINFET device according to claim 4, wherein said compressive stress layer is a silicon germanium layer.

6. The method of fabricating a FINFET device according to claim 4, wherein said tensile stress layer is a phosphorous silicon layer.

7. The method of fabricating a FINFET device of claim 1, wherein the first mask layer further exposes isolation structures on both sides of the first fin, and wherein an ion doping process is performed on the exposed isolation structures before the etching process is performed on the first fin; the second mask layer further comprises an isolation structure exposing two sides of the second fin, and an ion doping process is performed on the exposed isolation structure before the etching process is performed on the second fin.

8. The method of fabricating a FINFET device of claim 1, wherein the method of growing stress layers over the first fin and the second fin further comprises:

covering a second shielding layer on the first stress layer;

9. The method of fabricating a FINFET device according to claim 8, wherein the first masking layer, the second masking layer and the sidewalls are made of the same material.

10. The method of fabricating a FINFET device according to claim 1, wherein the stress layer is formed by an epitaxial process or a chemical vapor deposition process.

11. A FINFET device, comprising:

a substrate;

at least one fin formed on the substrate, wherein a stress layer grows on the fin, the at least one fin comprises a first fin and a second fin, the first fin correspondingly forms a transistor with a first conductive type, the second fin correspondingly forms a transistor with a second conductive type opposite to the first conductive type, and the stress layer grows on the first fin and the stress layer grows on the second fin and is opposite to the stress type of the stress layer;

and the top surface of the fin with the stress layer is lower than the top surface of the fin covered by the gate structure.

12. The FINFET device of claim 11, wherein the dopant ions in the isolation structure are nitrogen ions.

13. The FINFET device of claim 11, wherein the transistor of the first conductivity type is a P-type transistor and the stress layer grown on the first fin is a compressive stress layer; the transistor of the second conduction type is an N-type transistor, and the stress layer grown on the second fin is a tensile stress layer.

14. The FINFET device of claim 13, wherein the compressive stress layer is a silicon germanium layer.

15. The FINFET device of claim 13, wherein the tensile stress layer is a phosphorous silicon layer.