CN113838923B - Three-dimensional strain Si bipolar junction transistor and preparation method thereof - Google Patents

Three-dimensional strain Si bipolar junction transistor and preparation method thereof Download PDF

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CN113838923B
CN113838923B CN202111113232.4A CN202111113232A CN113838923B CN 113838923 B CN113838923 B CN 113838923B CN 202111113232 A CN202111113232 A CN 202111113232A CN 113838923 B CN113838923 B CN 113838923B
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fin
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CN113838923A (en
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周春宇
李作为
尚建蕊
王冠宇
徐超
孙继浩
关义春
赵鸿飞
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Yanshan University
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Abstract

Existing bipolar junction transistors have small gain and small characteristic frequency and require miniaturization. The application provides a three-dimensional strain Si bipolar junction transistor, which comprises a p-type Si substrate and an n-type Si substrate which are sequentially arranged in a first direction + Emitter region, siO 2 Shallow trench isolation structure, siO 2 The semiconductor device comprises a layer, a fin type semiconductor p-type base region, a SiGe strain epitaxial layer and an n-type collector region, wherein the first direction is the direction from a substrate to the n-type collector region; an n-type collector region is arranged on the fin-type semiconductor p-type base region; siO (SiO) 2 An emitter contact is arranged on the layer, a base contact is arranged on the SiGe strain epitaxial layer, and a collector contact is arranged on the P-type collector region; the SiGe strain epitaxial layer simultaneously applies uniaxial tensile stress to the fin semiconductor p-type base region and the n-type collector region. The electron mobility is increased, the transit time of the base region and the collector region is reduced, and the characteristic frequency of the device is increased.

Description

Three-dimensional strain Si bipolar junction transistor and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a three-dimensional strain Si bipolar junction transistor and a preparation method thereof.
Background
As the feature size of Complementary Metal Oxide Semiconductor (CMOS) process technology is scaled down to 22nm, conventional planar transistor structures have suffered from bottlenecks only by relying on techniques such as increasing the doping concentration of the channel, reducing the source-drain junction depth, and reducing the gate oxide thickness, so that the subthreshold current of the device becomes a main cause of impeding further process development. In 1999, the first fin field effect transistor (FinFET), a three-dimensional Metal Oxide Semiconductor (MOS) transistor, was created. Since the semiconductor located in the channel is very thin, like a Fin of a fish (Fin), researchers have named it as a Fin field effect transistor. The raised channel region of the FinFET transistor is a Fin-shaped semiconductor wrapped by a three-sided grid, the contact area between the grid and the channel is increased by the structure that the grid wraps the channel three-sided, the control capability of the grid on the channel is enhanced, and meanwhile, the distance from the grid to an internal Fin (Fin) is shortened, so that the grid can effectively control the channel, the leakage current when the device is closed is reduced, and the short channel effect is restrained. Intel corporation 2011 announced that 22nm-FinFET process technology was introduced, after which FinFET process technology became the dominant manufacturing process for small-scale integrated circuit fabrication for large vendors.
The BiCMOS technology is a technology of integrating Bipolar Junction Transistor (BJT) and Complementary Metal Oxide Semiconductor (CMOS) devices on one chip at the same time, and integrates the advantages of the BJT and CMOS devices, which make up for the advantages of both, and opens up a new way in analog/digital hybrid microelectronic circuits and very large scale integrated circuits.
Disclosure of Invention
1. Technical problem to be solved
In order to solve the problems of small gain, small characteristic frequency and small size of the existing bipolar junction transistor, the application provides a three-dimensional strain Si bipolar junction transistor and a preparation method thereof.
2. Technical proposal
To achieve the above object, the present application provides a three-dimensional strained Si bipolar junction transistor comprising, in a first direction, a p-type Si substrate, an n-type Si substrate, sequentially arranged + Emitter region, siO 2 Shallow trench isolation structure, siO 2 The semiconductor device comprises a layer, a fin-type semiconductor p-type base region, a SiGe strain epitaxial layer and an n-type collector region, wherein the first direction is the direction from the substrate to the n-type collector region; the fin-type semiconductor p-type base region is provided with the n-type collector region; the SiO is 2 An emitter contact is arranged on the layer, a base contact is arranged on the SiGe strain epitaxial layer, and a collector contact is arranged on the P-type collector region; the SiGe strain epitaxial layer simultaneously applies uniaxial tensile stress to the fin semiconductor p-type base region and the n-type collector region.
Another embodiment provided herein is: said n + The emitter region and the fin type semiconductor p-type base region have the same width.
Another embodiment provided herein is: the fin-type semiconductor p-type base region comprises an intrinsic base region and an extrinsic base region, the intrinsic base region is in contact with the n-type collector region, the intrinsic base region is wrapped by three sides of the n-type collector region, and the n-type collector region extracts electrons from the fin-type semiconductor p-type base region in three directions; the extrinsic base region is encased within a SiGe strained epitaxial layer.
Another embodiment provided herein is: said n + The width of the emitting area is 10 nm-20 nm; the width of the fin type semiconductor p-type base region is 10 nm-20 nm, and the height of the fin type semiconductor p-type base region is 21 nm-41 nm.
The present application also provides a method for preparing a bipolar junction transistor, characterized in that: the method is compatible with 22nm fin field effect transistor fabrication processes.
Another embodiment provided herein is: the method comprises the following steps: step 1: sequentially depositing a hard mask and a polysilicon auxiliary layer on a substrate; step 2: photoetching and etching the polysilicon auxiliary layer, and depositing SiO (silicon oxide) on the hard mask and the treated polysilicon auxiliary layer 2 A layer; step 3: for the SiO 2 Etching the layer to form SiO 2 The side wall is used for removing the polysilicon auxiliary layer; step 4: in SiO form 2 Etching the side wall downwards to form an active region by using the mask plate as a side wall; step 5:removing the SiO 2 Side wall, deposited SiO 2 A filling layer filling the active region; step 6: for the SiO 2 Back etching the filling layer to make the active region protrude from SiO 2 A surface controlling the fin semiconductor height; removing the hard mask; step 7: processing the fin-type semiconductor to form an emitter contact region; depositing a barrier layer; step 8: treating the barrier layer, and treating the SiO 2 Photoetching and etching the filling layer to form SiO 2 An auxiliary layer; step 9: in SiO form 2 The auxiliary layer and the barrier layer are masks for etching the fin-shaped semiconductor, and the SiO is removed 2 An auxiliary layer defining a fin-type semiconductor region uncovered by the barrier layer as an emitter region, and performing ion implantation on the emitter region to form n + An emission region; step 10: removing the barrier layer on the fin-type semiconductor; step 11: deposition of SiO 2 For the SiO 2 Back etching to form SiO 2 Shallow trench isolation, wherein a region of the active region protruding out of the shallow trench isolation is defined as a base region, and ion implantation is carried out on the protruding fin-shaped semiconductor to form a p-type base region; step 12: surface deposition of SiO 2 And Si (Si) 3 N 4 As a stop layer; step 13, depositing SiO on the stop layer 2 Sacrificial layer, photoetching and etching SiO through mask 2 Forming a groove on the sacrificial layer, and exposing the active region; step 14: selectively epitaxially growing Si in the grooves as a collector region; step 15: removing residual SiO 2 Sacrificial layer and Si as stop layer 3 N 4 And SiO 2 Then, ion implantation is carried out on the collector region to form lightly doped n - Ion implantation is carried out on the collector region to form heavily doped n + A collector region; step 16: deposition of SiO 2 Forming a side wall isolation layer in the collector region; step 17: removing SiO in the extrinsic base region of the collector region 2 And epitaxially growing a SiGe strain layer; step 18: forming a base contact over the SiGe strained layer outside the extrinsic base region; step 19: forming a collector contact above the collector region by photolithography and etching a window; step 20: etching SiO over the emitter contact region 2 Layer forming window, depositing polycrystalThe silicon forms the emitter contact.
Another embodiment provided herein is: the substrate is p-type lightly doped monocrystalline silicon, and the doping concentration of the substrate is 10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The hard mask plate is SiO 2 And Si (Si) 3 N 4 。
Another embodiment provided herein is: the SiO is 2 The filler layer is deposited using a plasma chemical vapor deposition process.
Another embodiment provided herein is: said n - The doping concentration of the collector region is 10 16 cm -3 The n is + The doping concentration of the collector region is 10 18 cm -3 The n is + Collector region and the n - The region of the type collector region constitutes an n-type collector region.
Another embodiment provided herein is: said n + The doping concentration of the emitter region is 10 18 cm -3 The doping concentration of the fin type semiconductor p-type base region is 10 16 cm -3 。
3. Advantageous effects
Compared with the prior art, the three-dimensional strain Si bipolar junction transistor and the preparation method thereof have the beneficial effects that:
the three-dimensional strain Si bipolar junction transistor is an NPN type BJT, and the device performance is further improved by applying uniaxial stress. The preparation process flow and the 22nm-FinFET can be integrated on the same substrate, and the preparation process flow and the preparation process are compatible.
The three-dimensional strain Si bipolar junction transistor provided by the application uses the preparation process of the FinFET, is convenient for integration of the two, and enables the performance of the device to be further improved through structural optimization and stress application while the device is miniaturized.
The three-dimensional strain Si bipolar junction transistor provided by the application, n + The emitter region and the fin type semiconductor p-type base region have the same width, and the current edge collecting effect of the emitter junction is effectively restrained.
According to the three-dimensional strain Si bipolar junction transistor, electrons are extracted from the fin-type semiconductor p-type base region in three directions by the n-type collector region, so that the carrier collecting capacity is improved, and the gain of the device is improved.
According to the three-dimensional strain Si bipolar junction transistor, the SiGe strain epitaxial layer is used for simultaneously applying uniaxial tensile stress to the p-type base region and the n-type collector region of the fin-type semiconductor, so that the electron mobility is increased, the transit time of the p-type base region and the n-type collector region of the fin-type semiconductor is reduced, and the characteristic frequency of the device is increased.
Drawings
FIG. 1 is a schematic three-dimensional schematic diagram of a three-dimensional strained Si bipolar junction transistor of the present application;
FIG. 2 is a first schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 3 is a second schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 4 is a third schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 5 is a fourth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 6 is a fifth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 7 is a sixth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 8 is a seventh schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 9 is an eighth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 10 is a ninth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 11 is a tenth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 12 is an eleventh schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 13 is a twelfth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 14 is a thirteenth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 15 is a fourteenth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 16 is a fifteenth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 17 is a sixteenth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 18 is a seventeenth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 19 is an eighteenth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 20 is a schematic illustration of an eighteenth (2) process flow for fabricating a three-dimensional strained Si bipolar junction transistor of the present application;
FIG. 21 is a nineteenth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 22 is a twentieth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 23 is a twenty-first schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 24 is a twenty-second schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 25 is a twenty-third schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
fig. 26 is a twenty-third (2) schematic diagram of a three-dimensional strained Si bipolar junction transistor fabrication process flow of the present application;
FIG. 27 is a twenty-third (3) schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 28 is a twenty-fourth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
fig. 29 is a twenty-fourth (2) schematic diagram of a three-dimensional strained Si bipolar junction transistor fabrication process flow of the present application;
FIG. 30 is a twenty-fifth schematic diagram of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 31 is a twenty-sixth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 32 is a twenty-seventh schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 33 is a twenty-eighth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 34 is a twenty-ninth schematic illustration of a three-dimensional strained Si bipolar junction transistor manufacturing process of the present application;
FIG. 35 is a thirty-first schematic illustration of a three-dimensional strained Si bipolar junction transistor fabrication process of the present application;
fig. 36 is a thirty (2) th schematic illustration of a three-dimensional strained Si bipolar junction transistor fabrication process of the present application.
Detailed Description
Hereinafter, specific embodiments of the present application will be described in detail with reference to the accompanying drawings, and according to these detailed descriptions, those skilled in the art can clearly understand the present application and can practice the present application. Features from various embodiments may be combined to obtain new implementations or to replace certain features from certain embodiments to obtain other preferred implementations without departing from the principles of the present application.
For the small-size BiCMOS manufacturing process, a process generalization is sought between the FinFET device and the bipolar transistor, so that the process is as simple as possible, and the cost is further saved. Therefore, it is important to fabricate small-sized bipolar junction transistors using FinFET fabrication processes.
Referring to fig. 1-36, the present application provides a bipolar junction transistor comprising, in a first direction, a p-type Si substrate, n, disposed in sequence + Emitter region, siO 2 Shallow trench isolation structure, siO 2 The semiconductor device comprises a layer, a fin-type semiconductor p-type base region, a SiGe strain epitaxial layer and an n-type collector region, wherein the first direction is the direction from the substrate to the n-type collector region; the saidThe fin type semiconductor p-type base region is provided with the n-type collector region; the SiO is 2 An emitter contact is arranged on the layer, a base contact is arranged on the SiGe strain epitaxial layer, and a collector contact is arranged on the n-type collector region; the SiGe strain epitaxial layer simultaneously applies uniaxial tensile stress to the fin semiconductor p-type base region and the n-type collector region.
And by means of the epitaxial SiGe layer, uniaxial tensile stress is applied to the base region and the collector region, so that electron mobility is increased, the transit time of the base region and the collector region is reduced, and the characteristic frequency of the device is increased.
Further, the n is + The emitter region and the fin type semiconductor p-type base region have the same width. The emitter region and the base region have the same width, and the current edge collecting effect of the emitter junction is effectively restrained.
Further, the fin-type semiconductor p-type base region comprises an intrinsic base region and an extrinsic base region, the intrinsic base region is in contact with the n-type collector region, the intrinsic base region is wrapped by three sides of the n-type collector region, and the n-type collector region extracts electrons from the fin-type semiconductor p-type base region in three directions; the extrinsic base region is wrapped in the SiGe strain epitaxial layer, and the collector region collects minority carriers of the intrinsic base region from three directions, so that the carrier collection capacity is improved, and the gain of the device is improved.
Further, the n is + The width of the emitting area is 10 nm-20 nm; the width of the Fin type semiconductor n-type base region is 10 nm-20 nm, the height of the Fin type semiconductor n-type base region is 21 nm-41 nm, and the dimension characteristics are the standard parameter range of the active region Fin type semiconductor (Fin) of the 22 nm-FinFET.
The present application also provides a method for fabricating a three-dimensional strained Si bipolar junction transistor, in which steps 1 to 6 are identical to FinFET fabrication methods to ensure that they can be integrated on the same substrate and that the dimensional parameter design for the Fin semiconductor (Fin) of the active region is identical, and the method is compatible with the 22nm Fin field effect transistor fabrication process. Transistors are initially implemented with FinFET processes at 22nm, and 22nm processes or below may be referred to as small-scale devices.
Further, the method packageThe method comprises the following steps: step 1: sequentially depositing a hard mask and a polysilicon auxiliary layer on a substrate; step 2: photoetching and etching the polysilicon auxiliary layer, and depositing SiO (silicon oxide) on the hard mask and the treated polysilicon auxiliary layer 2 A layer; step 3: for the SiO 2 Etching the layer to form SiO 2 The side wall is used for removing the polysilicon auxiliary layer; step 4: in SiO form 2 Etching the side wall downwards to form an active region by using the mask plate as a side wall; step 5: removing the SiO 2 Side wall, deposited SiO 2 A filling layer filling the active region; step 6: for the SiO 2 Back etching the filling layer to make the active region protrude from SiO 2 A surface controlling the fin semiconductor height; removing the hard mask; step 7: processing the fin-type semiconductor to form an emitter contact region; depositing a barrier layer; step 8: treating the barrier layer, and treating the SiO 2 Photoetching and etching the filling layer to form SiO 2 An auxiliary layer; step 9: in SiO form 2 The auxiliary layer and the barrier layer are masks for etching the fin-shaped semiconductor, and the SiO is removed 2 An auxiliary layer defining a fin-type semiconductor region uncovered by the barrier layer as an emitter region, and performing ion implantation on the emitter region to form n + An emission region; step 10: removing the barrier layer on the fin-type semiconductor; step 11: deposition of SiO 2 For the SiO 2 Back etching to form SiO 2 Shallow trench isolation, wherein a region of the active region protruding out of the shallow trench isolation is defined as a base region, and ion implantation is carried out on the protruding fin-shaped semiconductor to form a p-type base region; step 12: surface deposition of SiO 2 And Si (Si) 3 N 4 As a stop layer; step 13, depositing SiO on the stop layer 2 Sacrificial layer, photoetching and etching SiO through mask 2 Forming a groove on the sacrificial layer, and exposing the active region; step 14: selectively epitaxially growing Si in the grooves as a collector region; step 15: removing residual SiO 2 Sacrificial layer and Si as stop layer 3 N 4 And SiO 2 Then, ion implantation is carried out on the collector region to form lightly doped n - Ion implantation is carried out on the collector region to form heavily doped n + Collector regionA region; step 16: deposition of SiO 2 Forming a side wall isolation layer in the collector region; step 17: removing SiO in the extrinsic base region of the collector region 2 And epitaxially growing a SiGe strain layer; step 18: forming a base contact over the SiGe strained layer of the collector region; step 19: forming a collector contact above the collector region by photolithography and etching a window; step 20: etching SiO over the emitter contact region 2 And forming a window by the layer, and depositing polysilicon to form an emitter contact.
Further, the substrate is p-type lightly doped monocrystalline silicon, and the doping concentration of the substrate is 10 15 cm -3 The lightly doped substrate can reduce parasitic effect brought by the lightly doped substrate; the hard mask plate is SiO 2 And Si (Si) 3 N 4 。
Further, the SiO 2 The filling layer is deposited by a plasma chemical vapor deposition method, and the deposition temperature of the deposition method is low, so that the influence on the structure and physical properties of the matrix is small.
Further, the n is - The doping concentration of the collector region is 10 16 cm -3 The n is + The doping concentration of the collector region is 10 18 cm -3 The n is + Collector region and the n - The collector region regions constitute n-type collector regions; said n - The collector region is in direct contact with the base region to form a collector junction, and lightly doped n - The collector region is beneficial to improving the breakdown voltage of the collector junction and increasing the capability of collecting minority carriers of the base region, and the n is that + The collector region is not in direct contact with the base region due to heavy doping, and the resistance of the collector region can be reduced due to heavy doping.
Further, the n is + The emitter region is heavily doped with a doping concentration of 10 18 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The fin type semiconductor p-type base region is lightly doped, and the doping concentration is 10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The heavily doped emitter region can improve the injection efficiency of the transistor compared to the lightly doped base region, which is advantageous to keep the base minority carrier mobility from decreasing to maintain the minority carrier transit time.
Examples
The preparation method of the three-dimensional strain Si bipolar junction transistor is as shown in fig. 1-36, wherein fig. 1 is a perspective view of a device, and the preparation method specifically comprises the following steps:
step 1: p-type doped single crystal Si with crystal orientation of (110) is selected as substrate 101, and the doping concentration is 10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the As in fig. 2.
Step 2: deposition of SiO sequentially on the substrate 101 2 And Si (Si) 3 N 4 As a hard mask 201, wherein, siO 2 The SiO with the thickness of 10nm to 20nm is formed by the growth of a dry oxygen oxidation method 2 A film; wherein Si is 3 N 4 Deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) method, and the thickness is 150 nm-170 nm; as in fig. 3.
Step 3: a polysilicon auxiliary layer 202 is deposited on the hard mask 201. Depositing by a Low Pressure Chemical Vapor Deposition (LPCVD) method, wherein the thickness is 250-300 nm; as in fig. 4.
Step 4: photoetching and etching the polysilicon auxiliary layer 202 in the step 3; as in fig. 5.
Step 5: depositing SiO on the surface of the device structure formed in the step 4 2 203, depositing by a High Density Plasma Chemical Vapor Deposition (HDPCVD) method, controlling the SiO by controlling the deposition time 2 Thickness, thereby controlling width W of Fin type semiconductor (Fin) Fin The method comprises the steps of carrying out a first treatment on the surface of the As in fig. 6.
Preferably, the width W of Fin Fin Is 10nm to 20nm.
Step 6: for SiO described in step 5 2 203 to form SiO by etching 2 Side wall 204, siO 2 The width of the sidewall 204 is W Fin ，Si 3 N 4 As a stop layer; as shown in fig. 7.
Step 7: removing the polysilicon auxiliary layer 202 formed in the step 4; as in fig. 8.
Step 8: using the SiO formed in the step 6 2 The side wall 204 is used as a hard mask, an active region is formed by etching, and the number of the active regions formed by etching is two Fin; as in fig. 9.
Step 9: siO removal 2 Sidewall 204 as shown in fig. 10.
Step 10: deposition of SiO using HDPCVD method 2 A filling layer 205 filling the gaps between the active regions, planarizing the surface by Chemical Mechanical Polishing (CMP), si in the hard mask 201 3 N 4 As a stop layer; as in fig. 11.
Step 11: for SiO 2 Back etching of the filling layer 205 to form SiO 2 Fill layer 206, protruding the active region from the SiO 2 The surface, control the height of Fin through controlling the time of back etching; as in fig. 12.
Preferably, the height H of Fin Fin Corresponding to more than twice of the width, H Fin 21nm to 41nm.
Step 12: removing the hard mask 201; as shown in fig. 13.
Step 13: completely etching Fin of the left protruding surface to define an emitter contact region 301; as in fig. 14.
Step 14: redeposition SiO 2 And Si (Si) 3 N 4 A barrier layer 207 as ion implantation; as in fig. 15.
Step 15: removing the barrier layer in the bottom step 14 by photolithography and etching, and forming a barrier layer 208 on the upper half of Fin; as in fig. 16.
Step 16: after the photoetching and etching in the step 15, siO is exposed 2 Filling layer 206, which is photo-etched and etched by a mask plate to form SiO 2 An auxiliary layer 209; fig. 17 is a right side view of the process, as in fig. 17.
Step 17: at this time, fin on the right side is divided into an upper region and a lower region, and SiO as a barrier layer 208 is formed in the upper half region 2 And Si (Si) 3 N 4 Covering the lower half region with SiO 2 The auxiliary layer 209 is partially covered to laterally etch the lower half of Fin, not covered by SiO 2 All the area covered by the auxiliary layer 209 is etched, so that an I-shaped structure is formed, and the left Fin does not perform any operation on the structure; as in fig. 18, fig. 18 is a right side view of the process.
Step 18: siO removal 2 An auxiliary layer 209 defining an emitter region for the region not covered by the barrier layer 208, andperforming two large-angle ion implantation to form n + An emitter region 102; fig. 19 and 20 are right and front views of the process, respectively.
Preferably, n + The doping concentration of the emitter region is 10 18 cm -3 。
Step 19: removing the barrier layer 208 to expose an active region 401 having the same doping concentration as the substrate; as in fig. 21.
Step 20: deposition of SiO using HDPCVD 2 402 fill the gap and planarize by CMP; as in fig. 22.
Step 21: for the SiO of step 20 2 Back etching to form SiO 2 402 Shallow Trench Isolation (STI) structure 103, the region protruding the STI is defined as the active region 401 as the base region, the height of the active region Fin is controlled by controlling the time of etching back, the height is controlled and the H of step 11 is described Fin The same applies. SiO (SiO) 2 STI structure 103 acts simultaneously as n + An isolation layer of the emitter region, and then p-type ion implantation is carried out on the base region to form a Fin-type base region 105; as shown in fig. 23.
It may be preferable that the doping concentration of the fin semiconductor p-type base region 105 is 10 16 cm -3 。
Step 22: deposition of SiO on the surface 2 And Si (Si) 3 N 4 As a stop layer 210; as in fig. 24.
Step 23: deposition of SiO on stop layer 210 2 The sacrificial layer 211 is deposited with the thickness of 41 nm-61 nm and is more than 20nm higher than the top of the base region; as in fig. 25, fig. 25 is a right side view of the process.
SiO etching through mask 2 The sacrificial layer forms grooves 403 with a length equal to the length of SiO in step 16 2 Length of auxiliary layer 209, etching process Si 3 N 4 As a stop layer, then removing SiO on the base region in the groove 2 And Si (Si) 3 N 4 Exposing the active region, and removing Si at the bottom of the groove 3 N 4 Fig. 26 is a right side view of the process structure.
Si is selectively epitaxially grown in the recessed region as collector region 109, which spans the Fin-type base region, dividing the base region into an intrinsic base region 1051 that is in direct contact with the collector region and an extrinsic base region 1052 that is not in direct contact with the collector region on either side thereof, as shown in the right side view of the process structure in fig. 27.
Step 24: photoetching and etching to remove residual SiO 2 Sacrificial layer and Si as stop layer 3 N 4 And SiO 2 The method comprises the steps of carrying out a first treatment on the surface of the It will be readily appreciated that fig. 28 and 29 are front and right side views, respectively, of the process structure.
Step 25: the collector region 109 is subjected to a first ion implantation to form lightly doped n - The collector region 1091 is then subjected to a second ion implantation from top to bottom to form a heavily doped n with a relatively thin thickness + Collector region regions 1092, n + Collector region and n - The collector region regions constitute n-type collector regions; as in fig. 30.
Preferably, n - The doping concentration of the collector region 1091 is 10 16 cm -3 。
Preferably, n + The doping concentration of the collector region 1092 is 10 18 cm -3 。
Step 26: after the process is finished, siO is deposited on the surface of the device again 2 Layer 104, and forming a sidewall spacer layer in collector region 109 to form an electrical spacer; as in fig. 31.
Step 27: removing SiO on the extrinsic base regions 1052 on either side of the collector region 2 The method comprises the steps of carrying out a first treatment on the surface of the As in fig. 32.
Step 28: epitaxially growing a SiGe strain layer 106 on the extrinsic base region, applying uniaxial tensile stress to the intrinsic base region and the collector region, increasing electron mobility, reducing the transit time of the base region and the collector region, and increasing the device characteristic frequency; two base contacts 108 are formed over the SiGe strained layers on both sides of the collector region, respectively; as in fig. 33.
Step 29: forming a collector contact 110 by photolithography and etching a window over the collector region, through a Salicide (Salicide); as in fig. 34.
Step 30: etching SiO over defined emitter region 301 as described in step 13 2 A layer forming window, depositing polysilicon to form an emitter contact 107; as shown in fig. 35 and 3536, front and right views of the process, respectively.
Although the present application has been described with reference to particular embodiments, those skilled in the art will appreciate that many modifications are possible in the principles and scope of the disclosure. The scope of the application is to be determined by the appended claims, and it is intended that the claims cover all modifications that are within the literal meaning or range of equivalents of the technical features of the claims.

Claims (10)

1. A three-dimensional strained Si bipolar junction transistor, characterized by: in a first direction, comprises a p-type Si substrate and an n-type Si substrate which are arranged in sequence + Emitter region, siO 2 Shallow trench isolation structure, siO 2 The semiconductor device comprises a layer, a fin-type semiconductor p-type base region, a SiGe strain epitaxial layer and an n-type collector region, wherein the first direction is the direction from the substrate to the n-type collector region; the fin-type semiconductor p-type base region is provided with the n-type collector region;
the SiO is 2 An emitter contact is arranged on the layer, a base contact is arranged on the SiGe strain epitaxial layer, and a collector contact is arranged on the n-type collector region;
and the SiC strain epitaxial layer simultaneously applies uniaxial tensile stress to the fin-type semiconductor p-type base region and the n-type collector region.
2. The three-dimensional strained Si bipolar junction transistor of claim 1, wherein: said n + The emitter region and the fin type semiconductor p-type base region have the same width.
3. The three-dimensional strained Si bipolar junction transistor of claim 1, wherein: the fin-type semiconductor p-type base region comprises an intrinsic base region and an extrinsic base region, the intrinsic base region is in contact with the n-type collector region, the intrinsic base region is wrapped by three sides of the n-type collector region, and the n-type collector region extracts electrons from the fin-type semiconductor p-type base region in three directions; the extrinsic base region is encased within a SiGe strained epitaxial layer.
4. The three-dimensional strained Si bipolar junction transistor of claim 2, wherein: said n + The width of the emitting area is 10 nm-20 nm; the width of the fin type semiconductor p-type base region is 10 nm-20 nm, and the height of the fin type semiconductor p-type base region is 21 nm-41 nm.
5. A method of making the three-dimensional strained Si bipolar junction transistor of any of claims 1-4, characterized by: the method is compatible with 22nm fin field effect transistor fabrication processes.
6. The method of manufacturing according to claim 5, wherein: the method comprises the following steps:
step 1: sequentially depositing a hard mask and a polysilicon auxiliary layer on a substrate;
step 2: photoetching and etching the polysilicon auxiliary layer, and depositing SiO (silicon oxide) on the hard mask and the treated polysilicon auxiliary layer 2 A layer;
step 3: for the SiO 2 Etching the layer to form SiO 2 The side wall is used for removing the polysilicon auxiliary layer;
step 4: in SiO form 2 Etching the side wall downwards to form an active region by using the mask plate as a side wall;
step 5: removing the SiO 2 Side wall, deposited SiO 2 A filling layer filling the active region;
step 6: for the SiO 2 Back etching the filling layer to make the active region protrude from SiO 2 A surface controlling the fin semiconductor height; removing the hard mask;
step 7: processing the fin-type semiconductor to form an emitter contact region; depositing a barrier layer;
step 8: treating the barrier layer, and treating the SiO 2 Photoetching and etching the filling layer to form SiO 2 An auxiliary layer;
step 9: in SiO form 2 The auxiliary layer and the barrier layer are used as masks for fin type semiconductorLine etching to remove the SiO 2 An auxiliary layer defining a fin-type semiconductor region uncovered by the barrier layer as an emitter region, and performing ion implantation on the emitter region to form n + An emission region;
step 10: removing the barrier layer on the fin-type semiconductor;
step 11: deposition of SiO 2 For the SiO 2 Back etching to form SiO 2 Shallow trench isolation, wherein a region of the active region protruding out of the shallow trench isolation is defined as a base region, and ion implantation is carried out on the protruding fin-shaped semiconductor to form a p-type base region;
step 12: surface deposition of SiO 2 And Si (Si) 3 N 4 As a stop layer;
step 13, depositing SiO on the stop layer 2 Sacrificial layer, photoetching and etching SiO through mask 2 Forming a groove on the sacrificial layer, and exposing the active region;
step 14: selectively epitaxially growing Si in the grooves as a collector region;
step 15: removing residual SiO 2 Sacrificial layer and Si as stop layer 3 N 4 And SiO 2 Then, ion implantation is carried out on the collector region to form a lightly doped n-type collector region, and ion implantation is carried out on the collector region to form a heavily doped n + A collector region;
step 16: deposition of SiO 2 Forming a side wall isolation layer in the collector region;
step 17: removing SiO in the extrinsic base region of the collector region 2 And epitaxially growing a SiGe strain layer;
step 18: forming a base contact over the SiGe strained layer outside the extrinsic base region;
step 19: forming a collector contact above the collector region by photolithography and etching a window;
step 20: etching SiO over the emitter contact region 2 And forming a window by the layer, and depositing polysilicon to form an emitter contact.
7. The method of manufacturing according to claim 6, wherein: the substrateIs p-type doped monocrystalline silicon, the doping concentration of the substrate is 10 15 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The hard mask plate is SiO 2 And Si (Si) 3 N 4 。
8. The method of manufacturing according to claim 6, wherein: the SiO is 2 The filler layer is deposited using a plasma chemical vapor deposition process.
9. The method of manufacturing according to claim 6, wherein: said n — The doping concentration of the collector region is 10 16 cm -3 The n is + The doping concentration of the collector region is 10 18 cm -3 The n is + Collector region and the n — The region of the type collector region constitutes an n-type collector region.
10. The production method according to any one of claims 6 to 9, characterized in that: said n + The doping concentration of the emitter region is 10 18 cm -3 The doping concentration of the fin type semiconductor p-type base region is 10 16 cm -3 。
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