CN115831752A - Semiconductor device and preparation method thereof - Google Patents

Abstract

The application provides a semiconductor device and a method for manufacturing the same, the device comprising: a second portion of the substrate; a void layer on one side of the second portion of the substrate; the nanosheet stacked layer is positioned on one side, away from the second partial substrate, of the cavity layer; the nanosheet stacked layer includes a stack of a plurality of nanosheets; the nanosheets being formed of a semiconductor material; the lamination formed by the nanosheets forms a plurality of conductive channels; a surrounding gate surrounding the perimeter of the nanosheet stack; source and drain electrodes positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, the influence of the bottom parasitic channel effect can be avoided by arranging the cavity layer, so that the influence of leakage current and grid capacitance is reduced, and the electrical performance of the device can be further improved. The influence brought by the self-heating effect in the stacked nanosheets can be well solved. The leakage induced barrier lowering effect is effectively reduced, and parameters such as sub-threshold slope, on-off ratio and the like are improved.

Description

Semiconductor device and preparation method thereof

Technical Field

The present disclosure relates to semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

With the continuous shrinking of the characteristic dimension of the transistor, the performance of the device is improved by continuously introducing new materials, new processes and new structures, and meanwhile, the influence of a short channel effect caused by the size shrinking is reduced. The structure of the device is changed from a two-dimensional planar Metal Oxide Semiconductor (CMOS) device to a three-dimensional FinFET (Fin-Field-Effect Transistor) structure, and reaches the mainstream Nanowire/nanoshell Nanowire/Nanosheet ring-gate Transistor at present.

Gate-all-around transistors are considered to be one of the most promising next generation devices to replace FinFET devices under the 3nm technology node for mass production. The Effective gate width/Footprint of the ring gate device is effectively increased, the control capability of the gate on the channel is improved, the short channel effect can be effectively inhibited, and the current driving capability of the device is improved.

Currently, the research progress of nanoshiet-GAAFET (nanoshiet-Gate-all-around Field-Effect Transistor) is receiving wide attention from both academia and industry. The continuous optimization of the process flow and the key process and the exploration of a new structure based on the structure are also the popular research direction of a novel CMOS device.

The nanoshiet-GAAFET can improve the performance of the device by overlapping the number of the nanosheets. The novel device structure can be well compatible with the current mainstream FinFET process. However, due to the inevitable parasitic channel existing under the intrinsic channel of the nsefet (nano Field-Effect Transistor) and the FinFET (fin Field Effect Transistor), the parasitic channel has the influence of parasitic capacitance and leakage current, which causes the degradation of the electrical performance of the device, and also brings great challenges to the scaling of the Transistor. Since the parasitic channel of an NSFET is wider, it is affected more significantly by the parasitic channel. How to reduce the effect of the parasitic channel becomes a non-negligible problem.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for preventing the influence of bottom parasitic channel effect, so as to reduce the influence of leakage current and gate capacitance, and further increase the electrical performance of the device.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:

providing an initial substrate;

injecting inert gas into the initial substrate, and performing annealing treatment to form a cavity layer so as to divide the initial substrate into a first partial substrate and a second partial substrate;

epitaxially growing a superlattice lamination on the surface, opposite to the cavity layer, of the first partial substrate, far away from the cavity layer; the superlattice lamination is formed by alternately laminating a first semiconductor layer and a second semiconductor layer;

etching the superlattice lamination to form a plurality of fins;

depositing a dummy gate on the fin;

etching two ends of the fin to the surface of the initial substrate, and epitaxially growing source and drain electrodes at two ends of the etched fin, wherein the source and drain electrodes are made of a semiconductor material doped with conductive elements;

removing the false gate, etching the first semiconductor layer, and realizing the channel release of the second semiconductor layer nanosheet, wherein the nanosheet-formed stack constitutes a plurality of conductive channels;

forming a surrounding grid electrode surrounding the periphery of the nanosheet stacked layer;

and etching to remove the first part of the substrate.

In one possible implementation manner, the etching to remove the first portion of the substrate includes:

and etching to form at least one etching through hole connected with the cavity layer, and etching to remove the first part of the substrate through the etching through hole.

In one possible implementation manner, the etching to remove the first portion of the substrate includes:

and removing the first part of the substrate by wet etching.

In a possible implementation manner, after the etching to remove the first part of the substrate, the method further includes:

and filling the first part of the substrate and the hollow hole layer with gas and/or liquid medium with the medium constant less than or equal to a preset threshold value.

In one possible implementation, the etching the superlattice laminate to form a plurality of fins includes:

arranging a first side wall on the superlattice lamination; and etching the superlattice lamination by using the first side walls as masks to form the plurality of fins.

In a second aspect, embodiments of the present application provide a semiconductor device, including:

a second portion of the substrate;

the hollow hole layer is positioned on one side of the second partial substrate;

a nanosheet stack layer located on a side of the void layer remote from the second portion of the substrate; the nanoplatelet stack comprises a stack of a plurality of nanoplatelets; the nanoplatelets are formed from a semiconductor material; the stacks formed by the nanosheets form a plurality of conductive channels;

a wrap-around gate surrounding the perimeter of the nanosheet stack;

the source and drain electrodes are positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements.

In one possible implementation manner, the method further includes: and shallow trench isolation positioned between the cavity layer and the surrounding grid.

In one possible implementation manner, the method further includes: and the isolation layer is positioned on one side of the source and the drain, which is far away from the cavity layer.

In one possible implementation manner, the method further includes: and the second side wall is positioned between the isolation layer and the surrounding type grid electrode.

In one possible implementation, the types of devices include: the positive channel nanosheets surround the gate field effect transistor or the negative channel nanosheets surround the gate field effect transistor.

Compared with the prior art, the method has the following beneficial effects:

the embodiment of the application provides a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: a second portion of the substrate; a void layer on one side of the second portion of the substrate; the nanosheet stacked layer is positioned on one side, away from the second partial substrate, of the cavity layer; the nanosheet stack comprises a stack of a plurality of nanosheets; the nanosheets being formed of a semiconductor material; the lamination formed by the nanosheets forms a plurality of conductive channels; a surrounding gate surrounding the perimeter of the nanosheet stack; source and drain electrodes positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, the cavity layer is arranged, the influence of the bottom parasitic channel effect can be avoided, the influence of leakage current and grid capacitance is reduced, and the electrical performance of the device can be further improved. The influence brought by the self-heating effect in the stacked nanosheets can be well solved. The leakage induced barrier lowering effect is effectively reduced, and parameters such as sub-threshold slope, on-off ratio and the like are improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

FIGS. 2-13 illustrate cross-sectional views of structures in the fabrication of a semiconductor device provided by embodiments of the present application;

fig. 14 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

fig. 15 shows a top view of a semiconductor device provided in an embodiment of the present application.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.

As described in the background, with the shrinking of the feature size of the transistor, new materials, new processes and new structures are introduced to improve the device performance and reduce the short channel effect caused by the shrinking of the feature size. The structure of the device is changed from a two-dimensional planar Metal Oxide Semiconductor (CMOS) device to a three-dimensional FinFET (Fin-Field-Effect Transistor) structure, and reaches the mainstream Nanowire/nanoshell Nanowire/Nanosheet ring-gate Transistor at present.

Gate-all-around transistors are considered to be one of the most promising next generation devices to replace FinFET devices in the 3nm technology node to achieve mass production. The Effective gate width/Footprint of the ring gate device is effectively increased, the control capability of the gate on the channel is improved, the short channel effect can be effectively inhibited, and the current driving capability of the device is improved.

Currently, the research progress of nanoshiet-GAAFET (nanoshiet-Gate-all-around Field-Effect Transistor) is receiving wide attention from both academia and industry. The continuous optimization of the process flow and the key process and the exploration of a new structure based on the structure are also the popular research direction of a novel CMOS device.

The nanoshiet-GAAFET can improve the performance of the device by overlapping the number of the nanosheets. The novel device structure can be well compatible with the current mainstream FinFET process. However, due to the inevitable parasitic channel existing under the intrinsic channel of the nsefet (nano Field-Effect Transistor) and the FinFET (fin Field Effect Transistor), the parasitic channel has the influence of parasitic capacitance and leakage current, which causes the degradation of the electrical performance of the device, and also brings great challenges to the scaling of the Transistor. Since the parasitic channel of an NSFET is wider, it is affected more significantly by the parasitic channel. How to reduce the effect of the parasitic channel becomes a non-negligible problem.

In addition, how to effectively reduce the drain induced barrier lowering effect and improve parameters such as subthreshold slope and on-off ratio is also a technical problem to be solved in the field.

In order to solve the above technical problem, embodiments of the present application provide a semiconductor device and a method for manufacturing the same, the device including: a second portion of the substrate; a void layer on one side of the second portion of the substrate; the nanosheet stacked layer is positioned on one side, away from the second partial substrate, of the cavity layer; the nanosheet stack comprises a stack of a plurality of nanosheets; the nanosheets being formed of a semiconductor material; the lamination formed by the nanosheets forms a plurality of conductive channels; a surrounding gate surrounding the perimeter of the nanosheet stack; source and drain electrodes positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, the influence of the bottom parasitic channel effect can be avoided by arranging the cavity layer, so that the influence of leakage current and grid capacitance is reduced, and the electrical performance of the device can be further improved. The influence brought by the self-heating effect in the stacked nanosheets can be well solved. The leakage induced barrier lowering effect is effectively reduced, and parameters such as sub-threshold slope, on-off ratio and the like are improved.

Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application includes:

s101: an initial substrate is provided.

In the embodiment of the present application, referring to fig. 2, an initial substrate 0 may be prepared first, and the initial substrate 0 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, inP, siC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In this embodiment, the initial substrate 0 is a bulk silicon substrate.

Specifically, the initial substrate 0 is a portion of a semiconductor wafer suitable for forming one or more semiconductor devices, and when a bulk silicon substrate is used, highly doped well regions are formed in the bulk silicon substrate by implanting impurities, diffusing, and annealing to achieve a desired well depth. For P (positive) type FET, the highly doped well region is an N well, and the implanted impurity is N-type impurity ions, such as phosphorus (P) ions; in the case of N (negative) type FET, the highly doped well region is a P-well, and the implanted impurity is P-type impurity ions, such as boron (B) ions.

S102: and injecting inert gas into the initial substrate, and annealing to form a hollow layer so as to divide the initial substrate into a first partial substrate and a second partial substrate.

In the embodiment of the present application, referring to fig. 3, an inert gas, such as ammonia, may be injected into the initial substrate and annealed in a high temperature inert gas atmosphere to form a void layer 1, so as to divide the initial substrate into a first partial substrate 0' and a second partial substrate 0 ″.

A silicon dioxide layer 11 is grown on the surface of the first partial substrate 0'.

S103: epitaxially growing a superlattice lamination on the surface, opposite to the cavity layer, of the first partial substrate, far away from the cavity layer; the superlattice laminate is formed by alternately laminating a first semiconductor layer and a second semiconductor layer.

In the embodiment of the present application, referring to fig. 4, silicon dioxide (SiO 2) on the surface of the first partial substrate 0 'is removed, and a stack of multiple periods of a superlattice structure of the first semiconductor layer 51/the second semiconductor layer 52 is epitaxially grown on the first partial substrate 0'; the thickness of the first semiconductor layer 51 in the superlattice structure can be set to be 3-100nm, the thickness of the second semiconductor layer 52 in the superlattice structure can be set to be 1-50nm, and the finally produced thickness directly determines the height of a nanosheet channel and the electrostatic performance.

The superlattice of the first semiconductor layer 51/the second semiconductor layer 52 may be a Si/SiGe stack, a SiGe/Si stack, a SiGe/Ge stack, a Ge/SiGe stack, a Si/Ge stack, or a Ge/Si stack.

S104: and etching the superlattice lamination to form a plurality of fins.

In the embodiment of the present application, referring to fig. 5, in a possible implementation manner, a first sidewall 61 may be disposed on the superlattice laminate; the superlattice stack is etched using the first sidewalls 61 as a mask to form a plurality of fins.

Specifically, a nanoscale first sidewall 61 device may be formed by a Self-aligned sidewall transfer (SIT) process, the first sidewall 61 may be made of silicon nitride (SiNX), and the specific forming process is as follows: covering a sacrificial layer 62 on the superlattice lamination, wherein the sacrificial layer can be polysilicon (PolySi, p-si) or amorphous silicon (a-si), etching off part of the sacrificial layer 62, depositing a silicon nitride (SiNx) layer, and then etching off the rest of the sacrificial layer 62 by adopting anisotropic etching so that the sacrificial layer only remains on a plurality of periodic silicon nitride (SiNx) first side walls (spacers) 61 on the superlattice lamination, wherein the silicon nitride (SiNx) first side walls 61 play a role of a Hard Mask (Hard Mask) in photoetching.

Referring to fig. 6, the epitaxially grown superlattice stack may be etched into a plurality of periodically distributed fins.

Specifically, the first sidewall 61 is used as a mask to perform etching, so as to form a fin having a superlattice laminated structure. The upper part of the fin is a conductive channel region formed by the superlattice laminate, and the lower part of the fin is a first part of the substrate 0', so that the fin shown in fig. 6 is formed.

The fin includes not only a superlattice stack structure but also a single crystal silicon structure deep into the substrate. The etching process may be a dry etching process, and Reactive Ion Etching (RIE) may be used in one embodiment. The fins will be used to form one or more horizontal nanoplates of n-type field effect transistors and/or p-type field effect transistors.

It should be noted that although one fin is shown in fig. 6, it should be understood that any suitable number and configuration of fins may be used in embodiments of the present application. The fin has a height of about 10nm to 400nm and a width of about 1 nm to 100nm.

As shown in fig. 7, the first sidewall 61 is etched away, and then a Shallow Trench Isolation (STI) region 7 may be formed between two adjacent fins. A dielectric insulating material is deposited, followed by planarization, such as a CMP (chemical mechanical polishing) process, and then a selective etching back of the dielectric insulating material is performed to expose the three-dimensional fin structure, thereby forming the shallow trench isolation 7 adjacent to the fin.

The upper surface of the shallow trench isolation region 7 is generally flush with the interface between the superlattice stack structure in the fin and the substrate monocrystalline silicon, and can be higher or lower than the horizontal line of the interface. The shallow trench isolation 7 may be formed of a suitable dielectric material, such as silicon dioxide (SiO 2), silicon nitride (SiNx), etc. The shallow trench isolation regions 7 serve to separate transistors on adjacent fins. The shallow trench isolation region 7 exposes the first semiconductor layer 51 of the lowermost layer of the superlattice stack.

S105: a dummy gate is deposited over the fin.

In the embodiment of the present application, referring to fig. 8, a dummy gate 8 may be formed on the exposed fin in a direction perpendicular to the fin line (i.e., a B-B' direction), and the dummy gate 8 may be formed by using a thermal oxidation, a chemical vapor deposition (cvd), a sputtering (sputtering), or other processes. The dummy gate 8 crosses the superlattice stack on the upper portion of the fin, and a plurality of dummy gates 8 are periodically distributed along the direction of the fin line.

The material used for the dummy gate 8 may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).

S106: and etching the two ends of the fin to the surface of the initial substrate, and epitaxially growing source and drain electrodes at the two ends of the etched fin, wherein the source and drain electrodes are made of semiconductor materials doped with conductive elements.

In the embodiment of the present application, referring to fig. 9, a silicon nitride or doped silicon oxide material may be deposited and etched on both sides of each dummy gate 8 to form the second sidewalls 9.

Then, referring to fig. 10, the two ends of the fin may be etched to the surface of the initial substrate, and source and drain electrodes 41/42 are epitaxially grown at the two ends of the etched fin, where the material of the source and drain electrodes 41/42 is a semiconductor material doped with a conductive element.

Specifically, the heavily doped source/drain 41/42 may be formed by depositing a semiconductor material such As SiGe or Si and heavily doping the semiconductor material, using a doping element of B or BF2 for a P-type semiconductor device, and using a doping element of P/As for an N-type semiconductor device. Low temperature rapid thermal annealing is used to activate the impurities for the source and drain 41/42.

S107: and removing the false gate, etching the first semiconductor layer, and realizing the channel release of the second semiconductor layer nanosheet, wherein the nanosheet stack is formed into a plurality of conductive channels.

In the embodiment of the present application, referring to fig. 11, an isolation layer 10 may be deposited on the source/drain electrodes 41/42, and the material of the isolation layer 10 may be an oxide such as silicon dioxide.

Then, the aforementioned polycrystalline silicon (PolySi, p-si) or amorphous silicon is etched by a selective etching or etching process

The dummy gate 8 formed of silicon (a-si) is etched or etched away, i.e. the dummy gate 8 is removed.

Subsequently, as shown in fig. 12, the first semiconductor layer 51 in the superlattice stack is selectively etched to perform nanosheet 2 (nanoshiet) channel release. And etching/corroding the exposed conductive channel region of the fin, removing each layer of the first semiconductor layer 51, wherein the first semiconductor layer 51 is a sacrificial layer, and releasing the nanosheet 2 formed by the second semiconductor layer.

The width range of the nano-sheets 2 is 1-100nm, the thickness range is 1-50nm, and the interval range between the nano-sheets 2 is 3-100nm.

In one embodiment, for both P-type and N-type FETs, the sacrificial layer is a SiGe layer, which is selectively removed, leaving the Si layer, forming a Si-level stacked nanosheet stack device. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, the nanosheet channel is released by isotropically etching the sacrificial layer using a conventional wet process to form a nanosheet conductive channel.

In another embodiment, channel releases are performed separately for P-type and N-type FETs.

For a P-type FET, the sacrificial layer is a Si layer, the Si layer is selectively removed, the SiGe layer is reserved, and a SiGe horizontal laminated nanosheet stack device is formed. An etchant that selectively etches Si at a faster rate relative to SiGe can be used in the selective removal process. In one embodiment, the nanosheet conductive channel is formed by a conventional wet process that isotropically etches the sacrificial layer for nanosheet channel release.

For an N-type FET, the sacrificial layer is a SiGe layer, the SiGe layer is selectively removed, the Si layer is reserved, and a Si horizontal laminated nanosheet stack device is formed. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, the nanosheet conductive channel is formed by a conventional wet process that isotropically etches the sacrificial layer for nanosheet channel release. The second semiconductor nano-layer sheet 2 is laminated to form a nano-sheet stacked layer.

Next, as shown in fig. 12, a high K dielectric layer 12 is deposited, such that the high K dielectric layer 12 surrounds the surface of the nanosheet stack layer and covers the surface of the second sidewall 9. The high-K dielectric layer 12 may have a dielectric constant higher than about 6.0, and the material of the high-K dielectric layer 12 may be one or a combination of several selected from HfO2, hfSiOx, hfON, hfSiON, hfAlOx, hfLaOx, al2O3, zrO2, zrSiOx, ta2O5 and La2O 3.

S108: and forming a surrounding grid which surrounds the nanosheet stacked layer.

In the embodiment of the present application, referring to fig. 13, a metal gate 3 is deposited outside a high-K dielectric layer 12 in a space formed by a dummy gate 8, so as to form a multi-layer high-K/metal gate structure.

The metal gate 3 comprises a covering layer, a blocking layer, a work function layer and a filling layer in a multilayer structure. Film structures with different effective work functions can be formed through selective photoetching and corrosion so as to regulate and control the threshold value of the device. The metal gate 3 is typically formed by a chemical vapor deposition process, a physical vapor deposition process, or the like.

The metal grid 3 is made of one or a combination of more of TaC, taN, tiN, taTbN, taErN, taYbN, taSiN, hfSiN, moSiN, ruTax, niTax, moNx, tiSiN, tiCN, taAlC, tiAl, tiAlC, tiAlN, ptSix, ni3Si, pt, ru, ir, mo, ti, al, W, co, cr, au, cu, ag, hfRu or RuOx.

As shown in fig. 13, the metal gate 3 fills the space after the dummy gate 8 is removed. And then, carrying out chemical mechanical polishing on the high-K dielectric layer 12 and the metal gate 3 structure to flatten the structures, and removing the redundant high-K dielectric layer 12 and the metal gate 3 material exposed on the surface of the dielectric layer outside the space of the dummy gate 8. The high-K dielectric layer 12 and the metal gate 3 are filled in the space of the original first semiconductor layer 51 to form a surrounding gate structure, i.e., a surrounding gate, which surrounds the nanosheets 2.

S109: and etching to remove the first part of the substrate.

In the embodiment of the present application, referring to fig. 15, a top view of a semiconductor device provided in the embodiment of the present application includes a device region, a wet-etched Si substrate region, an etched via, and a Si substrate region.

A-A 'is along the central line of the fin line, B-B' is perpendicular to the central line of the fin line, and the attached figures 2-14 are cross-sectional schematic views of A-A 'and B-B'.

Referring to fig. 14, at least one etched via associated with the void layer may be etched, and the first portion of the substrate may be removed by etching the etched via. Optionally, the first portion of the substrate may be removed by wet etching.

For example, the selective removal of bulk silicon material, i.e., the first portion of the substrate, may be performed by wet etching by adjusting the etch selectivity of the Si substrate to SiGe and SiO 2. The method comprises the steps of forming an etched through hole from the top to the bottom by adding an etching layout, and then selectively removing a sub-Fin parasitic channel and bulk silicon material below STI by wet etching.

According to the embodiment of the application, the speed of selectively removing wet etching can be increased by adding the SON (silicon on nothing) substrate structure. The time and the rate of the wet etching are controlled, so that the thickness of the bulk silicon material to be removed is controlled.

Optionally, after the etching to remove the first portion of the substrate, the method further includes:

and filling the first part of the substrate and the cavity layer with gas and/or liquid medium with the medium constant less than or equal to the preset threshold value, so that the influence caused by the self-heating effect in the stacked nanosheets can be well solved.

According to the embodiment of the application, the influence caused by the bottom parasitic channel effect is reduced by combining the conventional Nanashet-GAAFET preparation method on the SON substrate and forming the SON substrate structure, so that the electrical performance of the device can be improved.

The application provides a preparation method of a semiconductor device, and the device prepared by the method comprises the following steps: a second portion of the substrate; a void layer on one side of the second portion of the substrate; the nanosheet stacked layer is positioned on one side, away from the second partial substrate, of the cavity layer; the nanosheet stack comprises a stack of a plurality of nanosheets; the nanosheets being formed of a semiconductor material; the stacks formed by the nanosheets form a plurality of conductive channels; a surrounding gate surrounding the perimeter of the nanosheet stack; source and drain electrodes positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, the influence of the bottom parasitic channel effect can be avoided by arranging the cavity layer, so that the influence of leakage current and grid capacitance is reduced, and the electrical performance of the device can be further improved. The influence brought by the self-heating effect in the stacked nanosheets can be well solved. The leakage induced barrier lowering effect is effectively reduced, and parameters such as sub-threshold slope, on-off ratio and the like are improved.

Exemplary device

Referring to fig. 14, a schematic diagram of a semiconductor device provided in an embodiment of the present application includes:

second partial substrate 0";

a cavity layer 1 positioned at one side of the second partial substrate 0';

a nanosheet stack layer located on the side of the void layer 1 remote from the second partial substrate 0'; the nanosheet stack comprises a stack of a plurality of nanosheets 2; the nanoplatelets 2 are formed of a semiconductor material; the stack of nanosheets 2 constitutes a plurality of conductive channels;

a surrounding grid 3 surrounding the periphery of the stacked layers of nanosheets 2;

source and drain electrodes 41/42 which are positioned at two ends of the nanosheet stack layer; the source and drain electrodes 41/42 are made of a semiconductor material doped with a conductive element.

In one possible implementation manner, the method further includes: shallow trench isolation 7 located between the void layer 1 and the surrounding gate 3.

In one possible implementation manner, the method further includes: and the isolation layer 10 is positioned on one side of the source and drain electrodes 41/42, which is far away from the cavity layer 1.

In one possible implementation manner, the method further includes: and a second sidewall 9 between the isolation layer 10 and the surrounding gate 3.

In one possible implementation, the types of devices include: the positive channel nanosheets surround the gate field effect transistor or the negative channel nanosheets surround the gate field effect transistor.

An embodiment of the present application provides a semiconductor device, including: a second portion of the substrate; a void layer on one side of the second portion of the substrate; the nanosheet stacked layer is positioned on one side, away from the second partial substrate, of the cavity layer; the nanosheet stack comprises a stack of a plurality of nanosheets; the nanosheets being formed of a semiconductor material; the lamination formed by the nanosheets forms a plurality of conductive channels; a surrounding gate surrounding the perimeter of the nanosheet stack; source and drain electrodes positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, the influence of the bottom parasitic channel effect can be avoided by arranging the cavity layer, so that the influence of leakage current and grid capacitance is reduced, and the electrical performance of the device can be further improved. The influence brought by the self-heating effect in the stacked nanosheets can be well solved. The drain induced barrier lowering effect is effectively reduced, and parameters such as sub-threshold slope, on-off ratio and the like are improved.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, they are described relatively simply, and reference may be made to some descriptions of the method embodiments for relevant points.

The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can make numerous possible variations and modifications to the disclosed solution, or modify it to equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

providing an initial substrate;

injecting inert gas into the initial substrate, and performing annealing treatment to form a cavity layer so as to divide the initial substrate into a first partial substrate and a second partial substrate;

epitaxially growing a superlattice lamination on the surface, opposite to the cavity layer, of the first partial substrate, far away from the cavity layer; the superlattice lamination is formed by alternately laminating a first semiconductor layer and a second semiconductor layer;

etching the superlattice lamination to form a plurality of fins;

depositing a dummy gate on the fin;

etching two ends of the fin to the surface of the initial substrate, and epitaxially growing a source drain at two ends of the etched fin, wherein the source drain is made of a semiconductor material doped with a conductive element;

removing the false gate, etching the first semiconductor layer, and realizing the channel release of the second semiconductor layer nanosheet, wherein the nanosheet-formed stack constitutes a plurality of conductive channels;

forming a surrounding grid surrounding the periphery of the nanosheet stacked layer;

and etching to remove the first part of the substrate.

2. The method of claim 1, wherein the etching to remove the first portion of the substrate comprises:

and etching to form at least one etching through hole connected with the cavity layer, and etching to remove the first part of the substrate through the etching through hole.

3. The method of claim 2, wherein the etching to remove the first portion of the substrate comprises:

and removing the first part of the substrate by wet etching.

4. The method of claim 1, further comprising, after etching away the first portion of the substrate:

and filling the first part of the substrate and the cavity layer with gas and/or liquid medium with the medium constant less than or equal to a preset threshold value.

5. The method of claim 1, wherein the etching the superlattice stack to form a plurality of fins comprises:

arranging a first side wall on the superlattice lamination; and etching the superlattice lamination by using the first side walls as masks to form the plurality of fins.

6. A semiconductor device, comprising:

a second portion of the substrate;

the hollow hole layer is positioned on one side of the second partial substrate;

a nanosheet stack layer located on a side of the void layer remote from the second portion of the substrate; the nanoplatelet stack comprises a stack of a plurality of nanoplatelets; the nanoplatelets are formed from a semiconductor material; the stacks formed by the nanosheets form a plurality of conductive channels;

a wrap-around gate surrounding the perimeter of the nanosheet stack;

the source and drain electrodes are positioned at two ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements.

7. The device of claim 6, further comprising: and shallow trench isolation positioned between the cavity layer and the surrounding grid.

8. The device of claim 6, further comprising: and the isolation layer is positioned on one side of the source and the drain, which is far away from the cavity layer.

9. The device of claim 8, further comprising: and the second side wall is positioned between the isolation layer and the surrounding type grid electrode.

10. The device of claim 6, wherein the types of devices comprise: the positive channel nanosheets surround the gate field effect transistor or the negative channel nanosheets surround the gate field effect transistor.

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