CN109962017A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN109962017A CN109962017A CN201711404925.2A CN201711404925A CN109962017A CN 109962017 A CN109962017 A CN 109962017A CN 201711404925 A CN201711404925 A CN 201711404925A CN 109962017 A CN109962017 A CN 109962017A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000002955 isolation Methods 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 21
- 230000003628 erosive effect Effects 0.000 claims description 2
- 230000001939 inductive effect Effects 0.000 description 19
- 239000000463 material Substances 0.000 description 10
- 230000008901 benefit Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor devices and forming method thereof, wherein method includes: offer semiconductor substrate；Isolation structure is formed on the semiconductor substrate；Fin is formed on the semiconductor substrate, fin includes the firstth area and the secondth area in the firstth area, the side wall in firstth area of fin is isolated structure covering, and the side wall in the secondth area of fin is isolated structure and is completely exposed, on fin width direction, the size of bottom is less than the size at the top in the firstth area of fin in secondth area of fin；The gate structure in the secondth area of fin is developed across on isolation structure.The method improves the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
MOS transistor is one of most important element in modern integrated circuits.The basic structure of MOS transistor includes: half
Conductor substrate；Source region and position positioned at the gate structure of semiconductor substrate surface, in the semiconductor substrate of gate structure side
Drain region in the semiconductor substrate of the gate structure other side.The working principle of MOS transistor is: by applying electricity in gate structure
Pressure adjusts and generates switching signal by the electric current of gate structure bottom channel.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.And fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin and the gate structure of sidewall surfaces described in covering part are located at grid
Source region in the fin of pole structure side and the drain region in the fin of the gate structure other side.
However, the performance for the semiconductor devices that fin formula field effect transistor is constituted in the prior art is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method thereof, to improve the property of semiconductor devices
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide semiconductor lining
Bottom；Isolation structure is formed on the semiconductor substrate；Form fin on the semiconductor substrate, fin include the firstth area and
The secondth area in the firstth area, the side wall in firstth area of fin are isolated structure covering, and the side wall quilt in the secondth area of fin
Isolation structure is completely exposed, and on fin width direction, the size of bottom is less than in the firstth area of fin in secondth area of fin
Top size；The gate structure in the secondth area of fin is developed across on isolation structure.
Optionally, further includes: before forming the isolation structure, form initial fin on a semiconductor substrate；It is formed
After the isolation structure, isolation structure covers the partial sidewall of initial fin；The initial fin that the isolation structure is exposed
Side wall perform etching, so that initial fin is formed the fin.
Optionally, the bottom width of the initial fin is greater than the top width of initial fin.
Optionally, the initial fin that the isolation structure exposes includes the first exposed region and on the first exposed region
Second exposed region；During the side wall of the initial fin exposed to isolation structure performs etching, wide along initial fin
It spends on direction, the average etch size to the second exposed region is greater than to the average etch size of the first exposed region.
Optionally, during the side wall of the initial fin exposed to isolation structure performs etching, initial fin
The smaller region of the distance of sidewall surfaces to semiconductor substrate surface along initial fin width direction by the size etched
It is bigger.
Optionally, the technique that the side wall of the initial fin exposed to isolation structure performs etching is dry carving technology, parameter
The gas for including: use includes NF3、H2And He, NF3Flow be 5sccm~15sccm, H2Flow be 30sccm~
The flow of 50sccm, He be 4500sccm~6000sccm, source radio-frequency power be 28 watts~35 watts, chamber pressure be 0torrr~
0.05torr。
Optionally, during the side wall of the initial fin exposed to isolation structure performs etching, along initial fin
It is equal to the etching size of the sidewall surfaces of initial fin everywhere in portion's width direction.
Optionally, the technique that the side wall of the initial fin exposed to isolation structure performs etching is dry carving technology, parameter
The gas for including: use includes NF3、H2And He, NF3Flow be 180sccm~220sccm, H2Flow be 3600sccm~
The flow of 3800sccm, He are 2200sccm~2300sccm, and source radio-frequency power is 220 watts~300 watts, and chamber pressure is
2torrr~5torr.
Optionally, the method for forming the isolation structure includes: to be formed to cover initial fin on the semiconductor substrate
The isolation structure film of side wall；It is etched back to isolation structure film, isolation structure film is made to form the isolation structure.
Optionally, the method for being etched back to isolation structure film includes: be etched back to for the first time to isolation structure film, is exposed
The partial sidewall of initial fin；It carries out after being etched back to for the first time, isolation structure film is etched back to for the second time, makes isolation structure
Film forms the isolation structure；The forming method of the semiconductor devices further include: carry out after being etched back to for the first time, and carrying out
Before being etched back to for the second time, the round and smooth processing in surface is carried out to the initial fin that isolation structure film exposes.
Optionally, the round and smooth processing in the surface includes annealing.
Optionally, the parameter of the annealing includes: the gas that uses for N2And H2One of or both combination,
Annealing temperature is 800 degrees Celsius~1000 degrees Celsius, and annealing pressure is 5torr~50torr.
Optionally, on fin width direction, the size at top is bottom in the secondth area of fin in firstth area of fin
1.2 times~1.5 times of size.
Optionally, on fin width direction, the size at top is 5nm~50nm, the fin in firstth area of fin
The size of bottom is 2nm~30nm in the secondth area, portion.
Optionally, further includes: be respectively formed source and drain doping area in the secondth area of fin of the gate structure two sides.
Optionally, further includes: after forming fin, and before forming gate structure, isolation structure is etched back,
The surface of isolation structure is set to be lower than the interface in fin the firstth area and the secondth area；After forming gate structure, gate structure is also covered
The partial sidewall surface in the firstth area of fin.
The present invention also provides a kind of semiconductor devices, comprising: semiconductor substrate；Fin in the semiconductor substrate
Portion, fin includes the firstth area in semiconductor substrate and the secondth area in the firstth area, on fin width direction, institute
The size for stating bottom in the secondth area of fin is less than the size at top in the firstth area of fin；Isolation in the semiconductor substrate
Structure, the side wall in isolation structure covering the firstth area of fin, and the surface of isolation structure are lower than or are flush to the firstth area and the
The interface in 2nd area；Gate structure on isolation structure and across the secondth area of fin.
Optionally, on fin width direction, the size at top is bottom in the secondth area of fin in firstth area of fin
1.2 times~1.5 times of size.
Optionally, on fin width direction, the size at top is 5nm~50nm, the fin in firstth area of fin
The size of bottom is 2nm~30nm in the secondth area, portion.
Optionally, further includes: source and drain doping area, the source and drain doping area are located at the fin of the gate structure two sides
In secondth area.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor devices that technical solution of the present invention provides, fin is formed, on fin width direction,
The size of bottom is less than the size at top in the firstth area of fin in the secondth area of fin.Bottom is in fin width side in the secondth area of fin
Upward size is smaller, correspondingly, the width in the secondth area of fin is smaller, so that control ability of the gate structure to the secondth area of fin
Increase.Size of the top on fin width direction is larger in the firstth area of fin, although isolation structure and the secondth area of fin it
Between there are positivity fixed charges at interface, but reduced in the secondth area of fin along the electric leakage of fin extending direction.To sum up, it improves
The performance of semiconductor devices.
In the semiconductor devices that technical solution of the present invention provides, on fin width direction, in the secondth area of fin bottom
Size is less than the size at top in the firstth area of fin.Size of the bottom on fin width direction is smaller in the secondth area of fin, phase
It answers, the width in the secondth area of fin is smaller, so that gate structure increases the control ability in the secondth area of fin.In the firstth area of fin
Size of the top on fin width direction is larger, although there are positivities to consolidate for the interface between the secondth area of isolation structure and fin
Determine charge, but is reduced in the secondth area of fin along the electric leakage of fin extending direction.To sum up, the property of semiconductor devices is improved
Energy.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 2 to Fig. 7 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
A kind of forming method of semiconductor devices, referring to FIG. 1, including: semiconductor substrate 100；Positioned at the semiconductor
Fin 110 on substrate 100；Isolation structure 120 in the semiconductor substrate 100, the isolation structure 120 cover fin
110 partial sidewall of portion；Gate structure 130 on isolation structure 120, the gate structure 130 is across fin 110 and covers
The atop part surface and partial sidewall surface of lid fin 110；It is located at the source and drain doping area of 130 two sides of gate structure.
For convenience of explanation, fin 110 includes the firstth area and the secondth area in the firstth area, the isolation structure 120
The side wall in 110 first area of fin is covered, and the surface of isolation structure 120 is flush to the interface in the firstth area and the secondth area, grid
Structure 130 is across 110 second area of fin.
In order to increase gate structure 130 to the control ability in 110 second area of fin, a kind of method are as follows: reduce fin 110 the
The width in 2nd area.Since 110 first area of fin and 110 second area of fin are formed in same etching technics, with fin
The width of the reduction of the width in 110 second area, portion, 110 first area of fin also reduces.
Interface between 110 first area's side wall of fin and isolation structure 120, there are more positivity fixed charge Qf
(positive fixed oxide charge), these positivity fixed charges QfIt is by 110 first area's side wall of fin and isolation junction
Interface atomic bonding between structure 120 is imperfect caused.
Width of the width of top area relative to bottom section in 110 first area of fin in usual 110 first area of fin
It is smaller, and in the case where the width in 110 first area of fin is reduced with the width in the secondth area, so that 110 first Qu Zhongding of fin
The width in portion region is smaller.By positivity fixed charge QfInfluence, fixed charge QfIt induces and is located in 110 first area of fin
Charge inducing, charge inducing and fixed charge QfIt is electrically opposite.Due to top area in 110 first area of fin width compared with
It is small, therefore in 110 width direction of fin, charge inducing top area in 110 first area of fin is distributed.
For convenience of explanation, the charge inducing at the center of top area in 110 first area of fin is known as center
Charge inducing.In 110 width direction of fin, the fixed charge Q of center charge inducing to 110 first area side side wall of finf
Distance and fixed charge Q to other side side wallfDistance it is almost the same, therefore center charge inducing is by fin 110
One area two sides fixed charge QfElectric field force size it is almost the same.Center charge inducing is by 110 two sides fixed charge Q of finf
Active force cancel out each other, therefore center charge inducing is easy to move under the action of other electric fields.It works in semiconductor devices
When, center charge inducing occurs mobile and generates electric leakage along 110 extending direction of fin.
To solve the above-mentioned problems, the present invention provides a kind of forming method of semiconductor devices, forms fin, and fin includes
Firstth area and the secondth area in the firstth area, the side wall in the firstth area of fin are isolated structure covering, and the side in the secondth area of fin
Wall is isolated structure and is completely exposed, and on fin width direction, the size of bottom is less than in the firstth area of fin in the secondth area of fin
The size at top；The gate structure in the secondth area of fin is developed across on isolation structure.The method improves semiconductor devices
Performance.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 7 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 2, semiconductor substrate 200 is provided, there is initial fin 210 in the semiconductor substrate 200.
In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.The semiconductor substrate 200 can also be
Polysilicon or amorphous silicon.The material of the semiconductor substrate 200 can also be the semiconductor materials such as germanium, SiGe, GaAs.
In the present embodiment, the initial fin 210 is formed by patterned semiconductor substrate 200.In other embodiments
In, it may is that formation fin material layer on a semiconductor substrate, then graphical fin material layer, to form initial fin.
In the present embodiment, the material of initial fin 210 is monocrystalline silicon.In other embodiments, the material of initial fin is
Other semiconductor materials.
It is influenced by the etching technics for forming initial fin 210, the bottom width of the initial fin 210 is greater than initial
The top surface of fin 210.The bottom width and top width of the initial fin 210 refer to being parallel to semiconductor substrate
200 surfaces and perpendicular to the size on initial 210 extending direction of fin.
The top surface of the initial fin 210 also has mask layer 211, and the mask layer 211 is used to formed initially
The position of initial fin 210 is defined during fin 210.
The material of the mask layer 211 includes silicon nitride.
Then, isolation structure is formed in the semiconductor substrate 200, isolation structure covers the part of initial fin 210
Side wall.
The method for forming the isolation structure includes: to be formed to cover initial 210 side of fin in the semiconductor substrate 200
The isolation structure film of wall；It is etched back to isolation structure film, isolation structure film is made to form the isolation structure.
The method for being etched back to isolation structure film includes: be etched back to for the first time to isolation structure film, exposes initial fin
The partial sidewall in portion 210；It carries out after being etched back to for the first time, isolation structure film is etched back to for the second time, makes isolation structure film
Form the isolation structure.
The forming method of the semiconductor devices further include: carry out after being etched back to for the first time, and carrying out second time quarter
Before erosion, the round and smooth processing in surface is carried out to the initial fin that isolation structure film exposes.
With reference to Fig. 3, the isolation structure film 220 for covering initial 210 side wall of fin is formed on semiconductor substrate 200.
The material of the isolation structure film 220 includes silica.
The isolation structure film 220 also side wall of mask film covering layer 211 and the top surface for exposing mask layer 211.
The method for forming the isolation structure film 220 include: in semiconductor substrate 200 and initial fin 210 formed every
From structure initial film, the whole surface of isolation structure initial film is higher than the top surface of mask layer 211；At the beginning of planarizing isolation structure
Top surface of the beginning film up to exposing mask layer 211, makes isolation structure initial film form isolation structure film 220.
Stop-layer of the mask layer 211 as planarization isolation structure initial film.
With reference to Fig. 4, isolation structure film 220 be etched back to for the first time, the partial sidewall of initial fin 210 is exposed.
In the present embodiment, further includes: be etched back to before isolation structure film 220, etching removal mask layer 211.
It with reference to Fig. 5, carries out after being etched back to for the first time, surface is carried out to the initial fin 210 that isolation structure film 220 exposes
Round and smooth processing.
The round and smooth processing in surface includes annealing.
In the present embodiment, the round and smooth processing in surface is annealing, described to make annealing treatment the sidewall surfaces for making initial fin 210
The surface of the corner connected with top surface is more round and smooth, avoids the sidewall surfaces of initial fin 210 and the company of top surface
Place is met in tip-shape.
The principle of the round and smooth processing in surface is carried out to the initial fin 210 that isolation structure film 220 exposes using annealing
It include: that the lattice of the surfacing of the initial fin 210 in high-temperature low-pressure environment, exposed to isolation structure film 220 carries out
Cleaning is rebuild, and the higher crystal face of surface energy is reduced, and the corner for connecting the sidewall surfaces of initial fin 210 with top surface exists
Become after annealing round and smooth.
The annealing includes spike annealing.It is described annealing using spike annealing benefit include: annealing compared with
It is completed in short time, it is smaller to make annealing treatment influence of the high temperature of use to other structures component.
The parameter of the annealing includes: the gas that uses for N2And H2One of or both combination, annealing temperature
It is 800 degrees Celsius~1000 degrees Celsius, annealing pressure is 5torr~50torr.
In the present embodiment, the round and smooth processing in surface is carried out before being etched back to and being etched back to for the first time for the second time, benefit includes:
The round and smooth processing in surface only is carried out to being etched back to the initial fin 210 that rear isolation structure film 220 exposes for the first time, i.e., only to initial
Top area in fin 210 is handled, and it is round and smooth not will do it surface to the initial fin 210 that isolation structure film 220 covers
Processing, so that the size and shape for the initial fin 210 that isolation structure film 220 covers is not influenced by the round and smooth processing in surface.
Isolation structure film 220 is etched back to for the second time, makes isolation structure after carrying out the round and smooth processing in surface with reference to Fig. 6
Film 220 forms the isolation structure 230.
It should be noted that in other embodiments, without the round and smooth processing in surface；Alternatively, after forming fin, to fin
Top corner at carry out the round and smooth processing in surface.
With reference to Fig. 7, the side wall for the initial fin 210 that isolation structure 230 exposes is performed etching, makes initial fin 210
Fin 240 is formed, fin 240 includes the first area A and the second area B on the first area A, the side of the 240 first area A of fin
Wall is isolated the covering of structure 230, and the side wall of 240 second area B of fin is isolated structure 230 and is completely exposed, in 240 width of fin
On direction, the size of bottom is less than the size at top in 240 first area A of fin in the 240 second area B of fin.
The initial fin 210 that the isolation structure 230 exposes is including the first exposed region and on the first exposed region
Second exposed region.
In the present embodiment, during the side wall of the initial fin 210 exposed to isolation structure 230 performs etching,
In initial 210 width direction of fin, the average quarter to the second exposed region is greater than to the average etch size of the first exposed region
Lose size.Benefit includes: the width of bottom section and the fin the in the secondth area of fin so that in the secondth area of fin being subsequently formed
The width gap of top area is smaller in 2nd area, in the case that the width of top area is certain in the secondth area of fin, can obtain
The width for obtaining bottom section in the secondth area of fin is smaller, is subsequently formed after the gate structure in the secondth area of fin, gate structure
Control ability enhancing to bottom section in the secondth area of fin.
Further, during the side wall of the initial fin 210 exposed to isolation structure 230 performs etching, initially
The smaller region of the distance on the sidewall surfaces of fin 210 to 200 surface of semiconductor substrate is in initial 210 width direction of fin
It is bigger by the size etched.
In the present embodiment, the region that the distance on sidewall surfaces to 200 surface of semiconductor substrate of initial fin 210 is smaller exists
It is bigger by the size etched in initial 210 width direction of fin, the side wall of the initial fin that isolation structure is exposed into
The technique of row etching is dry carving technology, and parameter includes: that the gas of use includes NF3、H2And He, NF3Flow be 5sccm~
15sccm, such as 10sccm, H2Flow be 30sccm~50sccm, the flow of such as 40sccm, He be 4500sccm~
6000sccm, such as 5000sccm, source radio-frequency power are 28 watts~35 watts, and such as 30 watts, chamber pressure is 0torrr~0.05torr,
Such as 0torrr.
In other embodiments, during the side wall of the initial fin exposed to isolation structure performs etching,
It is equal to the etching size of the sidewall surfaces of initial fin everywhere along initial fin width direction.In the case, at one
In embodiment, the technique performed etching to the side wall for the initial fin that isolation structure exposes is dry carving technology, and parameter includes: to adopt
Gas includes NF3、H2And He, NF3Flow be 180sccm~220sccm, such as 200sccm, H2Flow be
3600sccm~3800sccm, such as 3750sccm, the flow of He are 2200sccm~2300sccm, such as 2250sccm, source radio frequency
Power is 220 watts~300 watts, and such as 250 watts, chamber pressure is 2torrr~5torr, such as 4torr.
In the present embodiment, in 240 width direction of fin, the size at top is fin in the 240 first area A of fin
1.2 times of the size of bottom in 240 second area B~1.5 times.
In the present embodiment, in 240 width direction of fin, in the 240 first area A of fin top size be 5nm~
The size of bottom is 2nm~30nm in 50nm, the 240 second area B of fin.
It should be noted that the size at top refers in 240 first area A of fin: being flush to the first area A and the secondth area
At the position of interface, size of the 240 first area A of fin in 240 width direction of fin；Bottom in 240 second area B of fin
Size refers to: at the position for being flush to the first area A and second area's interface, 240 second area B of fin is in 240 width of fin
Size on direction.
In the present embodiment, further includes: be developed across the gate structure of 240 second area B of fin, institute on isolation structure 230
State the partial sidewall surface and atop part surface of gate structure covering 240 second area B of fin；In the gate structure two sides
Source and drain doping area is respectively formed in 240 second area B of fin.
In the present embodiment, source and drain doping area is located in 240 second area B of fin, and source and drain doping area is not located at fin 240 first
In area A.
In the present embodiment, in 240 width direction of fin, the size of bottom is less than fin first in 240 second area B of fin
The size at top in area A.Size of the bottom in 240 width direction of fin is smaller in 240 second area B of fin, correspondingly, fin
The width of 240 second area B is smaller, so that gate structure increases by the control ability of 240 second area B of fin.
In the present embodiment, size of the top in 240 width direction of fin is larger in 240 first area A of fin, although every
From the interface between 240 second area B of structure 230 and fin, there are positivity fixed charge Qf, but edge in 240 second area B of fin
240 extending direction of fin electric leakage reduce.Specifically, by positivity fixed charge QfInfluence, fixed charge QfInduce position
Charge inducing in 240 first area A of fin, charge inducing and fixed charge QfIt is electrically opposite.Due to 240 first area of fin
Size of the A top surface in 240 width direction of fin is larger, therefore, the induction of top area in 240 first area A of fin
Charge only in the region close to 240 side wall of fin, does not have charge inducing at the center of top area in 240 first area A of fin.
In 240 width direction of fin, the fixed charge Q of charge inducing to the 240 first area side A side wall of finfBe closer, feel
Answer charge to the fixed charge Q of the 240 first area other side A side wall of finfDistance farther out, and charge inducing and fixed charge Qf
Distance it is closer, charge inducing and fixed charge QfBetween electric field force it is bigger, therefore charge inducing is by 240 first area of fin
The two sides A fixed charge QfElectric field force difference in size it is larger, charge inducing is by the first area two sides A fixed charge QfElectric field force
Resultant force it is larger.The charge inducing close to 240 side wall of fin is by fixed charge QfActive force and be strapped in fin 240
Adjacent sidewalls, and be difficult to move under the action of other electric fields.In semiconductor devices work, along fin in 240 first area A of fin
The electric leakage of 110 extending direction of portion reduces.To sum up, the performance of semiconductor devices is improved.
In the present embodiment, after forming fin 240, and before forming gate structure, isolation structure 230 is not returned
Etching, correspondingly, the surface of isolation structure 230 is flush to the interface of fin 240 first area A and the second area B.
In other embodiments, further includes: after forming fin, and before forming gate structure, to isolation structure into
Row is etched back to, and the surface of isolation structure is made to be lower than the interface in fin 240 first area and the secondth area；After forming gate structure, grid
Pole structure also covers the partial sidewall surface in the firstth area of fin.
Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method, referring to FIG. 7, including:
Semiconductor substrate 200；Fin 240 in the semiconductor substrate 200, fin 240 include being located in semiconductor substrate 200
The firstth area and the second area B on the first area A, in 240 width direction of fin, bottom in the 240 second area B of fin
Size be less than 240 first area A of fin in top size；Isolation structure 230 in the semiconductor substrate 200, institute
The side wall that isolation structure 230 covers 240 first area A of fin is stated, and the surface of isolation structure 230 is lower than or is flush to the first area A
With the interface of the second area B；On isolation structure 230 and across the gate structure of 240 second area B of fin.
In 240 width direction of fin, the size at top is in 240 second area B of fin in the 240 first area A of fin
1.2 times of the size of bottom~1.5 times.
In 240 width direction of fin, the size at top is 5nm~50nm, the fin in the 240 first area A of fin
The size of bottom is 2nm~30nm in 240 second area B of portion.
The semiconductor devices further include: source and drain doping area, the source and drain doping area are located at the gate structure two
In the 240 second area B of fin of side.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor devices characterized by comprising
Semiconductor substrate is provided；
Isolation structure is formed on the semiconductor substrate；
Fin is formed on the semiconductor substrate, and fin includes the firstth area and the secondth area in the firstth area, the fin
The side wall in the firstth area is isolated structure covering, and the side wall in the secondth area of fin is isolated structure and is completely exposed, in fin width side
Upwards, in secondth area of fin bottom size be less than the firstth area of fin in top size；
The gate structure in the secondth area of fin is developed across on isolation structure.
2. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: formed it is described every
Before structure, initial fin is formed on a semiconductor substrate；After forming the isolation structure, isolation structure covers initial fin
Partial sidewall；The side wall for the initial fin that the isolation structure exposes is performed etching, initial fin is made to form the fin
Portion.
3. the forming method of semiconductor devices according to claim 2, which is characterized in that the bottom of the initial fin is wide
Degree is greater than the top width of initial fin.
4. the forming method of semiconductor devices according to claim 3, which is characterized in that the isolation structure exposed
Initial fin includes the first exposed region and the second exposed region on the first exposed region；It is initial being exposed to isolation structure
During the side wall of fin performs etching, along initial fin width direction, to the average etch size of the first exposed region
Greater than the average etch size to the second exposed region.
5. the forming method of semiconductor devices according to claim 4, which is characterized in that is exposed to isolation structure
During the side wall of initial fin performs etching, the distance of sidewall surfaces to the semiconductor substrate surface of initial fin is smaller
Region is bigger by the size etched along initial fin width direction.
6. the forming method of semiconductor devices according to claim 5, which is characterized in that exposed to isolation structure first
The technique that the side wall of beginning fin performs etching is dry carving technology, and parameter includes: that the gas of use includes NF3、H2And He, NF3Stream
Amount is 5sccm~15sccm, H2Flow be 30sccm~50sccm, the flow of He is 4500sccm~6000sccm, and source is penetrated
Frequency power is 28 watts~35 watts, and chamber pressure is 0torrr~0.05torr.
7. the forming method of semiconductor devices according to claim 3, which is characterized in that is exposed to isolation structure
It is each to the sidewall surfaces of initial fin along initial fin width direction during the side wall of initial fin performs etching
The etching size at place is equal.
8. the forming method of semiconductor devices according to claim 7, which is characterized in that exposed to isolation structure first
The technique that the side wall of beginning fin performs etching is dry carving technology, and parameter includes: that the gas of use includes NF3、H2And He, NF3Stream
Amount is 180sccm~220sccm, H2Flow be 3600sccm~3800sccm, the flow of He be 2200sccm~
2300sccm, source radio-frequency power are 220 watts~300 watts, and chamber pressure is 2torrr~5torr.
9. the forming method of semiconductor devices according to claim 2, which is characterized in that form the side of the isolation structure
Method includes: to form the isolation structure film for covering initial fin side wall on the semiconductor substrate；It is etched back to isolation structure film, is made
Isolation structure film forms the isolation structure.
10. the forming method of semiconductor devices according to claim 9, which is characterized in that be etched back to isolation structure film
Method includes: be etched back to for the first time to isolation structure film, exposes the partial sidewall of initial fin；Return for the first time and carves
After erosion, isolation structure film is etched back to for the second time, isolation structure film is made to form the isolation structure；
The forming method of the semiconductor devices further include: carry out after being etched back to for the first time, and be etched back to it for the second time
Before, the round and smooth processing in surface is carried out to the initial fin that isolation structure film exposes.
11. the forming method of semiconductor devices according to claim 10, which is characterized in that the round and smooth processing packet in surface
Include annealing.
12. the forming method of semiconductor devices according to claim 11, which is characterized in that the parameter of the annealing
It include: the gas that uses for N2And H2One of or both combination, annealing temperature be 800 degrees Celsius~1000 degrees Celsius, move back
Pressure ignition is 5torr~50torr.
13. the forming method of semiconductor devices according to claim 1, which is characterized in that on fin width direction, institute
The size for stating top in the firstth area of fin is 1.2 times~1.5 times of the size of bottom in the secondth area of fin.
14. the forming method of semiconductor devices according to claim 13, which is characterized in that on fin width direction,
The very little of top ruler is 5nm~50nm in firstth area of fin, and the size of bottom is 2nm~30nm in secondth area of fin.
15. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: in the grid knot
Source and drain doping area is respectively formed in the secondth area of fin of structure two sides.
16. the forming method of semiconductor devices according to claim 1, which is characterized in that further include: forming fin
Afterwards, and before forming gate structure, isolation structure is etched back, make the surface of isolation structure lower than the firstth area of fin and
The interface in the secondth area；After forming gate structure, gate structure also covers the partial sidewall surface in the firstth area of fin.
17. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Fin in the semiconductor substrate, fin include the firstth area in semiconductor substrate and are located in the firstth area
The secondth area, on fin width direction, in secondth area of fin the size of bottom be less than the firstth area of fin in top ruler
It is very little；
Isolation structure in the semiconductor substrate, the side wall in the isolation structure covering the firstth area of fin, and isolation junction
The surface of structure is lower than or is flush to the interface in the firstth area and the secondth area；
Gate structure on isolation structure and across the secondth area of fin.
18. semiconductor devices according to claim 17, which is characterized in that on fin width direction, the fin
The size at top is 1.2 times~1.5 times of the size of bottom in the secondth area of fin in one area.
19. semiconductor devices according to claim 18, which is characterized in that on fin width direction, the fin
The size at top is 5nm~50nm in one area, and the size of bottom is 2nm~30nm in secondth area of fin.
20. semiconductor devices according to claim 17, which is characterized in that further include: source and drain doping area, the source and drain are mixed
Miscellaneous area is located in the secondth area of fin of the gate structure two sides.
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| CN113451121A (en) * | 2020-03-24 | 2021-09-28 | 广东汉岂工业技术研发有限公司 | Fin manufacturing method of FinFET device |
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Application publication date: 20190702 |