CN103515282A - Fin field-effect transistor and forming method thereof - Google Patents

Fin field-effect transistor and forming method thereof Download PDF

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Publication number
CN103515282A
CN103515282A CN201210206531.7A CN201210206531A CN103515282A CN 103515282 A CN103515282 A CN 103515282A CN 201210206531 A CN201210206531 A CN 201210206531A CN 103515282 A CN103515282 A CN 103515282A
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Prior art keywords
fin formula
effect transistor
field effect
formation method
shallow trench
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CN201210206531.7A
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Chinese (zh)
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韩秋华
三重野文健
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a fin field-effect transistor and a forming method thereof. According to the fin field-effect transistor provided by the invention, side walls of formed shallow trench isolations have a gradient, namely, the formed shallow trench isolations are prevented from having a vertical part, thus avoiding the problem that the vertical parts are not conducive to oxide filling to cause gaps in the shallow trench isolations. Then, first fin structures are reprocessed to form second fin structures to enable the side walls of first parts of the second fin structures to be perpendicular to planes where the surfaces of the shallow trench isolations are located, thus obtaining a structure required by the fin field-effect transistor. Finally, the stability of a device is greatly improved.

Description

A kind of fin formula field effect transistor and forming method thereof
Technical field
The present invention relates to integrated circuit and manufacture field, particularly a kind of fin formula field effect transistor and forming method thereof.
Background technology
In advanced complementary metal oxide semiconductors (CMOS) (CMOS) industry, arrival along with 22nm and smaller szie, in order to improve short-channel effect and to improve the performance of device, fin formula field effect transistor (Fin Field-effect transistor, FinFET) is adopted widely by its unique structure.
As shown in Figure 1, it is fin formula field effect transistor schematic diagram, and fin formula field effect transistor is to have one from the outstanding active region of substrate 10, and this structure is long and narrow, therefore be called as fin formula structure (fin) 12; Between adjacent two fin formula structures 12, be formed with shallow trench isolation (STI) 11; The surface of fin formula structure 12 and shallow trench isolation 11 is formed with grid structure 13; Yuan/ drain region (not shown) is positioned in fin formula structure 12, grid structure 13 both sides; 14 of channel regions are arranged in the active region between grid structure 13 ，Yuan/ drain regions, below.
But, in traditional handicraft, two-fold slope formula (double slope) shape of fin formula structure exists certain drawback, the vertical portion of this shape is unfavorable for the filling of oxide, thus shallow trench isolation 11Nei You space 15, and this obviously will reduce the stability of device greatly.
Summary of the invention
The object of the present invention is to provide a kind of formation method of fin formula field effect transistor, to solve fin formula structure unwarrantable problem of quality when forming shallow trench isolation of two-fold of the prior art slope formula (double slope) shape.
For solving the problems of the technologies described above, the invention provides a kind of formation method of fin formula field effect transistor, comprising:
Substrate is provided;
By etching technics, on described substrate, forming a plurality of the first fin formula structures, is isolation channel between adjacent the first fin formula structure;
Filling oxide layer etching in described isolation channel, form shallow trench isolation, and the sidewall of described shallow trench isolation has gradient, and the surface of described shallow trench isolation is lower than the upper surface of described the first fin formula structure;
Described in etching, the first fin formula structure forms the second fin formula structure, and described the second fin formula structure comprises first and second portion, and the sidewall of described first is perpendicular to the surperficial place plane of described shallow trench isolation.
Further, in the formation method of described fin formula field effect transistor, on described substrate, be formed with mask layer.
Further, in the formation method of described fin formula field effect transistor, the sidewall of described the first fin formula structure has the gradient of 85 ° ~ 86 °.
Further, in the formation method of described fin formula field effect transistor, adopt the first fin formula structure described in dry etch process etching to form the second fin formula structure.
Further, in the formation method of described fin formula field effect transistor, the pressure of described dry etch process is 5 ~ 50milli-torr.
Further, in the formation method of described fin formula field effect transistor, the reacting gas of described dry etch process comprises: fluorocarbon, one or more in chlorine and hydrogen bromide.
Further, in the formation method of described fin formula field effect transistor, described gas flow is: fluorocarbon 10 ~ 100sccm, chlorine 10 ~ 1000sccm, hydrogen bromide 10 ~ 1000sccm.
Further, in the formation method of described fin formula field effect transistor, adopt chemical meteorology deposition or physical gas-phase deposition to carry out the filling of oxide layer.
Further, in the formation method of described fin formula field effect transistor, adopt oxide layer described in dry etching or wet-etching technology etching.
Further, in the formation method of described fin formula field effect transistor, described wet-etching technology is for adopting the hydrofluoric acid of dilution to carry out etching.
The formation method of above-mentioned fin formula field effect transistor makes an a kind of fin formula field effect transistor, comprising:
Substrate, described substrate has a plurality of shallow trench isolation;
Be positioned at the second fin formula structure of described shallow trench isolation both sides, described the second fin formula structure comprises first and second portion, and the sidewall of described first is perpendicular to the surperficial place plane of shallow trench isolation.
Compared with prior art, in fin formula field effect transistor provided by the invention, the sidewall of the shallow trench isolation that forms has gradient, avoided formed shallow trench isolation to there is vertical portion, thereby also just avoided vertical portion to be unfavorable for the filling of oxide, caused the problem in shallow trench isolation Nei You space.Afterwards the first fin formula structure is reprocessed and formed the second fin formula structure, make the sidewall of first of the second fin formula structure perpendicular to the surperficial place plane of described shallow trench isolation, meet the needed structure of fin formula field effect transistor.Finally, improved greatly the stability of device.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation of the fin formula field effect transistor of prior art;
Fig. 2 ~ Fig. 7 is the cross sectional representation of formation method of the fin formula field effect transistor of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the formation method of fin formula field effect transistor provided by the invention is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, substrate 20 is provided, described substrate 20 can be silicon substrate, or the substrate of doped germanium and so on, or silicon-on-insulator (SOI) etc., can comprise all kinds of doped regions, buried layer etc.In the present embodiment, on described substrate 20, form mask layer 21, described mask layer 21 can be SiN(silicon nitride) layer.Then please refer to Fig. 3, through existing viable process photoetching, etching, form a plurality of the first fin formula structures 31, is isolation channel 30 between adjacent the first fin formula structure 31.The the first fin formula structure 31 forming after etching has 85 ° ~ 86° base angle 32, the sidewall of the first fin formula structure 31 has the gradient of 85 ° ~ 86 °, as 85.3 ° be a better selection scheme, can when follow-up filling oxide layer, play preferably effect, avoid vertical stratification to be unfavorable for the shortcoming of filling.
Please refer to Fig. 4, in described isolation channel, filling oxide layer 40, concrete, can adopt known chemical meteorology deposition or physical gas-phase deposition to carry out the filling of oxide layer 40.Through flatening process, oxide layer 40 surfaces are flushed with mask layer 21.Then, please refer to Fig. 5, etching oxidation layer, forms shallow trench isolation 50.Concrete, can adopt dry etching or wet-etching technology, wherein said wet-etching technology is for adopting the hydrofluoric acid of dilution to carry out etching.Now, the surface of shallow trench isolation 50 is lower than the upper surface of described the first fin formula structure 31.
Please refer to Fig. 6, described in etching, the first fin formula structure forms the second fin formula structure 60, and described the second fin formula structure 60 comprises the 60a of first and second portion 60b, wherein, the sidewall 60as of first is perpendicular to the surperficial place plane of described shallow trench isolation 50, the right angle 61 marking in figure.
Concrete, adopt the first fin formula structure described in dry etch process etching to form the second fin formula structure 60, wherein, the pressure of described dry etch process is 5 ~ 50milli-torr, reacting gas comprises fluorocarbon (C xf y), chlorine (Cl 2) and hydrogen bromide (HBr) in one or more, concrete, gas flow can be fluorocarbon 10 ~ 100sccm, chlorine 10 ~ 1000sccm, hydrogen bromide 10 ~ 1000sccm.
Please refer to Fig. 7, on the basis of structure shown in Fig. 6, remove mask layer, proceed to form the techniques such as grid structure 70He Yuan/ drain region (not shown), form a kind of fin formula field effect transistor with better quality shallow trench isolation 50, comprise: substrate 20, described substrate 20 has a plurality of shallow trench isolation 50; Be positioned at the second fin formula structure 60 of described shallow trench isolation 50 both sides, described the second fin formula structure 60 comprises the 60a of first and second portion 60b, the sidewall 60as of the described 60a of first is perpendicular to the surperficial place plane of shallow trench isolation 50, i.e. right angle shown in figure 51, described second portion 60b base angle is 85 ° ~ 86 °, i.e. angle shown in figure 32; The sidewall 60as of the described 60a of first is not connected with the sidewall 60bs of second portion 60b, has transition region 72 between the two; The grid structure 70，Yuan/ drain region that is positioned at the second fin formula structure 60 and shallow trench isolation 50 surfaces is positioned in the second fin formula structure 60, grid structure 70 both sides, and 71 of channel regions are arranged in the active region between grid structure 70 ，Yuan/ drain regions, below.
In fin formula field effect transistor providing at the present embodiment and forming method thereof, the sidewall of the shallow trench isolation that forms has gradient, avoided formed shallow trench isolation to there is vertical portion, thereby also just avoided vertical portion to be unfavorable for the filling of oxide, caused the problem in shallow trench isolation Nei You space.Afterwards the first fin formula structure is reprocessed and formed the second fin formula structure, make the sidewall of first of the second fin formula structure perpendicular to the surperficial place plane of described shallow trench isolation, meet the needed structure of fin formula field effect transistor.Finally, improved greatly the stability of device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these change and modification.

Claims (11)

1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided;
By etching technics, on described substrate, forming a plurality of the first fin formula structures, is isolation channel between adjacent two the first fin formula structures;
Filling oxide layer etching in described isolation channel, form shallow trench isolation, and the sidewall of described shallow trench isolation has gradient, and the surface of described shallow trench isolation is lower than the upper surface of described the first fin formula structure;
Described in etching, the first fin formula structure forms the second fin formula structure, and described the second fin formula structure comprises first and second portion, and the sidewall of described first is perpendicular to the surperficial place plane of described shallow trench isolation.
2. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, on described substrate, is formed with mask layer.
3. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, the sidewall of described the first fin formula structure has the gradient of 85 ° ~ 86 °.
4. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, adopts the first fin formula structure described in dry etch process etching to form the second fin formula structure.
5. the formation method of fin formula field effect transistor as claimed in claim 4, is characterized in that, the pressure of described dry etch process is 5 ~ 50milli-torr.
6. the formation method of fin formula field effect transistor as claimed in claim 4, is characterized in that, the reacting gas of described dry etch process comprises: fluorocarbon, one or more in chlorine and hydrogen bromide.
7. the formation method of fin formula field effect transistor as claimed in claim 6, is characterized in that, described gas flow is: fluorocarbon 10 ~ 100sccm, chlorine 10 ~ 1000sccm, hydrogen bromide 10 ~ 1000sccm.
8. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, adopts chemical meteorology deposition or physical gas-phase deposition to carry out the filling of oxide layer.
9. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, adopts oxide layer described in dry etching or wet-etching technology etching.
10. the formation method of fin formula field effect transistor as claimed in claim 9, is characterized in that, described wet-etching technology is for adopting the hydrofluoric acid of dilution to carry out etching.
11. 1 kinds of fin formula field effect transistors that the formation method of utilizing any one fin formula field effect transistor in claim 1 to 10 makes, is characterized in that, comprising:
Substrate, described substrate has a plurality of shallow trench isolation;
Be positioned at the second fin formula structure of described shallow trench isolation both sides, described the second fin formula structure comprises first and second portion, and the sidewall of described first is perpendicular to the surperficial place plane of shallow trench isolation.
CN201210206531.7A 2012-06-20 2012-06-20 Fin field-effect transistor and forming method thereof Pending CN103515282A (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996625A (en) * 2014-06-12 2014-08-20 上海华力微电子有限公司 Formation method of fin structure
CN104037088A (en) * 2014-06-19 2014-09-10 上海华力微电子有限公司 Method for manufacturing fin field effect transistor
CN104332410A (en) * 2014-11-05 2015-02-04 上海华力微电子有限公司 Manufacturing method for fin type field effect transistor
CN104347427A (en) * 2014-11-05 2015-02-11 上海华力微电子有限公司 Method for manufacturing fin field effect transistor (FET)
CN104362097A (en) * 2014-11-05 2015-02-18 上海华力微电子有限公司 Manufacturing method of fin field-effect transistor
CN105551959A (en) * 2014-10-24 2016-05-04 格罗方德半导体公司 Fin structures and multi-Vt scheme based on tapered fin and method to form
CN105762186A (en) * 2014-12-17 2016-07-13 中国科学院微电子研究所 Fin field-effect transistor, fin structure and manufacturing method thereof
CN107978525A (en) * 2016-10-21 2018-05-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109962017A (en) * 2017-12-22 2019-07-02 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

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US20020109182A1 (en) * 2000-10-28 2002-08-15 Lee Kang-Yoon Integrated circuit devices having active regions with expanded effective widths and methods of manufacturing same
CN1581431A (en) * 2003-08-14 2005-02-16 三星电子株式会社 Multi-structure silicon fin and its making method
CN1992206A (en) * 2005-07-29 2007-07-04 台湾积体电路制造股份有限公司 Method for forming a semiconductor device
CN101490821A (en) * 2006-07-14 2009-07-22 美光科技公司 Subresolution silicon features and methods for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020109182A1 (en) * 2000-10-28 2002-08-15 Lee Kang-Yoon Integrated circuit devices having active regions with expanded effective widths and methods of manufacturing same
CN1581431A (en) * 2003-08-14 2005-02-16 三星电子株式会社 Multi-structure silicon fin and its making method
CN1992206A (en) * 2005-07-29 2007-07-04 台湾积体电路制造股份有限公司 Method for forming a semiconductor device
CN101490821A (en) * 2006-07-14 2009-07-22 美光科技公司 Subresolution silicon features and methods for forming the same

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996625A (en) * 2014-06-12 2014-08-20 上海华力微电子有限公司 Formation method of fin structure
CN103996625B (en) * 2014-06-12 2017-01-25 上海华力微电子有限公司 Formation method of fin structure
CN104037088A (en) * 2014-06-19 2014-09-10 上海华力微电子有限公司 Method for manufacturing fin field effect transistor
CN105551959B (en) * 2014-10-24 2019-06-18 格罗方德半导体公司 Novel fin structure and more limit voltage forms and forming method thereof according to oblique type fin
CN105551959A (en) * 2014-10-24 2016-05-04 格罗方德半导体公司 Fin structures and multi-Vt scheme based on tapered fin and method to form
CN104332410A (en) * 2014-11-05 2015-02-04 上海华力微电子有限公司 Manufacturing method for fin type field effect transistor
CN104347427A (en) * 2014-11-05 2015-02-11 上海华力微电子有限公司 Method for manufacturing fin field effect transistor (FET)
CN104362097A (en) * 2014-11-05 2015-02-18 上海华力微电子有限公司 Manufacturing method of fin field-effect transistor
CN104332410B (en) * 2014-11-05 2017-12-22 上海华力微电子有限公司 A kind of manufacture method of fin formula field effect transistor
CN105762186A (en) * 2014-12-17 2016-07-13 中国科学院微电子研究所 Fin field-effect transistor, fin structure and manufacturing method thereof
CN107978525A (en) * 2016-10-21 2018-05-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107978525B (en) * 2016-10-21 2021-04-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109962017A (en) * 2017-12-22 2019-07-02 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

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Application publication date: 20140115