CN103794490A - Method for forming self-aligned double pattern - Google Patents

Method for forming self-aligned double pattern Download PDF

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CN103794490A
CN103794490A CN201210425630.4A CN201210425630A CN103794490A CN 103794490 A CN103794490 A CN 103794490A CN 201210425630 A CN201210425630 A CN 201210425630A CN 103794490 A CN103794490 A CN 103794490A
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layer
side wall
mask
sub
etching
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CN103794490B (en
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隋运奇
何其旸
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Abstract

Provided is a method for forming a self-aligned double pattern. The method comprises: providing a layer to be etched, wherein the surface of the layer to be etched is equipped with a sacrificial layer sacrificial layer and a mask layer on the surface of the sacrificial layer, wherein the material of the mask layer is insulating material; forming a sidewall layer on the surfaces of the layer to be etched, the sacrificial layer, and the mask layer, wherein the sidewall layer comprises a first sub sidewall layer, a second sub sidewall layer on the surface of the first sub sidewall layer, and a third sub sidewall layer on the surface of the second sub sidewall layer, the material of the second sub sidewall layer is polycrystalline silicon, and the material of the first sub sidewall layer is the same as that of the third sub sidewall layer; etching the sidewall layer until the surface of the mask layer is exposed, thereby forming a sidewall on the surface of the layer to be etched on the two sides of the sacrificial layer; removing the mask layer after the sidewall is formed; and removing the sacrificial layer after the mask layer is removed. Formed self-aligned double patterns are formed by etching mask and are accurate and same in characteristic dimensions.

Description

The formation method of self-aligned double patterning shape
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of self-aligned double patterning shape.
Background technology
Along with the continuous progress of semiconductor technology, the process node of semiconductor device just constantly reduces.But owing to being subject to the restriction of existing photoetching process precision, the mask pattern forming with existing photoetching process is difficult to meet semiconductor device and continues to reduce the demand of characteristic size, has contained the development of semiconductor technology.
For on the basis of existing photoetching process, can further dwindle the size of semiconductor device, prior art has proposed a kind of double-pattern metallization processes.Wherein, be especially simply widely used because of its technique with autoregistration Dual graphing (Self-Aligned Double Patterning, SADP) technique.Fig. 1 to Fig. 4 be prior art form mask with autoregistration double picture metallization processes, and carry out the cross-sectional view of etching process, comprising:
Please refer to Fig. 1, layer 100 to be etched is provided, described layer to be etched 100 surface have sacrifice layer 101, and described sacrifice layer 101 adopts existing photoetching process to form.
Please refer to Fig. 2, form mask side wall 103 on layer to be etched 100 surface of described sacrifice layer 101 both sides.
Please refer to Fig. 3, form after mask side wall 103, remove described sacrifice layer 101(as shown in Figure 2).
Please refer to Fig. 4, remove sacrifice layer 101(as shown in Figure 2) after, take described mask side wall 103 as mask, layer 100 to be etched described in etching, forms groove.
But, forming mask with existing autoregistration double picture metallization processes, and carry out after etching, the figure pattern of etching gained is bad, makes the unstable properties of formed semiconductor device.
More double-pattern metallization processes please refer to the U.S. patent documents that publication number is US 2007/0148968A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of self-aligned double patterning shape, and take the autoregistration figure that formed, when mask carries out etching, the pattern of the figure of etching gained is accurately unified, makes the characteristic size of formed semiconductor device unified.
For addressing the above problem, the invention provides a kind of formation method of self-aligned double patterning shape, comprising: layer to be etched is provided, and described layer to be etched surface has the mask layer of sacrifice layer and described sacrificial layer surface, and the material of described mask layer is insulating material; Form side wall layer on described layer to be etched, sacrifice layer and mask layer surface, described side wall layer comprises the second sub-side wall layer on the first sub-side wall layer, the first sub-side wall layer surface and the 3rd sub-side wall layer on the second sub-side wall layer surface, the material of described the second sub-side wall layer is polysilicon, and described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer; Return side wall layer described in etching until expose mask layer surface, form side wall on the layer to be etched surface of described sacrifice layer both sides; After forming side wall, remove described mask layer; After removing described mask layer, remove described sacrifice layer.
Alternatively, also comprise: described layer to be etched surface has resilient coating, forms sacrifice layer at described buffer-layer surface.
Alternatively, the material of described resilient coating is polysilicon, and the thickness of described resilient coating is 50 dust ~ 80 dusts.
The formation method of self-aligned double patterning shape, is characterized in that as claimed in claim 2, also comprises: after removing sacrifice layer, remove the surperficial remaining resilient coating of described layer to be etched.
Alternatively, the material of described the first sub-side wall layer and the 3rd sub-side wall layer is silicon nitride or silica, the thickness of described the first sub-side wall layer is 100 dust ~ 120 dusts, and the thickness of described the second sub-side wall layer is 100 dust ~ 120 dusts, and the thickness of described the 3rd sub-side wall layer is 100 dust ~ 120 dusts.
Alternatively, the formation technique of described the first sub-side wall layer, the second sub-side wall layer and the second sub-side wall layer is chemical vapor deposition method or physical gas-phase deposition.
Alternatively, the material of described mask layer is silicon oxynitride.
Alternatively, the technique of removing described mask layer is dry etch process, and etching gas comprises: SiCl 4.
Alternatively, the gas of described dry etching also comprises: CF 2h 2, CF 3h and CH 4and O 2in one or more combinations.
Alternatively, the material of described sacrifice layer is amorphous carbon or silica.
Alternatively, when the material of described sacrifice layer is amorphous carbon, the technique of removing described sacrifice layer is cineration technics, and the gas of described cineration technics is oxygen; When the material of described sacrifice layer is silica, the technique of removing described sacrifice layer is wet-etching technology, and etching liquid is hydrofluoric acid.
Alternatively, the formation technique of described sacrifice layer and mask layer is: at described buffer-layer surface deposited sacrificial film, the material of described sacrificial film is amorphous carbon; At described sacrificial film surface deposition mask film, the material of described mask film is silicon oxynitride; Form photoresist layer at described mask film surface, described photoresist layer defines correspondence position and the shape of sacrifice layer; Take described photoresist layer as mask, adopt mask film described in anisotropic dry etch process etching, until expose described sacrificial film, form mask layer; Take described mask layer as mask, adopt sacrificial film described in anisotropic dry etch process etching, until expose resilient coating.
Alternatively, the material of described layer to be etched is silica.
Alternatively, also comprise: Semiconductor substrate is provided, and described layer to be etched is positioned at described semiconductor substrate surface.
Alternatively, also comprise: removing after described sacrifice layer, take described side wall as mask, layer to be etched is until expose Semiconductor substrate described in etching; Take the layer to be etched after etching as mask, Semiconductor substrate described in etching.
Alternatively, also comprise: the dielectric layer between described Semiconductor substrate and layer to be etched and one or more layers in device layer are overlapping.
Alternatively, also comprise: removing after described sacrifice layer, take described side wall as mask, layer to be etched is until expose dielectric layer or device layer described in etching; Take the layer to be etched after etching as mask, dielectric layer or device layer described in etching.
Alternatively, described layer to be etched is Semiconductor substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form and comprise the second sub-side wall layer on the first sub-side wall layer, the first sub-side wall layer surface and the 3rd sub-side wall layer on the second sub-side wall layer surface on layer to be etched, sacrifice layer and mask layer surface, and described side wall layer is returned to etching formation side wall; Wherein, it is " L " shape that the second sub-side wall layer in described side wall layer returns shape after etching, the material of described mask layer is insulating material, and the material of described the second sub-side wall layer is polysilicon, described polysilicon has higher selectivity with respect to the material of mask layer, in the time removing described mask layer, " L " shape the second sub-side wall layer in described side wall can keep the width of described side wall and highly can not reduce; Guarantee that with this figure that etching obtains is accurate, and deviation can not occur, thereby makes the characteristic size of formed semiconductor device certain, stable performance take described side wall as when layer to be etched described in mask etching; In addition,, because described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer, in the time removing mask layer, the silicon nitride that is positioned at described polysilicon both sides in described side wall can be subject to etching simultaneously, therefore the sidewall pattern symmetry of described side wall both sides; The graphic limit consistent appearance forming along the sidewall etching of described side wall both sides, is conducive to the unification of the characteristic size that keeps semiconductor device.
Further, before forming described sacrifice layer, form resilient coating on described etch layer surface; In the time of the mask layer of follow-up removal sacrificial layer surface, described resilient coating can protect the surface of layer to be etched not to be thinned; Thereby after having avoided follow-up removal sacrifice layer, the layer apparent height to be etched that is positioned at side wall both sides is inconsistent; And then, guarantee follow-uply more easily to control as the technique of layer to be etched described in mask etching take described side wall, avoid occurring the inconsistent problem of gash depth that over etching, etching are incomplete or form; Can make the characteristic size of formed semiconductor device unified, stable performance, and technique is more easily controlled.
Accompanying drawing explanation
Fig. 1 to Fig. 4 be prior art form mask with autoregistration double picture metallization processes, and carry out the cross-sectional view of etching process;
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the self-aligned double patterning shape described in embodiments of the invention.
Embodiment
As stated in the Background Art, existing autoregistration double picture metallization processes forms mask, and carries out after etching, and the figure pattern of etching gained is bad, makes the unstable properties of formed semiconductor device.
The present inventor finds through research, in prior art, in order to make to adopt self-aligned double patterning shape metallization processes to form mask and to carry out the more accurate easily control of figure of etching, described sacrifice layer 101(is as shown in Figure 1) formation technique be: in layer 100 surface formation sacrificial film to be etched; Form mask film on described sacrificial film surface; Form photoresist layer at described mask film surface, described photoresist layer has defined follow-up correspondence position and the shape that needs the sacrifice layer forming; Take described photoresist layer as mask, mask film described in etching until expose sacrificial film surface, forms mask layer; Take described mask layer as mask, sacrificial film described in etching until expose layer to be etched 100 surface, forms sacrifice layer 101.
Because described sacrifice layer 101 needs to be removed after forming side wall 103, therefore the material of described sacrifice layer 101 need be chosen easy removed material, comprising: silica or amorphous carbon; In addition, because the hardness of silicon nitride is higher, the material of the side wall 103 of prior art is silicon nitride, is conducive to keep the stable of figure in etching technics; To sum up, the material require of described mask layer is chosen the material all with respect to side wall 103 and sacrifice layer 101 with higher Etch selectivity, and the material that therefore prior art adopts is silicon oxynitride.
But, please continue to refer to Fig. 1 to Fig. 4, due to after forming side wall 103, before removing sacrifice layer 101, need to remove mask layer; In the time that the material of described mask layer is silicon oxynitride, removes the technique of described mask layer and easily the side wall 103 take silicon nitride as material and described layer 100 to be etched are carried out to etching simultaneously; Wherein, after described side wall 103 is etched in the process of removal mask layer, the width dimensions of described side wall 103 and highly all corresponding reducing, easily cause on layer to be etched described in etching 100 o'clock, the boundary forming along the sidewall etching of described side wall 103 is wayward, and the dimension of picture of to be etched layer 100 gained described in etching, and device design size between there is deviation, and then make the performance of formed semiconductor device bad.
Further, in prior art, layer 100 to be etched is Semiconductor substrate, dielectric layer or device layer, especially in the time that described layer 100 to be etched is the dielectric layer take silica as material, because the Etch selectivity between silicon oxynitride and silica is less, remove technique the having the greatest impact to described layer 100 to be etched of described mask layer; The attenuate if described layer 100 to be etched is etched in the process of removing mask layer, after removing sacrifice layer 101, the layer to be etched surface of described side wall 103 both sides do not flush, cause the technique of layer 100 to be etched described in etching to be difficult for accurately controlling, easily cause over etching, etching not exclusively or cause the gash depth difference forming in the interior etchings of layer 100 to be etched, make the technique of layer 100 to be etched described in etching be difficult to control.
The present inventor entered further research, and the side wall layer that is used in formation side wall comprises the second sub-side wall layer on the first sub-side wall layer, the first sub-side wall layer surface and the 3rd sub-side wall layer on the second sub-side wall layer surface; Wherein, the material of described the second sub-side wall layer is polysilicon, and described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer; It is " L " shape that the second sub-side wall layer in described side wall layer returns shape after etching, because the material of described the second sub-side wall layer is polysilicon, polysilicon has higher Etch selectivity with respect to the material of mask layer, and described " L " shape side wall can be in the process of the described mask layer of removal, keep the width dimensions of described side wall constant, avoid the height of side wall too to be reduced simultaneously; And, because described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer, therefore in the time removing described mask layer, the side wall that described the first sub-side wall layer and the 3rd sub-side wall layer form can be etched simultaneously, has guaranteed that the shape of the sidewall of described side wall both sides can be symmetrical; The accurately easily control of figure obtaining take described side wall as mask etching layer to be etched; And take the side wall that formed as described in mask etching when to be etched layer, the boundary of etching figure is good, makes the characteristic size of formed semiconductor device same, stable performance.
In addition, the present inventor finds, forms resilient coating, then form the mask layer of sacrifice layer and sacrificial layer surface in described buffer-layer surface on described layer to be etched surface; Form in described sacrifice layer both sides after side wall when follow-up, removing in the process of described mask layer, due to the protection of described resilient coating, described layer to be etched can not be subject to removing the impact of mask layer technique and attenuate; Thereby, avoided follow-up and produced over etching or the incomplete problem of etching take described side wall as when layer to be etched described in mask etching, or avoided the gash depth that forms in described side wall both sides inconsistent; Make the characteristic size of formed semiconductor device same, stable performance.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the self-aligned double patterning shape described in embodiments of the invention.
Please refer to Fig. 5, device layer 200 is provided, described device layer 200 surfaces have layer 201 to be etched, and described layer to be etched 201 surface have resilient coating 202.
The surface of described layer 201 to be etched adopts self-aligned double patterning shape technique to form side wall as etch mask in subsequent technique, and carries out etching to form semiconductor device.
In the present embodiment, described layer 201 to be etched is formed at device layer 200 surfaces, and described device layer 200 is formed at semiconductor substrate surface; In another embodiment, described layer 201 to be etched can also directly be formed at Semiconductor substrate (not shown) surface; Described Semiconductor substrate is used to subsequent technique that workbench is provided; Described Semiconductor substrate is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V compounds of group substrate (such as silicon nitride or GaAs etc.).
It should be noted that, it is overlapping that described semiconductor substrate surface can also form one or more layers in dielectric layer (not shown) or device layer 200, described layer 201 to be etched is formed at described dielectric layer or device layer 200 surfaces, at subsequent technique, described layer 201 to be etched is carried out after etching, described layer 201 to be etched is positioned at the mask of device layer 200, dielectric layer or the Semiconductor substrate of its below as etching; Wherein, described dielectric layer is used for making electricity isolation between each layer device layer 200, and material comprises: one or more in silica, silicon nitride, silicon oxynitride, polysilicon, low-K dielectric material and high K dielectric material; Described device layer 200 is used to form the part-structure in semiconductor device, and material comprises: one or more in metal, polysilicon, amorphous carbon, SiGe or carborundum.
In the present embodiment, in order to make the Etch selectivity between described device layer 200 and etch layer 201 larger, the material of described layer 201 to be etched is silica; Described layer to be etched 201 is etched and for the mask as device layer described in etching 200 in subsequent technique; Due in subsequent technique, described layer to be etched 201 surface are formed with the side wall as etch mask, layer 201 to be etched take described side wall after mask etching can copy the figure of described side wall completely, and the stability of described layer 201 to be etched is high compared with side wall, effect as etch mask is better, can be in the time forming the etching figure of smaller szie, make figure that etching obtains more accurately and be easy to control.
In another embodiment, described layer 201 to be etched is formed at semiconductor substrate surface, in subsequent technique, after over etching, as the mask of Semiconductor substrate described in etching, thereby in Semiconductor substrate, forms groove to continue to manufacture semiconductor device.
Described resilient coating 202 is at follow-up formation side wall, and while removing the mask layer of sacrificial layer surface, protect the described to be etched layer 201 surface attenuate that is not etched, thereby guarantee follow-up take the side wall that formed as mask, layer to be etched 201 o'clock described in etching, etching technics is easily controlled, and has avoided over etching, etching not exclusively or gash depth inconsistent problem that side wall both sides form; The material of described resilient coating 202 is polysilicon, and forming technique is physical vaporous deposition technique after chemical vapor deposition method; The thickness of described resilient coating 202 is 50 dust ~ 80 dusts, and the layer 201 to be etched that can adequately protect in the time of the described resilient coating 202 of follow-up removal, can not cause excessive impact to the height of formed side wall simultaneously.
Please refer to Fig. 6, form the mask layer 204 on sacrifice layer 203 and described sacrifice layer 203 surfaces on described resilient coating 202 surfaces, the material of described mask layer 204 is insulating material.
Described sacrifice layer 203 need to have higher Etch selectivity with the side wall of follow-up formation and resilient coating, and need to be easy to be removed and noresidue, and therefore the material of described sacrifice layer is silica or amorphous carbon; The formation technique of described silica or amorphous carbon is simple, and described silica can be removed by wet-etching technology, and described amorphous carbon is removed by cineration technics, the sacrifice layer 203 forming can thoroughly be removed and can not produce residual and affect the carrying out of technique in subsequent technique; And described silica or amorphous carbon have certain degree of hardness, the shape of formed sacrifice layer 203 is fixed, in the time of follow-up formation side wall, can not be out of shape the quality that affects formed side wall because of described sacrifice layer 203; In the present embodiment, the material of described sacrifice layer 203 is amorphous carbon.
The formation technique of described sacrifice layer 203 is: in described resilient coating 202 surface deposition sacrificial film, in the present embodiment, the material of described sacrificial film is amorphous carbon; At described sacrificial film surface deposition mask film, in order to make formed mask layer 204 have higher Etch selectivity with respect to the side wall of sacrifice layer 203 and follow-up formation, the material of described mask film is silicon oxynitride; Form photoresist layer at described mask film surface, described photoresist layer defines correspondence position and the shape of sacrifice layer; Take described photoresist layer as mask, adopt mask film described in anisotropic dry etch process etching, until expose described sacrificial film, form mask layer 204; Take described mask layer 204 as mask, adopt sacrificial film described in anisotropic dry etch process etching, until expose resilient coating 202, form sacrifice layer 203.
Because the distance between width and the adjacent sacrifice layer 203 of described sacrifice layer 203 is subject to the restriction of existing photoetching process accuracy and cannot further dwindles, limit the integrated growth requirement of semiconductor device; When adopting self-aligned double patterning shape metallization processes, subsequent technique forms side wall in described sacrifice layer 203 both sides, mask using described side wall as etching technics again, can be in original region that only can form a sacrifice layer, form the side wall of double amount as etch mask; Thereby the size of the semiconductor structure after etching is further reduced, reached the object of dwindling feature sizes of semiconductor devices.
Wherein, the material of described mask layer 204 is silicon oxynitride, has certain hardness, and all has Etch selectivity with respect to the material of the side wall of sacrifice layer 203 and follow-up formation; When take photoresist layer as mask, etching forms after mask layer 204, described mask layer 204 can copy the figure of photoresist layer completely, and described mask layer 204 has hardness, therefore, the size of sacrifice layer 203 forming take described mask layer 204 as mask etching is more accurate, and the characteristic size of follow-up formed semiconductor structure is accurate, has avoided in etching process the figure because of photoresist layer to change and has caused the sacrifice layer 203 that etching obtains that deviation occurs.
Please refer to Fig. 7, form side wall layer 205 on described layer 201 to be etched, sacrifice layer 203 and mask layer 204 surfaces, described side wall layer 205 comprises the first sub-side wall layer 2051, the second sub-side wall layer 2052 on the first sub-side wall layer 2051 surfaces and the 3rd sub-side wall layer 2053 on the second sub-side wall layer 2052 surfaces, the material of described the second sub-side wall layer 2052 is polysilicon, and described the first sub-side wall layer 2051 is identical with the material of the 3rd sub-side wall layer 2053.
Described side wall layer 205 is for forming side wall at subsequent technique; The material of described the first sub-side wall layer 2051 and the 3rd sub-side wall layer 2053 is silicon nitride or silica; In the present embodiment, the material of described the first sub-side wall layer 2051 and the 3rd sub-side wall layer 2053 is silicon nitride, and the hardness of silicon nitride is higher, is conducive in subsequent technique as etch mask; The formation technique of described the first sub-side wall layer 2051, the second sub-side wall layer 2052 and the 3rd sub-side wall layer 2053 is chemical vapor deposition method or physical gas-phase deposition, preferably chemical vapor deposition method; The thickness of described the first sub-side wall layer 2051 is 100 dust ~ 120 dusts, and the thickness of described the second sub-side wall layer 2052 is 100 dust ~ 120 dusts, and the thickness of described the 3rd sub-side wall layer 2053 is 100 dust ~ 120 dusts.The formation technique of described the first sub-side wall layer 2051, the second sub-side wall layer 2052 and the 3rd sub-side wall layer 2053 is well known to those skilled in the art, and therefore not to repeat here.
Described the second sub-side wall layer 2052 forms the structure of " L " shape in side wall in subsequent technique, because polysilicon has certain degree of hardness, therefore after follow-up formation side wall, remove in the process of mask layer 204, can keep the width of formed side wall and highly constant, thereby the effect while having guaranteed described side wall as etch mask, makes the figure of etching gained meet design standard; In addition, described the first sub-side wall layer 2051 is positioned at the identical sub-side wall of " L " conformal polysilicon two layers of material with the 3rd sub-side wall layer 2053 in follow-up formation, in the process of follow-up removal mask layer 204, the sub-side wall that described material is identical is thinned simultaneously, thereby guarantee the symmetry of the cross-section structure of the side wall forming, can make the boundary of the figure obtaining along described side wall etching unified; The characteristic size of the semiconductor device therefore, forming more accurately and is easily controlled.
Please refer to Fig. 8, return side wall layer 205 described in etching until expose mask layer 204 and the surface of resilient coating 202, form side wall 205a on layer to be etched 201 surface of described sacrifice layer 203 both sides.
Described time etching technics is anisotropic dry etch process, because described anisotropic dry etch process makes etching gas ion to the layer 200 vertical bombardment in surface to be etched, therefore can remove the side wall layer 205 of described resilient coating 202 surfaces and mask layer 204 top surfaces; And, parallel with the direction of motion of described etching gas ion owing to being positioned at the side wall layer 205 of described sacrifice layer 203 sidewall surfaces, therefore described etching gas is difficult to bombardment and removes and be positioned at the side wall layer 205 of described sacrifice layer 203 sidewalls, thereby the side wall layer 205 that is positioned at described sacrifice layer 203 sidewalls is retained, forms side wall 205a.
Because described sacrifice layer 203 both sides form respectively side wall 205a, therefore can, forming in the scope of a sacrifice layer 203, form the side wall 205a of double amount as mask, thereby make the feature size downsizing of formed semiconductor device; And described side wall 205a does not form by photoetching process, is not therefore subject to the restriction of photoetching process accuracy, still can guarantee accurately can controlling of distance between width and the adjacent side wall 205a of formed side wall 205a.
Concrete, adopt for the first time described in anisotropic dry etch process etching the 3rd sub-side wall layer 2053(as shown in Figure 7), until expose the second sub-side wall layer 2052 on mask layer 204 and layer to be etched 201 surface, form the 3rd sub-side wall 2053a, etching gas comprises CHF 3and O 2; Take described the 3rd sub-side wall 2053a as mask, adopt described in the dry etch process etching of anisotropic for the second time the second sub-side wall layer 2052(as shown in Figure 7), until expose the first sub-side wall layer 2051(as shown in Figure 7), form the second sub-side wall 2052a, etching gas comprises one or both in chlorine and hydrogen bromide; Take described the second sub-side wall 2052a as mask, adopt the first sub-side wall layer 2051 described in anisotropic dry etch process etching for the third time, until expose mask layer 204 and layer to be etched 201 surface, form the first sub-side wall 2051a, etching gas comprises CHF 3and O 2.
Wherein, described the second sub-side wall 2052a is " L " shape structure, owing to thering is higher Etch selectivity between described polysilicon and the silicon oxy-nitride material of mask layer 204, therefore in the time of the described mask layer 204 of follow-up removal, described the second sub-side wall 2052a can keep the width of side wall 205 and height dimension not to be reduced, thereby assurance is carried out take described side wall 205 as mask, the figure of etching is more accurate and size unified; In addition, because the Etch selectivity between described the first sub-side wall 2051a and the 3rd sub-side wall 2053a and the silicon oxy-nitride material of mask layer 204 is lower, in the process of follow-up removal mask layer 204, can be etched simultaneously and reduce height; But, because the second sub-side wall 2052a can keep width and the height dimension of described side wall, therefore better as the effect of etch mask using described side wall 205; Simultaneously, because described the first sub-side wall 2051a and the 3rd sub-side wall 2053a are lowered simultaneously, guarantee the sidewall pattern symmetry of described side wall 205 both sides silicon nitride materials, the graphic limit consistent appearance that subsequent technique is formed along the sidewall etching of described side wall 205 silicon nitride materials, thus make the characteristic size of formed semiconductor device accurately unified.
Please refer to Fig. 9, after forming side wall 205a, remove described mask layer 204(as shown in Figure 8).
The technique of removing described mask layer 204 is dry etch process, and etching gas comprises: SiCl 4, described etching gas also comprises: CF 2h 2, CF 3h and CH 4and O 2in one or more combinations; Wherein, described gas SiCl 4can improve the selectivity of etching technics for polycrystalline silicon material, removing completely in the process of described mask layer 204, not damage described the second sub-side wall 2052a; Described the second sub-side wall 2052a is in the technique of the described mask layer 204 of removal, width and height dimension all can not be reduced, thereby the etching figure forming as etch mask that has guaranteed described side wall 205 is accurate, and meet design standard, avoided being reduced because of width and the height dimension of side wall 205 problem that makes etching figure generation deviation.
In addition; because described layer to be etched 201 surface have resilient coating 202; because the material of described resilient coating 202 is polysilicon; there is higher selectivity with respect to the material of described mask layer 204; in the process of described removal mask layer 204; described resilient coating 204 can protect the layer to be etched surface that is positioned at sacrifice layer 203 and side wall 205 both sides not to be etched; when after follow-up removal sacrifice layer 203; be positioned to be etched layer 201 flush of side wall 205 both sides, the technique of layer 201 to be etched described in subsequent etching is easily controlled.
And the both sides of described the second sub-side wall 2052a have the first sub-side wall 2051a and the 3rd sub-side wall 2053a; Because silicon nitride is relatively low with respect to the Etch selectivity of mask layer 204, in the process of the described mask layer 204 of removal, described the first sub-side wall 2051a and the 3rd sub-side wall 2053a can be subject to the impact of etching technics, cause reducing of width and height dimension; But, because described the first sub-side wall 2051a and the 3rd sub-side wall 2053a are etched simultaneously, make described the first sub-side wall 2051a identical with the thickness that the 3rd sub-side wall 2053a is etched, therefore the sidewall pattern symmetry in described the first sub-side wall 2051a and the 3rd sub-side wall 2053a outside; Thereby make follow-up take described side wall 205 when mask carries out etching, the pattern of the graphic limit forming along the sidewall etching in described the first sub-side wall 2051a and the 3rd sub-side wall 2053a outside is unified, the characteristic size of the semiconductor device forming is unified.
Please refer to Figure 10, after removing described mask layer 204, remove described sacrifice layer 203(as shown in Figure 9).
In the time that the material of described sacrifice layer 203 is amorphous carbon, the technique of removing described sacrifice layer 203 is cineration technics, and the gas of described cineration technics is oxygen, can not cause damage to side wall 205; In the time that the material of described sacrifice layer 203 is silica, the technique of removing described sacrifice layer 203 is wet-etching technology, etching liquid is hydrofluoric acid, because described silica is higher with respect to the Etch selectivity of the first sub-side wall 2051a, the second sub-side wall 2052a or the 3rd sub-side wall 2053a, therefore in the time removing described sacrifice layer 203, can not damage described side wall 205.
After removing described sacrifice layer 203, described side wall 205 is as the mask of subsequent etching technique; The restriction that is subject to existing photoetching process precision due to the distance between width and the adjacent sacrifice layer 203 of described sacrifice layer 203 cannot further reduce; And described side wall 205 is not formed at described sacrifice layer 203 both sides by photoetching process, in the region that forms a sacrifice layer 203, can form the side wall 205 of double amount, therefore described side wall 205 is in the situation that guaranteeing characteristic size accuracy, size can further reduce, and is conducive to form the semiconductor device that integrated level is higher.
In the present embodiment, because the material of described sacrifice layer 203 is amorphous carbon, therefore, the technique of removing described sacrifice layer 203 is cineration technics.
It should be noted that, after removing described sacrifice layer 203, remove layer to be etched 201 surperficial remaining resilient coating 202, and expose layer to be etched 201 surface.
Please refer to Figure 11, removing after described sacrifice layer 203, take described side wall 205a as mask, layer 201 to be etched is until expose device layer 200 described in etching.
In the present embodiment, described layer 201 to be etched is formed at device layer surface, and therefore described in etching, the technique of layer 201 to be etched stops at described device layer surface.In another embodiment, when described layer 201 to be etched is formed at dielectric layer or semiconductor substrate surface, described in etching, the technique of layer 201 to be etched stops at described dielectric layer or semiconductor substrate surface.
The dry etch process that described in described etching, the technique of layer 201 to be etched is anisotropic; In the present embodiment, after layer to be etched described in etching 201, take the layer 201 to be etched after described etching as mask, device layer 200 described in etching.In another embodiment, in the time that described layer to be etched 201 is formed at dielectric layer or semiconductor substrate surface, take the layer 201 to be etched after described etching as mask, dielectric layer or Semiconductor substrate described in etching.
In the present embodiment, the material of described layer 201 to be etched is silica, and silica has certain degree of hardness, and the stability as mask in etching technics is stronger; In addition, the figure of the layer 201 to be etched after etching is identical with the figure of described side wall 205a, therefore, in the time of to be etched layer 201 mask as etched features layer 200 after described etching, can make the more accurate easily control of the technique of device layer 200 described in etching, the characteristic size of the semiconductor device forming is more accurately unified, is conducive to the stable performance of semiconductor device.
It should be noted that, the side wall 205a forming in the present embodiment can also directly be formed at semiconductor substrate surface, and described in the present embodiment, layer 201 to be etched is Semiconductor substrate, and described side wall 205a is as the mask of etching semiconductor substrate; Due in the process of removal mask layer 204, the second sub-side wall 2052a can keep the height of described side wall 205a and width dimensions not to be reduced, and the outside sidewall of described the first sub-side wall 2051a and the 3rd sub-side wall 2053a is symmetrical after removing mask layer 204, therefore take described side wall 2052a as the figure of Semiconductor substrate gained described in mask etching accurate, characteristic size is same, and the performance of semiconductor device forming is stable.
In the present embodiment, described surface to be etched is formed with resilient coating, and described sacrifice layer is formed at described buffer-layer surface, and described sacrificial layer surface has mask layer; Form the second sub-side wall in the first sub-side wall, the first sub-side wall outside and the 3rd sub-side wall in described the second sub-side wall outside at the buffer-layer surface of described sacrifice layer both sides; Wherein, described the second sub-side wall is " L " shape, can be in the process of follow-up removal mask layer, and keep the width of described side wall and height dimension not to be reduced, thereby guarantee that the figure forming take described side wall as mask etching is accurate; Be arranged in the first sub-side wall of described the second sub-side wall both sides and the 3rd sub-side wall in the process of removing mask layer, can be etched simultaneously, therefore the sidewall pattern symmetry in described the first sub-side wall and the 3rd sub-side wall outside; The figure that carries out etching gained take described side wall as mask is more accurate, and size is unified, is conducive to the stable performance of semiconductor device; In addition, the resilient coating that is positioned at layer to be etched surface can be in the time removing mask layer, protects layer to be etched surface injury-free; When after follow-up removal sacrifice layer, be positioned at the to be etched layer flush of side wall both sides, therefore make described in etching the technique of layer to be etched more easy to control.
In sum, form and comprise the second sub-side wall layer on the first sub-side wall layer, the first sub-side wall layer surface and the 3rd sub-side wall layer on the second sub-side wall layer surface on layer to be etched, sacrifice layer and mask layer surface, and described side wall layer is returned to etching formation side wall; Wherein, it is " L " shape that the second sub-side wall layer in described side wall layer returns shape after etching, the material of described mask layer is insulating material, and the material of described the second sub-side wall layer is polysilicon, described polysilicon has higher selectivity with respect to the material of mask layer, in the time removing described mask layer, " L " shape the second sub-side wall layer in described side wall can keep the width of described side wall and highly can not reduce; Guarantee that with this figure that etching obtains is accurate, and deviation can not occur, thereby makes the characteristic size of formed semiconductor device certain, stable performance take described side wall as when layer to be etched described in mask etching; In addition,, because described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer, in the time removing mask layer, the silicon nitride that is positioned at described polysilicon both sides in described side wall can be subject to etching simultaneously, therefore the sidewall pattern symmetry of described side wall both sides; The graphic limit consistent appearance forming along the sidewall etching of described side wall both sides, is conducive to the unification of the characteristic size that keeps semiconductor device.
Further, before forming described sacrifice layer, form resilient coating on described etch layer surface; In the time of the mask layer of follow-up removal sacrificial layer surface, described resilient coating can protect the surface of layer to be etched not to be thinned; Thereby after having avoided follow-up removal sacrifice layer, the layer apparent height to be etched that is positioned at side wall both sides is inconsistent; And then, guarantee follow-uply more easily to control as the technique of layer to be etched described in mask etching take described side wall, avoid occurring the inconsistent problem of gash depth that over etching, etching are incomplete or form; Can make the characteristic size of formed semiconductor device unified, stable performance, and technique is more easily controlled.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (18)

1. a formation method for self-aligned double patterning shape, is characterized in that, comprising:
Layer to be etched is provided, and described layer to be etched surface has the mask layer of sacrifice layer and described sacrificial layer surface, and the material of described mask layer is insulating material;
Form side wall layer on described layer to be etched, sacrifice layer and mask layer surface, described side wall layer comprises the second sub-side wall layer on the first sub-side wall layer, the first sub-side wall layer surface and the 3rd sub-side wall layer on the second sub-side wall layer surface, the material of described the second sub-side wall layer is polysilicon, and described the first sub-side wall layer is identical with the material of the 3rd sub-side wall layer;
Return side wall layer described in etching until expose mask layer surface, form side wall on the layer to be etched surface of described sacrifice layer both sides;
After forming side wall, remove described mask layer;
After removing described mask layer, remove described sacrifice layer.
2. the formation method of self-aligned double patterning shape as claimed in claim 1, is characterized in that, also comprises: described layer to be etched surface has resilient coating, forms sacrifice layer at described buffer-layer surface.
3. the formation method of self-aligned double patterning shape as claimed in claim 2, is characterized in that, the material of described resilient coating is polysilicon, and the thickness of described resilient coating is 50 dust ~ 80 dusts.
4. the formation method of self-aligned double patterning shape as claimed in claim 2, is characterized in that, also comprises: after removing sacrifice layer, remove the surperficial remaining resilient coating of described layer to be etched.
5. the formation method of self-aligned double patterning shape as claimed in claim 1, it is characterized in that, the material of described the first sub-side wall layer and the 3rd sub-side wall layer is silicon nitride or silica, the thickness of described the first sub-side wall layer is 100 dust ~ 120 dusts, the thickness of described the second sub-side wall layer is 100 dust ~ 120 dusts, and the thickness of described the 3rd sub-side wall layer is 100 dust ~ 120 dusts.
6. the formation method of self-aligned double patterning shape as claimed in claim 1, is characterized in that, the formation technique of described the first sub-side wall layer, the second sub-side wall layer and the second sub-side wall layer is chemical vapor deposition method or physical gas-phase deposition.
7. the formation method of self-aligned double patterning shape as claimed in claim 1, is characterized in that, the material of described mask layer is silicon oxynitride.
8. the formation method of self-aligned double patterning shape as claimed in claim 1, is characterized in that, the technique of removing described mask layer is dry etch process, and etching gas comprises: SiCl 4.
9. the formation method of self-aligned double patterning shape as claimed in claim 8, is characterized in that, the gas of described dry etching also comprises: CF 2h 2, CF 3h and CH 4and O 2in one or more combinations.
10. the formation method of self-aligned double patterning shape as claimed in claim 1, is characterized in that, the material of described sacrifice layer is amorphous carbon or silica.
The 11. formation methods of self-aligned double patterning shape as claimed in claim 10, is characterized in that, when the material of described sacrifice layer is amorphous carbon, the technique of removing described sacrifice layer is cineration technics, and the gas of described cineration technics is oxygen; When the material of described sacrifice layer is silica, the technique of removing described sacrifice layer is wet-etching technology, and etching liquid is hydrofluoric acid.
The 12. formation methods of self-aligned double patterning shape as claimed in claim 1, is characterized in that, the formation technique of described sacrifice layer and mask layer is: at described buffer-layer surface deposited sacrificial film, the material of described sacrificial film is amorphous carbon; At described sacrificial film surface deposition mask film, the material of described mask film is silicon oxynitride; Form photoresist layer at described mask film surface, described photoresist layer defines correspondence position and the shape of sacrifice layer; Take described photoresist layer as mask, adopt mask film described in anisotropic dry etch process etching, until expose described sacrificial film, form mask layer; Take described mask layer as mask, adopt sacrificial film described in anisotropic dry etch process etching, until expose resilient coating.
The 13. formation methods of autoregistration double-pattern as claimed in claim 1, is characterized in that, the material of described layer to be etched is silica.
The 14. formation methods of autoregistration double-pattern as claimed in claim 1, is characterized in that, also comprise: Semiconductor substrate is provided, and described layer to be etched is positioned at described semiconductor substrate surface.
The 15. formation methods of autoregistration double-pattern as claimed in claim 14, is characterized in that, also comprise: after removing described sacrifice layer, take described side wall as mask, layer to be etched is until expose Semiconductor substrate described in etching; Take the layer to be etched after etching as mask, Semiconductor substrate described in etching.
The 16. formation methods of autoregistration double-pattern as claimed in claim 14, is characterized in that, also comprise: between described Semiconductor substrate and layer to be etched, have one or more layers in dielectric layer and device layer overlapping.
The 17. formation methods of autoregistration double-pattern as claimed in claim 16, is characterized in that, also comprise: after removing described sacrifice layer, take described side wall as mask, layer to be etched is until expose dielectric layer or device layer described in etching; Take the layer to be etched after etching as mask, dielectric layer or device layer described in etching.
The 18. formation methods of autoregistration double-pattern as claimed in claim 1, is characterized in that, described layer to be etched is Semiconductor substrate.
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CN105244259A (en) * 2015-10-14 2016-01-13 上海华力微电子有限公司 Structure and fabrication method of multiple patterning mask layer
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