CN103187260B - The formation method of fin formula field effect transistor - Google Patents
The formation method of fin formula field effect transistor Download PDFInfo
- Publication number
- CN103187260B CN103187260B CN201110459718.3A CN201110459718A CN103187260B CN 103187260 B CN103187260 B CN 103187260B CN 201110459718 A CN201110459718 A CN 201110459718A CN 103187260 B CN103187260 B CN 103187260B
- Authority
- CN
- China
- Prior art keywords
- sacrifice layer
- groove
- formation method
- field effect
- fin structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A formation method for fin formula field effect transistor, comprising: provide substrate, described substrate is formed with fin structure and is positioned at the second sacrifice layer on fin structure and surrounds the first sacrifice layer of described fin structure and the second sacrifice layer; Form the second groove, described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer; The sidewall of described second groove forms side wall; Along the first sacrifice layer described in the second etching groove being formed with side wall, form the 3rd groove, described 3rd groove exposes described fin structure; And grid structure is formed in described 3rd groove, described grid structure is across described fin structure.Described method can be avoided causing damage to fin structure and on fin structure, forming side wall residue, and then guarantees the formation of high performance fin formula field effect transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of fin formula field effect transistor.
Background technology
As everyone knows, transistor is the key element in integrated circuit.In order to improve the operating rate of transistor, need the drive current improving transistor.Again because the drive current of transistor is proportional to the grid width of transistor, therefore to improve drive current, just need to increase grid width.But, increase grid width and conflict mutually with the downsizing demand of the size of semiconductor own, so developed fin formula field effect transistor (FinFET).
In prior art, the formation method of fin formula field effect transistor (FinFET) comprising: provide substrate; Fin structure is formed over the substrate by the method for etching; On described substrate and fin structure, grid structure is formed by the method for etching; Side wall is formed in described grid structure both sides.As the publication No. Chinese patent application that is CN102074506A discloses a kind of formation method of fin formula field effect transistor.
In the above-mentioned methods, when formation grid structure, etching technics can damage the sidewall of described fin structure.In addition, in the forming process of described side wall, the sidewall of fin structure also can sustain damage and can adhere to one deck side wall residue.Side wall residue on the damage of above-mentioned fin structure and fin structure all will have influence on follow-up formed device performance.
Therefore, need a kind of formation method proposing new fin formula field effect transistor, avoid producing damage to fin structure and on fin structure, adhering to side wall residue, and then avoid described damage and side wall residue to cause adverse effect to follow-up formed device.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin formula field effect transistor, avoids causing damage to fin structure and on fin structure, forming side wall residue, and then guarantees the formation of high performance fin formula field effect transistor.
For solving the problem, embodiments providing a kind of formation method of fin formula field effect transistor, comprising:
Substrate is provided, described substrate is formed with fin structure and is positioned at the second sacrifice layer on fin structure and surrounds the first sacrifice layer of described fin structure and the second sacrifice layer;
Form the second groove, described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
The sidewall of described second groove forms side wall;
Along the first sacrifice layer described in the second etching groove being formed with side wall, form the 3rd groove, described 3rd groove exposes described fin structure; And
In described 3rd groove, form grid structure, described grid structure is across described fin structure.
Alternatively, if described substrate is silicon-on-insulator, described fin structure and the first sacrifice layer formation method comprise:
Form the second sacrifice layer;
Etch the top layer silicon of the second sacrifice layer and silicon-on-insulator, expose the buried layer of silicon-on-insulator, form fin structure; And
Form the first sacrifice layer, the buried layer exposed described in described first sacrifice layer covers and the second sacrifice layer after etching.
Alternatively, the formation method of described second groove comprises: etch described first sacrifice layer, forms described second groove.
Alternatively, described 3rd groove also exposes the buried layer of silicon-on-insulator.
Alternatively, described second sacrifice layer is formed by the top layer silicon of silicon on oxide isolated body.
Alternatively, if described substrate is body silicon, described fin structure and the first sacrifice layer formation method comprise:
Form the first sacrifice layer over the substrate;
In described first sacrifice layer, form the first groove, described first groove exposes described substrate;
In described first groove, form fin structure by epitaxial growth technology, the upper surface of described fin structure is lower than the first sacrifice layer upper surface; And
The upper surface of the described fin structure in described first groove forms the second sacrifice layer, and the upper surface of described second sacrifice layer is lower than the upper surface of described first sacrifice layer.
Alternatively, described 3rd groove does not expose described substrate.
Alternatively, the temperature of described epitaxial growth technology is 600 DEG C ~ 900 DEG C.
Alternatively, the formation method of described second groove comprises:
Described first sacrifice layer and the second sacrifice layer form hard mask layer, and described hard mask layer is different from described second sacrifice layer material;
Described hard mask layer is polished; And
Etch the hard mask layer and described first sacrifice layer that polish, form the second groove.
Alternatively, described hard mask layer comprises silicon nitride.
Alternatively, described second sacrifice layer is the upper surface formation by being oxidized described fin structure.
Alternatively, the height of described fin structure is 20nm ~ 100nm.
Alternatively, the thickness of described side wall is 10nm ~ 30nm.
Alternatively, described spacer material layer comprises polysilicon.
Alternatively, the formation method of described grid structure comprises: in the 3rd groove, deposit gate dielectric layer; Gate dielectric layer forms gate material layers; Cmp is carried out to described gate material layers and hard mask layer, stops at the first sacrifice layer.
Alternatively, described gate dielectric layer comprises high-k dielectric material.
Alternatively, the material of described grid is metal.
Alternatively, described first sacrifice layer comprises silica.
Compared with prior art, embodiments of the invention have the following advantages:
By surrounding the first sacrifice layer around described fin structure, side wall is formed by the sidewall that is formed in the second groove in the first sacrifice layer, and form grid structure by being formed in the 3rd groove in the first sacrifice layer, forming grid structure and formed in the side wall process of grid structure like this, described fin structure has the protection of the first sacrifice layer and/or the second sacrifice layer, be not subject to the damage of the technique of the side wall forming grid structure and form grid structure, therefore, fin structure crystal mass is higher, the performance of fin structure to the fin formula field effect transistor formed that can not resemble damaged of the prior art has an impact.
In addition, in an embodiment of the present invention, in the forming process of described side wall, there is hard mask layer as stop, therefore, more can not cause damage to fin structure, thus also can not affect the performance of the fin formula field effect transistor of follow-up formation.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the formation method of the fin formula field effect transistor of one embodiment of the invention;
Fig. 2 ~ 5, Fig. 7 ~ 8 and Figure 10 ~ 16 are middle 3-D solid structure schematic diagrames of the formation method of the fin formula field effect transistor of one embodiment of the invention;
Fig. 6 and 9 is the sectional median plane structural representation of the fin formula field effect transistor of one embodiment of the invention.
Embodiment
In prior art, the formation method of fin formula field effect transistor can cause damage to fin structure, and on fin structure, form side wall residue, thus causes the hydraulic performance decline of fin formula field effect transistor.For the problems referred to above, The embodiment provides a kind of formation method of fin formula field effect transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
Embodiments provide a kind of formation method of fin formula field effect transistor, please refer to Fig. 1, described method comprises:
Step S1, provides substrate, described substrate is formed with fin structure and is positioned at the second sacrifice layer on fin structure and surrounds the first sacrifice layer of described fin structure and the second sacrifice layer;
Step S2, forms the second groove, and described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
Step S3, the sidewall of described second groove forms side wall;
Step S4, along described in be formed with side wall the second etching groove described in the first sacrifice layer, form the 3rd groove, described 3rd groove exposes described fin structure; And
Step S5, in described 3rd groove, form grid structure, described grid structure is across described fin structure.
Lower mask body composition graphs 2 ~ Figure 16, the technical scheme that the embodiment of the present invention provides is described in detail, Fig. 2 ~ Fig. 5, Fig. 7 ~ 8 and Figure 10 ~ 16 are middle 3-D solid structure schematic diagrames of the formation method of the fin formula field effect transistor of one embodiment of the invention, Fig. 6 and Fig. 9 is the sectional median plane structural representation of the fin formula field effect transistor of one embodiment of the invention.
First, please refer to Fig. 2, perform step S1, substrate 1 is provided, described substrate 1 be formed with fin structure 4 and be positioned at the second sacrifice layer 5 on fin structure 4 and surround the first sacrifice layer 2 of described fin structure 4 and the second sacrifice layer 5.In embodiments of the present invention, described substrate 1 can be body silicon, can certainly be silicon-on-insulator, is hereafter body silicon with substrate for example is illustrated.Described first sacrifice layer 2 can comprise silica.
Described fin structure and the first sacrifice layer 2 form method and comprise: please refer to Fig. 2, and described substrate 1 is formed the first sacrifice layer 2.
Then, please refer to Fig. 3, etch described first sacrifice layer 2, in described first sacrifice layer 2, form the first groove 3, described first groove 3 exposes described substrate 1.
Then, please refer to Fig. 4, in described first groove 3, form fin structure 4 by epitaxial growth technology, the upper surface of described fin structure 4 is lower than the upper surface of the first sacrifice layer 2.
Then, please continue to refer to Fig. 4, the upper surface of the described fin structure 4 in described first groove 3 forms the second sacrifice layer 5, and the upper surface of described second sacrifice layer 5 is lower than the upper surface of described first sacrifice layer 2.
As one embodiment of the present of invention, the height of described fin structure can be about 20nm ~ 100nm, and the temperature of described epitaxial growth technology can be about 600 DEG C ~ 900 DEG C.
It should be noted that, in embodiments of the present invention, described fin structure 4 is formed by silicon epitaxy, hinge structure, described fin structure is not subject to the damage as being subject to when etching of the prior art forms fin structure self, the fin structure crystal mass that extension is formed is relatively good, and also can not sustain damage in follow-up formation grid structural manufacturing process.
In addition, described second sacrifice layer 5, using the resilient coating between the hard mask layer and fin structure 4 of follow-up formation, prevents from producing over etching in the process of follow-up formation second groove, thus avoids described over etching to cause damage to described fin structure 2,
In embodiments of the present invention, described second sacrifice layer 5 is formed by the upper surface of the described fin structure 4 of oxidation.
Then, please refer to Fig. 4 ~ 5, perform step S2, form the second groove 7, described second groove 7 bearing of trend is vertical with the bearing of trend of described fin structure 4, higher than the surface of described second sacrifice layer 5 bottom described second groove 7.In embodiments of the present invention, the formation method of described second groove 7 comprises: please refer to Fig. 4, and described first sacrifice layer 2 and the second sacrifice layer 5 form hard mask layer 6, and described hard mask layer 6 is different from described second sacrifice layer 5 material; Then, described hard mask layer 6 is polished; Then, please refer to Fig. 5, etch along the direction vertical with the bearing of trend of fin structure 4 hard mask layer 6 and described first sacrifice layer 2 that polish, form described second groove 7.
In embodiments of the present invention, described hard mask layer 6 can comprise silicon nitride, by cmp, described hard mask layer 6 is polished, the hard mask layer 6 polished described in etching and described first sacrifice layer 2, the method forming the second groove 7 comprises: on hard mask layer 6, form patterned first photoresist (not shown), and the side wall position of described patterned first photoresist layer and follow-up formation is corresponding; With described patterned photoresist for hard mask layer described in mask etching 6 and the first sacrifice layer 2, form described second groove 7.
It should be noted that, in embodiments of the present invention, in the etching process forming described second groove 7, need to etch described hard mask layer 6 and described first sacrifice layer 2 bi-material, due to described first sacrifice layer 2 and the second sacrifice layer 5 material close, if etch away the hard mask layer 6 on described second sacrifice layer 5 completely, the over etching to described second sacrifice layer 5 will be produced, thus damage is caused to described fin structure 4.Therefore, the second sacrifice layer 5 in described second groove 7 also should retain a part of hard mask layer 6, the hard mask layer 6 of described reservation for protecting described fin structure follow-up in the process forming side wall and grid structure.Please refer to Fig. 6, Fig. 6 is the cross-sectional view of Fig. 5 along y-z plane.
Then, please refer to Fig. 7, perform step S3, on the sidewall of described second groove 7, form side wall 8, for providing one section of transitional region when follow-up source/drain region is spread, preventing follow-up source/drain from injecting to raceway groove diffusion too many.In embodiments of the present invention, the formation method of side wall 8 comprises: in described second groove 7, deposit spacer material layer; Described spacer material layer forms patterned second photoresist, and the grid locations of structures of described patterned second photoresist layer and follow-up formation is corresponding; Etch described spacer material layer with described patterned second photoresist layer and form side wall 8.In embodiments of the present invention, described spacer material layer can be polysilicon.
In embodiments of the present invention, the thickness of described side wall 8 can be about 10nm ~ 30nm.
It should be noted that, in the formation etching process of described side wall 8, have the hard mask layer 6 of described reservation as stop, fin structure 4 surface can not produce damage.
Then, please refer to Fig. 8, perform step S4.Etch the first sacrifice layer 2 of described fin structure both sides, form the 3rd groove 9, described 3rd groove 9 exposes described fin structure 2, forms grid structure so that follow-up in described 3rd groove 9.In embodiments of the present invention, the substrate in described 3rd groove 9 still retains described first sacrifice layer 2 of a part, for isolated gate structure and substrate.Please refer to Fig. 9, Fig. 9 is the cross-sectional view of Fig. 8 along x-y plane.
It should be noted that, as shown in Figure 9, described second sacrifice layer 5 on described fin structure and the hard mask layer 6 of described reservation after forming the second groove are consumed in the etching process of above-mentioned formation the 3rd groove 9, described 3rd groove 9 exposes described fin structure 2, the grid structure formed on described fin structure so that follow-up.
Then, please refer to Figure 10, perform step S5.Grid structure 10 is formed in described 3rd groove 9.In an embodiment of the present invention, the formation method of described grid structure 10 comprises: heavy gate dielectric layer (not shown) in the 3rd groove 9; Described gate dielectric layer is formed grid (not shown); Cmp is carried out to described grid and hard mask layer 6, stops at the first sacrifice layer 2.As one embodiment of the present of invention, described gate dielectric layer can comprise high-k dielectric material, and described grid can be metal gates.
It should be noted that, described grid structure 10 is formed by depositing operation, and hinge structure can not damage fin structure 4.
Finally, please refer to Figure 11, in embodiments of the present invention, the formation method of fin formula field effect transistor, also comprises: after the described grid structure 10 of formation, remove the hard mask layer 6 on described second sacrifice layer 5; Source/drain doping is carried out in the both sides of described fin structure 10; Remove described second sacrifice layer 5.
In the above-described embodiments, be that body silicon is illustrated for substrate, described substrate can also be silicon-on-insulator.If substrate is silicon-on-insulator, the method of the fin formula field effect transistor of the formation method embodiment of the present invention is similar, difference is: please refer to Figure 12, first top layer silicon 11 surface of silicon 10 forms the second sacrifice layer 21 on insulator, and described second sacrifice layer 21 can be formed by the top layer silicon 11 of silicon 10 on oxide isolated body; Then, please refer to Figure 13, etch the top layer silicon 11 of the second sacrifice layer 21 and silicon-on-insulator 10, expose the buried layer 12 of described silicon-on-insulator 10, form fin structure 11 ' and the second sacrifice layer 21 '; Then, please refer to Figure 14, form the first sacrifice layer 30, the buried layer 12 exposed described in described first sacrifice layer 30 covers and the second sacrifice layer 21 ' after etching.
Then, please refer to Figure 15, etch described first sacrifice layer 30 to form bearing of trend second groove 31 vertical with the bearing of trend of described fin structure 11 ', certainly, in described first sacrifice layer 30 process of etching, described first sacrifice layer 30 surface can also be coated with mask layer (not shown), can be such as photoresist or silicon nitride, the bottom surface of described second groove 31 does not expose described second sacrifice layer 21 ', and namely the bottom surface of described second groove 31 is higher than the surface of described second sacrifice layer 21 '.
Then form side wall 31 ' at described second groove 31 sidewall, concrete formation method and previous embodiment similar, do not add detailed description.
Then, please refer to Figure 16, etching first sacrifice layer 30 is continued on the basis that sidewall is formed the second groove 31 of spacer material, form the 3rd groove 32, described 3rd groove 32 bottom-exposed goes out the buried layer 12 of described silicon-on-insulator, can certainly exceed buried layer 12, and described 3rd groove 32 is for the formation of grid structure, technique and the previous embodiment of concrete formation grid structure are similar, do not add detailed description at this.
In sum, embodiments of the invention have the following advantages:
By surrounding the first sacrifice layer around described fin structure, side wall is formed by the sidewall that is formed in the second groove in the first sacrifice layer, and form grid structure by being formed in the 3rd groove in the first sacrifice layer, forming grid structure and formed in the side wall process of grid structure like this, described fin structure has the protection of the first sacrifice layer and/or the second sacrifice layer, be not subject to the damage of the technique of the side wall forming grid structure and form grid structure, therefore, fin structure crystal mass is higher, the performance of fin structure to the fin formula field effect transistor formed that can not resemble damaged of the prior art has an impact.
In addition, in an embodiment of the present invention, in the forming process of described side wall, there is hard mask layer as stop, therefore, more can not cause damage to fin structure, thus also can not affect the performance of the fin formula field effect transistor of follow-up formation.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (15)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Substrate is provided, described substrate is formed with fin structure and is positioned at the second sacrifice layer on fin structure and surrounds the first sacrifice layer of described fin structure and the second sacrifice layer;
Form the second groove, described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
The sidewall of described second groove forms side wall;
Along the first sacrifice layer described in the second etching groove being formed with side wall, form the 3rd groove, described 3rd groove exposes described fin structure; And
In described 3rd groove, form grid structure, described grid structure is across described fin structure;
Wherein, described fin structure and the first sacrifice layer formation method comprise:
Form the first sacrifice layer over the substrate;
In described first sacrifice layer, form the first groove, described first groove exposes described substrate;
In described first groove, form fin structure by epitaxial growth technology, the upper surface of described fin structure is lower than the first sacrifice layer upper surface; And
The upper surface of the described fin structure in described first groove forms the second sacrifice layer, and the upper surface of described second sacrifice layer is lower than the upper surface of described first sacrifice layer;
The formation method of described second groove comprises:
Described first sacrifice layer and the second sacrifice layer form hard mask layer, and described hard mask layer is different from described second sacrifice layer material;
Described hard mask layer is polished; And
Etch the hard mask layer and described first sacrifice layer that polish, form the second groove.
2. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, described substrate is silicon-on-insulator.
3. the formation method of fin formula field effect transistor as claimed in claim 2, is characterized in that, described second sacrifice layer is formed by the top layer silicon of silicon on oxide isolated body.
4. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, described substrate is body silicon.
5. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, described 3rd groove does not expose described substrate.
6. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, the temperature of described epitaxial growth technology is 600 DEG C ~ 900 DEG C.
7. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, described hard mask layer comprises silicon nitride.
8. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, described second sacrifice layer is that the upper surface by being oxidized described fin structure is formed.
9. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, the height of described fin structure is 20nm ~ 100nm.
10. the formation method of fin formula field effect transistor as claimed in claim 1, it is characterized in that, the thickness of described side wall is 10nm ~ 30nm.
The formation method of 11. fin formula field effect transistors as claimed in claim 1, it is characterized in that, described spacer material layer comprises polysilicon.
The formation method of 12. fin formula field effect transistors as claimed in claim 1, it is characterized in that, the formation method of described grid structure comprises: in the 3rd groove, deposit gate dielectric layer; Gate dielectric layer forms gate material layers; Cmp is carried out to described gate material layers and hard mask layer, stops at the first sacrifice layer.
The formation method of 13. fin formula field effect transistors as claimed in claim 12, it is characterized in that, described gate dielectric layer comprises high-k dielectric material.
The formation method of 14. fin formula field effect transistors as claimed in claim 12, is characterized in that, the material of described grid is metal.
The formation method of 15. fin formula field effect transistors as claimed in claim 1, it is characterized in that, described first sacrifice layer comprises silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110459718.3A CN103187260B (en) | 2011-12-31 | 2011-12-31 | The formation method of fin formula field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110459718.3A CN103187260B (en) | 2011-12-31 | 2011-12-31 | The formation method of fin formula field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187260A CN103187260A (en) | 2013-07-03 |
| CN103187260B true CN103187260B (en) | 2016-03-16 |
Family
ID=48678370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110459718.3A Active CN103187260B (en) | 2011-12-31 | 2011-12-31 | The formation method of fin formula field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187260B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979202B (en) * | 2014-04-04 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| US10199480B2 (en) * | 2016-09-29 | 2019-02-05 | Globalfoundries Inc. | Controlling self-aligned gate length in vertical transistor replacement gate flow |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201003796A (en) * | 2008-07-02 | 2010-01-16 | Promos Technologies Inc | Method for preparing FinFET device |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100505712B1 (en) * | 2003-10-22 | 2005-08-02 | 삼성전자주식회사 | Method for fabricating recess channel array transistor |
| KR100620446B1 (en) * | 2004-03-09 | 2006-09-12 | 삼성전자주식회사 | Fin field effect transistor and method of manufacturing the same |
| KR100532353B1 (en) * | 2004-03-11 | 2005-11-30 | 삼성전자주식회사 | FinFET and Method of manufacturing the same |
| KR20060027440A (en) * | 2004-09-22 | 2006-03-28 | 삼성전자주식회사 | Capacitively coupled junction finfet(fin field effect transistor), method of manufacturing for the same and cmos(complementary metal oxide semiconductor) transistor employing the same |
| JP4648096B2 (en) * | 2005-06-03 | 2011-03-09 | 株式会社東芝 | Manufacturing method of semiconductor device |
| KR100657969B1 (en) * | 2005-08-30 | 2006-12-14 | 삼성전자주식회사 | Method of fabricating a semiconductor device having a single gate electrode corresponding a pair of fin-type channel regions |
| KR100945925B1 (en) * | 2007-12-20 | 2010-03-05 | 주식회사 하이닉스반도체 | Method for forming saddle Fin type transistor |
| US20090283829A1 (en) * | 2008-05-13 | 2009-11-19 | International Business Machines Corporation | Finfet with a v-shaped channel |
| US8519476B2 (en) * | 2009-12-21 | 2013-08-27 | Alpha And Omega Semiconductor Incorporated | Method of forming a self-aligned charge balanced power DMOS |
-
2011
- 2011-12-31 CN CN201110459718.3A patent/CN103187260B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201003796A (en) * | 2008-07-02 | 2010-01-16 | Promos Technologies Inc | Method for preparing FinFET device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187260A (en) | 2013-07-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8525234B2 (en) | Formation of FinFET gate spacer | |
| US20140117454A1 (en) | FinFET with Dummy Gate on Non-Recessed Shallow Trench Isolation (STI) | |
| CN107452679B (en) | Semiconductor device and method for manufacturing the same | |
| CN104795332A (en) | Fin-type field effect transistor forming method | |
| CN103560153B (en) | A kind of tunneling field-effect transistor and preparation method thereof | |
| JP2007200972A (en) | Semiconductor device and manufacturing method thereof | |
| US10236383B2 (en) | Method for fabricating semiconductor device | |
| WO2017035780A1 (en) | Tunnel field-effect transistor and manufacturing method thereof | |
| US9356124B2 (en) | Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure | |
| CN103515282A (en) | Fin field-effect transistor and forming method thereof | |
| WO2012100563A1 (en) | Method for preparing germanium-based schottky n-type field effect transistor | |
| CN104319290B (en) | Three grid graphene fin formula field effect transistors and its manufacturing method | |
| CN103311123A (en) | Semiconductor device manufacturing method | |
| CN104517848A (en) | LDMOS (lateral double-diffused metal oxide semiconductor) transistor structure and formation method thereof | |
| CN205749689U (en) | A kind of test structure of fin formula field effect transistor parasitic capacitance | |
| CN103187260B (en) | The formation method of fin formula field effect transistor | |
| CN103515283A (en) | Semiconductor device manufacturing method | |
| US20170287723A1 (en) | Semiconductor device and method for fabricating the same | |
| CN103594362A (en) | Fin field effect transistor and manufacture method thereof | |
| CN104217948B (en) | Semiconductor manufacturing method | |
| CN105047701A (en) | Method for preparing fin-shaped semiconductor device with suspended grid electrode | |
| CN103187300B (en) | Fin formula field effect transistor and forming method thereof | |
| CN104425371A (en) | Method for forming semiconductor structure | |
| US10600692B2 (en) | Semiconductor device | |
| CN103367432B (en) | Multiple gate field effect transistor and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |