CN103187260A - Formation method of fin field effect transistor - Google Patents

Formation method of fin field effect transistor Download PDF

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CN103187260A
CN103187260A CN2011104597183A CN201110459718A CN103187260A CN 103187260 A CN103187260 A CN 103187260A CN 2011104597183 A CN2011104597183 A CN 2011104597183A CN 201110459718 A CN201110459718 A CN 201110459718A CN 103187260 A CN103187260 A CN 103187260A
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forming
sacrificial layer
trench
method
layer
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CN2011104597183A
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CN103187260B (en
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卜伟海
康劲
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中芯国际集成电路制造(上海)有限公司
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Abstract

A formation method of a fin field effect transistor comprises the following steps: providing a substrate, forming a fin structure, a second sacrificial layer located on the fin structure and a first sacrificial layer surrounding the fin structure and the second sacrificial layer; forming a second groove, wherein the extending direction of the second groove is vertical to the extending direction of the fin structure, and the bottom of the second groove is higher than the surface of the second sacrificial layer; forming a sidewall on a side wall of the second groove; sculpturing the first sacrificial layer along the second groove with the sidewall, forming a third groove, wherein the third groove is exposed out from the fin structure; and forming a gate structure in the third groove, wherein the gate structure stretches across the fin structure. The method can prevent the fin structure from being damaged and prevent sidewall residuum from forming on the fin structure, so that the formation of the fin field effect transistor with high performance is ensured.

Description

鳍式场效应晶体管的形成方法 A method of forming a fin field effect transistor

技术领域 FIELD

[0001] 本发明涉及半导体技术领域,特别涉及一种鳍式场效应晶体管的形成方法。 [0001] The present invention relates to semiconductor technology, and particularly relates to a method of forming a fin field effect transistor.

背景技术 Background technique

[0002] 众所周知,晶体管是集成电路中的关键元件。 [0002] is well known, an integrated circuit transistor is a key element. 为了提高晶体管的工作速度,需要提高晶体管的驱动电流。 In order to improve the speed of the transistor, necessary to increase the driving current of the transistor. 又由于晶体管的驱动电流正比于晶体管的栅极宽度,因此要提高驱动电流,就需要增加栅极宽度。 Also, because the driving current of the transistor is proportional to the gate width of the transistor, so to increase the driving current, it is necessary to increase the gate width. 但是,增加栅极宽度与半导体本身尺寸的缩小化需求相冲突,于是发展出了鳍式场效应晶体管(FinFET)。 However, the gate width of the semiconductor itself, the reduction in size of the conflicting requirements, then developed a fin field effect transistor (FinFET).

[0003] 现有技术中,鳍式场效应晶体管(FinFET)的形成方法包括:提供衬底;在所述衬底上通过刻蚀的方法形成鳍结构;通过刻蚀的方法在所述衬底和鳍结构上形成栅结构;在所述栅结构两侧形成侧墙。 [0003] In the prior art, a method of forming a fin field effect transistor (FinFET) comprising: providing a substrate; forming a fin structure by the method of etching on the substrate; by the method of etching the substrate and forming a gate structure over the fin structure; forming spacers on both sides of the gate structure. 如公布号为CN102074506A的中国专利申请公开了一种鳍式场效应晶体管的形成方法。 As Publication No. CN102074506A the Chinese Patent Application discloses a method of forming a fin field effect transistor.

[0004] 在上述方法中,在形成栅结构的时候,刻蚀工艺会损伤所述鳍结构的侧壁。 In the above method, at the time of forming the gate structure, the sidewall of the fin structure damage [0004] The etching process will be. 另外,在所述侧墙的形成过程,鳍结构的侧壁也会受到损伤且会粘附一层侧墙残留物。 Further, during the formation of the sidewall, the sidewalls of the fin and the structure will be damaged spacer layer adheres residue. 上述鳍结构的损伤以及鳍结构上的侧墙残留物都将影响到后续所形成的器件性能。 Damage and residue on the sidewall of the fin structure above the fin structure will affect the device performance of the subsequently formed.

[0005] 因此,需要提出一种新的鳍式场效应晶体管的形成方法,避免对鳍结构产生损伤和在鳍结构上粘附侧墙残留物,进而避免所述损伤和侧墙残留物给后续所形成的器件造成不利影响。 [0005] Accordingly, a method is proposed to form a new fin field effect transistor, to avoid damage to the fin structure and the adhesive residues on the sidewall of the fin structure, thereby avoiding damage to the spacers and to the subsequent residue the formed adversely affected.

发明内容 SUMMARY

[0006] 本发明解决的问题是提供一种鳍式场效应晶体管的形成方法,避免对鳍结构造成损伤和在鳍结构上形成侧墙残留物,进而确保高性能的鳍式场效应晶体管的形成。 [0006] The present invention solves the problem to provide a method of forming a fin field effect transistor, and to avoid damage to the fin structure is formed on a sidewall of the fin structure residues, thereby ensuring a high-performance of FinFETs .

[0007] 为解决上述问题,本发明实施例提供了一种鳍式场效应晶体管的形成方法,包括: [0007] In order to solve the above problems, embodiments of the present invention provides a method of forming a fin field effect transistor, comprising:

[0008] 提供衬底,所述衬底上形成有鳍结构和位于鳍结构上的第二牺牲层、以及包围所述鳍结构和第二牺牲层的第一牺牲层; [0008] providing a substrate on which the fin structure and the sacrificial layer located on the second fin structure, a first sacrificial layer surrounds the fin structure and the second sacrificial layer;

[0009] 形成第二沟槽,所述第二沟槽延伸方向与所述鳍结构的延伸方向垂直,所述第二沟槽底部高于所述第二牺牲层的表面; [0009] forming a second trench extending in a direction perpendicular to the groove extending direction of the second fin structure, the surface of the second sacrificial layer in the second trench above the bottom;

[0010] 在所述第二沟槽的侧壁上形成侧墙; [0010] forming spacers on sidewalls of the second trench;

[0011] 沿形成有侧墙的第二沟槽刻蚀所述第一牺牲层,形成第三沟槽,所述第三沟槽暴露出所述鳍结构;以及 [0011] The second trench etching the first sacrificial layer is formed along the sidewall, forming a third trench, the third trench to expose the fin structure; and

[0012] 在所述第三沟槽内形成栅结构,所述栅结构横跨所述鳍结构。 [0012] The gate structure is formed in the third trench, the gate structure across said fin structure.

[0013] 可选地,若所述衬底是绝缘体上硅,所述鳍结构和第一牺牲层形成方法包括: [0013] Alternatively, if the substrate is a silicon on insulator, said fin structure and the method of the first sacrificial layer comprises:

[0014] 形成第二牺牲层; [0014] forming a second sacrificial layer;

[0015] 刻蚀第二牺牲层和绝缘体上硅的顶层硅,暴露出绝缘体上硅的掩埋层,形成鳍结构;以及[0016] 形成第一牺牲层,所述第一牺牲层覆盖所述暴露出的掩埋层和刻蚀后的第二牺牲层。 [0015] etching the second sacrificial layer and the silicon-on-insulator top silicon layer, to expose a buried layer of silicon-on-insulator, forming a fin structure; and [0016] forming a first sacrificial layer, the first sacrificial layer covering the exposed a buried layer and the second sacrificial layer after etching.

[0017] 可选地,所述第二沟槽的形成方法包括:刻蚀所述第一牺牲层,形成所述第二沟槽。 [0017] Alternatively, the method of forming the second trench comprises: etching the first sacrificial layer, forming the second trench.

[0018] 可选地,所述第三沟槽还暴露出绝缘体上硅的掩埋层。 [0018] Alternatively, the third trench further expose a buried layer of silicon-on-insulator.

[0019] 可选地,所述第二牺牲层通过氧化绝缘体上硅的顶层硅形成。 [0019] Alternatively, the top silicon layer silicon on insulator by oxidizing the second sacrificial layer is formed.

[0020] 可选地,若所述衬底是体硅,所述鳍结构和第一牺牲层形成方法包括: [0020] Alternatively, if the substrate is a silicon body, the method of the first fin structure and the sacrificial layer comprises:

[0021 ] 在所述衬底上形成第一牺牲层; [0021] forming a first sacrificial layer on the substrate;

[0022] 在所述第一牺牲层中形成第一沟槽,所述第一沟槽暴露出所述衬底; [0022] forming a first trench in the first sacrificial layer, exposing the substrate, the first trench;

[0023] 在所述第一沟槽内通过外延生长工艺形成鳍结构,所述鳍结构的上表面低于第一牺牲层上表面;以及 [0023] formed within the trench by epitaxial growth process first fin structure, the fin structure on the surface of the first sacrificial layer below the upper surface;

[0024] 在所述第一沟槽内的所述鳍结构的上表面形成第二牺牲层,所述第二牺牲层的上表面低于所述第一牺牲层的上表面。 [0024] The upper surface of the fin structure in the first trench to form a second sacrificial layer, the upper surface of the second sacrificial layer is lower than the upper surface of the first sacrificial layer.

[0025] 可选地,所述第三沟槽未暴露出所述衬底。 [0025] Alternatively, the third trench does not expose the substrate.

[0026] 可选地,所述外延生长工艺的温度为600°C〜900°C。 [0026] Alternatively, the epitaxial growth process temperature is 600 ° C~900 ° C.

[0027] 可选地,所述第二沟槽的形成方法包括: [0027] Alternatively, the method of forming the second trench comprises:

[0028] 在所述第一牺牲层和第二牺牲层上形成硬质掩膜层,所述硬质掩膜层与所述第二牺牲层材质不同; [0028] forming a hard mask layer on the first sacrificial layer and the second sacrificial layer, the hard mask layer and the second sacrificial layer is made of different materials;

[0029] 将所述硬质掩膜层磨平;以及 [0029] The polished hard mask layer; and

[0030] 刻蚀磨平的硬质掩膜层和所述第一牺牲层,形成第二沟槽。 [0030] etching the polished hard mask layer and the first sacrificial layer, forming a second trench.

[0031] 可选地,所述硬质掩膜层包含氮化硅。 [0031] Optionally, the hard mask layer comprises silicon nitride.

[0032] 可选地,所述第二牺牲层是通过氧化所述鳍结构的上表面形成。 [0032] Alternatively, the second sacrificial layer is formed by oxidizing the surface of the fin structure.

[0033] 可选地,所述鳍结构的高度为20nm〜lOOnm。 [0033] Alternatively, the height of the fin structure 20nm~lOOnm.

[0034] 可选地,所述侧墙的厚度为IOnm〜30nm。 [0034] Alternatively, the sidewall thickness of IOnm~30nm.

[0035] 可选地,所述侧墙材料层包括多晶硅。 [0035] Alternatively, the spacer material layer comprises polysilicon.

[0036] 可选地,所述栅结构的形成方法包括:在第三沟槽中沉积栅介质层;在栅介质层上形成栅极材料层;对所述栅极材料层和硬质掩膜层进行化学机械研磨,停止于第一牺牲层。 [0036] Alternatively, the method of forming the gate structure comprises: depositing a gate dielectric layer in the third trench; forming a layer of gate material on the gate dielectric layer; the gate material layer and a hard mask on layer chemical mechanical polishing is stopped in the first sacrificial layer.

[0037] 可选地,所述栅介质层包括高k介电材料。 [0037] Alternatively, the gate dielectric layer comprises a high k dielectric material.

[0038] 可选地,所述栅极的材料为金属。 [0038] Alternatively, the gate material is a metal.

[0039] 可选地,所述第一牺牲层包括氧化硅。 [0039] Alternatively, the first sacrificial layer comprises silicon oxide.

[0040] 与现有技术相比,本发明的实施例具有以下优点: [0040] Compared with the prior art, embodiments of the present invention have the following advantages:

[0041] 通过在所述鳍结构周围包围第一牺牲层、通过形成在第一牺牲层中的第二沟槽的侧壁上形成侧墙、以及通过形成在第一牺牲层中的第三沟槽内形成栅结构,这样在形成栅结构和形成栅结构的侧墙过程中,所述鳍结构具有第一牺牲层和/或第二牺牲层的保护,没有受到形成栅结构以及形成栅结构的侧墙的工艺的损伤,因此,鳍结构晶体质量较高,不会象现有技术中的受损伤的鳍结构对形成的鳍式场效应晶体管的性能产生影响。 [0041] By around the fin structure surrounds the first sacrificial layer, is formed by spacers on the sidewalls of the second trench is formed in the first sacrificial layer, and by a third groove formed in the first sacrificial layer groove formed gate structure, the gate structure is formed so that the process of sidewall gate structure formed in the first fin structure having a protective sacrificial layer and / or the second sacrificial layer is not formed by the gate structure and forming a gate structure damage process spacers, and therefore, high quality crystal structure of the fin, is not damaged as in the prior art fin structure affect the performance of FinFETs formed.

[0042] 另外,在本发明的实施例中,在所述侧墙的形成过程中,有硬质掩膜层作为阻挡,因此,更不会对鳍结构造成损伤,从而也不会影响后续形成的鳍式场效应晶体管的性能。 [0042] Further, in the embodiment of the present invention, during formation of the sidewall, a hard mask as a barrier layer, and therefore, will not cause damage to the fin structure, thereby not affecting the subsequent formation the performance of the FinFET. 附图说明 BRIEF DESCRIPTION

[0043] 图1是本发明一个实施例的鳍式场效应晶体管的形成方法的流程示意图; [0043] FIG. 1 is a schematic flow diagram of a method of forming a fin field effect transistor according to one embodiment of the present invention;

[0044] 图2〜5、图7〜8和图10〜16是本发明一个实施例的鳍式场效应晶体管的形成方法的中间三维立体结构示意图; [0044] FIG. 2 ~ 5, and FIGS. 7~8 10~16 intermediate is a schematic view of the method of three-dimensional structure of a FinFET embodiment of the present invention is formed;

[0045] 图6和9为本发明一个实施例的鳍式场效应晶体管的中间剖面结构示意图。 [0045] FIGS. 6 and 9, intermediate a schematic cross-sectional structure of the FinFET embodiment of a present invention. 具体实施方式 Detailed ways

[0046] 现有技术中,鳍式场效应晶体管的形成方法会给鳍结构造成损伤,并在鳍结构上形成侧墙残留物,从而造成鳍式场效应晶体管的性能下降。 [0046] In the prior art, a method of forming a fin field effect transistor will damage the fin structure, and forming spacers on the fin structure in the residue, causing the performance of FinFETs decreases. 针对上述问题,本发明的实施例提供了一种鳍式场效应晶体管的形成方法。 In response to these problems, embodiments of the present invention provides a method of forming a fin field effect transistor.

[0047] 为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。 [0047] For the above-described objects, features and advantages of the present invention can be more fully understood by reading the following description of the drawings in detail specific embodiments of the present invention binds.

[0048] 在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是本发明还可以采用其他不同于在此描述的其它方式来实施,因此本发明不受下面公开的具体实施例的限制。 [0048] forth in the following description, numerous specific details in order to provide a thorough understanding of the present invention, the present invention also in other ways other than described may be employed to implement, therefore the present invention is not limited to the specific embodiments disclosed below limit.

[0049] 本发明实施例提供了一种鳍式场效应晶体管的形成方法,请参考图1,所述方法包括: [0049] The embodiment provides a method of forming a fin field effect transistor of the present invention, please refer to FIG. 1, the method comprising:

[0050] 步骤SI,提供衬底,所述衬底上形成有鳍结构和位于鳍结构上的第二牺牲层、以及包围所述鳍结构和第二牺牲层的第一牺牲层; [0050] Step the SI, providing a substrate on which the fin structure and the sacrificial layer located on the second fin structure, the fin structure surrounds the first sacrificial layer and the second sacrificial layer;

[0051] 步骤S2,形成第二沟槽,所述第二沟槽延伸方向与所述鳍结构的延伸方向垂直,所述第二沟槽底部高于所述第二牺牲层的表面; [0051] Step S2, the second trench is formed, a direction perpendicular to the extending direction of the second trench extending fin structure, the surface of the second sacrificial layer in the second trench above the bottom;

[0052] 步骤S3,在所述第二沟槽的侧壁上形成侧墙; [0052] Step S3, the spacers are formed on sidewalls of the second trench;

[0053] 步骤S4,沿所述形成有侧墙的第二沟槽刻蚀所述第一牺牲层,形成第三沟槽,所述第三沟槽暴露出所述鳍结构;以及 [0053] step S4, is formed along the second trench etching the first sacrificial layer sidewall spacers, forming a third trench, the third trench to expose the fin structure; and

[0054] 步骤S5,在所述第三沟槽内形成栅结构,所述栅结构横跨所述鳍结构。 [0054] Step S5, the gate structure is formed in the third trench, the gate structure across said fin structure.

[0055] 下面具体结合图2〜图16,对本发明实施例提供的技术方案进行详细的说明,图2〜图5、图7〜8和图10〜16是本发明一个实施例的鳍式场效应晶体管的形成方法的中间三维立体结构示意图,图6和图9为本发明一个实施例的鳍式场效应晶体管的中间剖面结构示意图。 [0055] 2 ~ in detail below in conjunction with FIG 16, the technical solutions provided by the detailed description of the embodiment of the present invention, FIG. 2 ~ 5, and FIGS. 7~8 10~16 fin field is an embodiment of the present invention a schematic view of an intermediate structure of the method of the three-dimensional effect transistor is formed, FIG. 6 and FIG 9 intermediate a schematic cross-sectional structure of the FinFET embodiment of the present invention.

[0056] 首先,请参考图2,执行步骤SI,提供衬底1,所述衬底I上形成有鳍结构4和位于鳍结构4上的第二牺牲层5、以及包围所述鳍结构4和第二牺牲层5的第一牺牲层2。 [0056] First, referring to FIG 2, the SI step, the substrate 1 provided with the fin structure of the fin structure 4 and the second sacrificial layer 5, 4, 4 and surrounding said fin structure formed on the substrate I the first sacrificial layer and the second sacrificial layer 5 is 2. 在本发明实施例中,所述衬底I可以为体硅,当然也可以为绝缘体上硅,下文以衬底为体硅为例加以说明。 In an embodiment of the present invention, the substrate may be a bulk silicon I may of course be an insulator on the silicon, bulk silicon substrate below as an example will be described. 所述第一牺牲层2可以包括氧化硅。 The first sacrificial layer 2 may include silicon oxide.

[0057] 所述鳍结构和第一牺牲层2形成方法包括:请参考图2,在所述衬底I上形成第一牺牲层2。 2 The method of forming the [0057] first fin structure and the sacrificial layer comprises: Referring to FIG 2, a first sacrificial layer 2 is formed on the substrate I.

[0058] 接着,请参考图3,刻蚀所述第一牺牲层2,在所述第一牺牲层2中形成第一沟槽3,所述第一沟槽3暴露出所述衬底I。 [0058] Next, please refer to FIG. 3, etching the first sacrificial layer 2, a first groove 3 is formed in the first sacrificial layer 2, the first trenches exposing the substrate I 3 .

[0059] 然后,请参考图4,在所述第一沟槽3内通过外延生长工艺形成鳍结构4,所述鳍结构4的上表面低于第一牺牲层2的上表面。 [0059] Then, referring to FIG 4, 4, the upper surface of the fin structure 4 is lower than the upper surface of the first sacrificial layer 2 in the first trench 3 is formed by an epitaxial growth process fin structure.

[0060] 然后,请继续参考图4,在所述第一沟槽3内的所述鳍结构4的上表面形成第二牺牲层5,所述第二牺牲层5的上表面低于所述第一牺牲层2的上表面。 [0060] Then, with continued reference to FIG. 4, on the inner surface of the first groove 3 of the fin structure 4 forming a second sacrificial layer 5, an upper surface of the second sacrificial layer 5 is lower than the upper surface of the first sacrificial layer 2.

[0061] 作为本发明的一个实施例,所述鳍结构的高度可以约为20nm〜IOOnm,所述外延生长工艺的温度可以约为600°C〜900°C。 [0061] As one embodiment of the present invention, the height of the fin structure may be about 20nm~IOOnm, the temperature of the epitaxial growth process may be approximately 600 ° C~900 ° C.

[0062] 需要说明的是,在本发明实施例中,所述鳍结构4是通过硅外延形成的,相对现有技术,所述鳍结构没有受到如现有技术中的刻蚀形成鳍结构自身时受到的损伤,外延形成的鳍结构晶体质量比较好,而且在后续形成栅结构工艺中也不会受到损伤。 [0062] Incidentally, in the embodiment of the present invention, the fin structure 4 is formed by the epitaxial silicon, over the prior art, the fin structure as the prior art has not been etched to form a fin structure itself when subjected to damage, the crystal quality of the fin structure is formed epitaxially is better, but also in the gate structure is formed in the subsequent processes will not be damaged.

[0063] 另外,所述第二牺牲层5将作为后续形成的硬质掩膜层和鳍结构4之间的缓冲层,防止后续形成第二沟槽的过程中产生过刻蚀,从而避免所述过刻蚀对所述鳍结构2造成损伤, [0063] Further, during the second sacrificial layer 5 as a buffer layer between the hard mask layer and the subsequent formation of the fin structure 4, to prevent the subsequent formation of the second trench is etched through to produce, thereby avoiding the said over-etching damage to the fin structure 2,

[0064] 在本发明实施例中,所述第二牺牲层5通过氧化所述鳍结构4的上表面形成。 [0064] In an embodiment of the present invention, the second sacrificial layer 5 is formed by oxidizing the surface of the fin structure 4.

[0065] 接着,请参考图4〜5,执行步骤S2,形成第二沟槽7,所述第二沟槽7延伸方向与所述鳍结构4的延伸方向垂直,所述第二沟槽7底部高于所述第二牺牲层5的表面。 [0065] Next, referring to FIG. 4 to 5, step S2, a second trench 7 is formed, the second trench 7 extending in a direction perpendicular to the extending direction of the fin structure 4, the second trench 7 surface of the second sacrificial layer 5 is higher than the bottom. 在本发明实施例中,所述第二沟槽7的形成方法包括:请参考图4,在所述第一牺牲层2和第二牺牲层5上形成硬质掩膜层6,所述硬质掩膜层6与所述第二牺牲层5材质不同;接着,将所述硬质掩膜层6磨平;然后,请参考图5,沿与鳍结构4的延伸方向垂直的方向刻蚀磨平的硬质掩膜层6和所述第一牺牲层2,形成所述第二沟槽7。 In an embodiment of the present invention, a method of forming the second trench comprises 7: Please refer to FIG. 4, the hard mask layer 6 is formed on the second sacrificial layer 2 and the first sacrificial layer 5, the hard quality mask layer 6 and the second sacrificial layer 5 made of different materials; Subsequently, the hard mask layer 6 is polished; then, referring to FIG 5, extending along a direction perpendicular to the fin structure 4 in the direction of etching polished hard mask layer 6 and the first sacrificial layer 2, the second trench 7 is formed.

[0066] 在本发明实施例中,所述硬质掩膜层6可以包括氮化硅,通过化学机械研磨将所述硬质掩膜层6磨平,刻蚀所述磨平的硬质掩膜层6和所述第一牺牲层2,形成第二沟槽7的方法包括:在硬质掩膜层6上形成图形化的第一光刻胶(未示出),所述图形化的第一光刻胶层和后续形成的侧墙位置对应;以所述图形化的光刻胶为掩膜刻蚀所述硬质掩膜层6和第一牺牲层2,形成所述第二沟槽7。 [0066] In an embodiment of the present invention, the hard mask may comprise silicon nitride layer 6, by chemical mechanical polishing to the polished hard mask layer 6, the etching the hard mask polished is formed on the hard layer 6, a first photoresist mask (not shown) is patterned, the patterned: film 6 and the first sacrificial layer 2, the method includes forming the second trench 7 a first photoresist layer and a position corresponding to the subsequently formed sidewall; using the patterned photoresist as a mask and etching the hard mask layer 6 and the first sacrificial layer 2, forming the second groove 7 slot.

[0067] 需要说明的是,在本发明实施例中,在形成所述第二沟槽7的刻蚀过程中,需要对所述硬质掩膜层6和所述第一牺牲层2两种材料进行刻蚀,由于所述第一牺牲层2和第二牺牲层5材料接近,如果完全刻蚀掉所述第二牺牲层5上的硬质掩膜层6,就会产生对所述第二牺牲层5的过刻蚀,从而对所述鳍结构4造成损伤。 [0067] Incidentally, in the embodiment of the present invention, the second trench is formed in the etching process. 7 requires two sorts of the hard mask layer 6 and the first sacrificial layer 2 etching materials, due to the proximity of the first sacrificial layer 2 and the second sacrificial material layer 5, if etched away the hard mask layer 5 on the second sacrificial layer 6, it will produce the first two over-etching of the sacrificial layer 5, thereby causing damage to the fin 4 structure. 因此,在所述第二沟槽7中的第二牺牲层5上应还保留一部分硬质掩膜层6,所述保留的硬质掩膜层6用于在后续在形成侧墙和栅结构的过程中保护所述鳍结构。 Thus, in the second trench 7 5 should also retain a portion of the second sacrificial layer 6 hard mask layer, said hard mask layer 6 is reserved for subsequent formation of the gate structure and sidewall the process of protecting the fin structure. 请参考图6,图6为图5沿yz平面的剖面结构示意图。 Please refer to FIG. 6, FIG. 6 is a schematic cross-sectional structure of FIG. 5 along the plane yz.

[0068] 接着,请参考图7,执行步骤S3,在所述第二沟槽7的侧壁上,形成侧墙8,用于在后续源/漏区扩散时提供一段过渡区域,防止后续的源/漏注入向沟道扩散太多。 [0068] Next, referring to FIG 7, performs step S3, on sidewalls of the second trench 7, spacers 8 are formed for providing a transition area at the subsequent source / drain diffusion regions, preventing the subsequent source / drain implant diffusion into the channel too. 在本发明实施例中,侧墙8的形成方法包括:在所述第二沟槽7中沉积侧墙材料层;在所述侧墙材料层上形成图形化的第二光刻胶,所述图形化的第二光刻胶层和后续形成的栅结构位置对应;以所述图形化的第二光刻胶层刻蚀所述侧墙材料层形成侧墙8。 In an embodiment of the present invention, a method of forming spacers 8 comprises: a second trench in said spacer material layer 7 is deposited; forming a patterned photoresist on said second spacer material layer, said patterning the second photoresist layer and the gate structure is formed corresponding to the position of the following; using the patterned second photoresist layer and etching the sidewall spacer material layer 8 is formed. 在本发明实施例中,所述侧墙材料层可以为多晶硅。 In an embodiment of the present invention, the spacer material layer may be a polysilicon.

[0069] 在本发明实施例中,所述侧墙8的厚度可以约为IOnm〜30nm。 [0069] In an embodiment of the present invention, the thickness of the sidewall may be about 8 IOnm~30nm.

[0070] 需要说明的是,在所述侧墙8的形成刻蚀过程中,有所述保留的硬质掩膜层6作为阻挡,鳍结构4表面不会产生损伤。 [0070] Incidentally, in forming the sidewall 8 in the etching process, a hard mask layer 6 as a barrier to the reservation, the surface of the fin structure 4 is not damaged. [0071] 接着,请参考图8,执行步骤S4。 [0071] Next, referring to FIG. 8, step S4. 刻蚀所述鳍结构两侧的第一牺牲层2,形成第三沟槽9,所述第三沟槽9暴露出所述鳍结构2,以便后续在所述第三沟槽9中形成栅结构。 The first sacrificial layer is etched on both sides of the fin structure 2, forming a third trench 9, the third trench to expose the fin structure 9 2, for subsequent formation of a gate in the third trench 9 structure. 在本发明实施例中,所述第三沟槽9中的衬底上仍保留一部分所述第一牺牲层2,用于隔离栅结构和衬底。 In an embodiment of the present invention, the third part of the first trenches remains sacrificial layer 9 on the substrate 2, for the isolation structure and the substrate. 请参考图9,图9为图8沿χ-y平面的剖面结构示意图。 Please refer to FIG. 9, FIG. 9 is a schematic diagram of χ-y plane 8 along the sectional structure.

[0072] 需要说明的是,如图9所示,所述鳍结构上的所述第二牺牲层5和形成第二沟槽后所述保留的硬质掩膜层6将在上述形成第三沟槽9的刻蚀过程中被消耗掉,所述第三沟槽9暴露出所述鳍结构2,以便后续在所述鳍结构上形成的栅结构。 [0072] Incidentally, in FIG. 9, the second fin structure on the sacrificial layer 5 and the hard mask layer after forming said second trench formed a third reservation in the above-6 the etching process in the trench 9 is consumed, the third trench gate structure 9 to expose the fin structure 2, in order to subsequently formed on the fin structure.

[0073] 接着,请参考图10,执行步骤S5。 [0073] Next, referring to FIG 10, step S5. 在所述第三沟槽9中形成栅结构10。 Forming a gate structure 10 in the third trench 9. 在本发明的实施例中,所述栅结构10的形成方法包括:在第三沟槽9中沉栅介质层(图未示);在所述栅介质层上形成栅极(图未示);对所述栅极和硬质掩膜层6进行化学机械研磨,停止于第一牺牲层2。 In an embodiment of the present invention, a method of forming the gate structure 10 comprising: a third trench in the gate dielectric layer 9 in the sink (not shown); forming a gate on the gate dielectric layer (not shown) ; the gate electrode 6 and the hard mask layer by chemical mechanical polishing, a first sacrificial layer 2 is stopped. 作为本发明的一个实施例,所述栅介质层可以包括高k介电材料,所述栅极可以为金属栅极。 As an embodiment of the present invention, the gate dielectric layer may comprise a high-k dielectric material, the gate may be a metal gate.

[0074] 需要说明的是,所述栅结构10是通过沉积工艺形成,相对现有技术不会损伤鳍结构4。 [0074] Incidentally, the gate structure 10 is formed by a deposition process, over the prior art does not damage the fin structure 4.

[0075] 最后,请参考图11,在本发明实施例中,鳍式场效应晶体管的形成方法,还包括:在形成所述栅结构10之后,去除所述第二牺牲层5上的硬质掩膜层6 ;在所述鳍结构10的两侧进行源/漏掺杂;去除所述第二牺牲层5。 [0075] Finally, referring to FIG 11, in the present invention, a method of forming a fin field effect transistor of the embodiment, further comprising: after forming the gate structure 10, removing the hard layer on the second sacrificial 5 6 the mask layer; source / drain doping in both sides of the fin structure 10; removing the second sacrificial layer 5.

[0076] 在上述实施例中,以衬底是体硅为例加以说明,所述衬底还可以是绝缘体上硅。 [0076] In the above embodiment, the substrate is a bulk silicon as an example to be described, the substrate may also be a silicon on insulator. 若衬底是绝缘体上硅,形成方法本发明实施例的鳍式场效应晶体管的方法类似,区别在于:请参考图12,先在绝缘体上硅10的顶层硅11表面形成第二牺牲层21,所述第二牺牲层21可以通过氧化绝缘体上硅10的顶层硅11形成;然后,请参考图13,刻蚀第二牺牲层21和绝缘体上硅10的顶层硅11,暴露出所述绝缘体上硅10的掩埋层12,形成鳍结构11'和第二牺牲层21' ;然后,请参考图14,形成第一牺牲层30,所述第一牺牲层30覆盖所述暴露出的掩埋层12和刻蚀后的第二牺牲层21'。 If the substrate is a silicon on insulator forming method of the present invention similar to the method of the FinFET embodiment, except that: Referring to FIG. 12, the first surface of the silicon-on-insulator 10 of the top silicon layer 11 forming a second sacrificial layer 21, the second sacrificial oxide layer 21 can be a silicon on insulator 10, the top silicon layer 11 is formed; then, referring to FIG 13, etching the second sacrificial layer 21 and top layer 10 of silicon silicon on insulator 11, exposing the insulator buried layer 12 of silicon 10, a fin structure 11 'and the second sacrificial layer 21'; then, referring to FIG 14, a first sacrificial layer 30 is formed, the first sacrificial layer 30 covers the exposed buried layer 12 the second sacrificial layer 21 'and the etched.

[0077] 接着,请参考图15,刻蚀所述第一牺牲层30以形成延伸方向与所述鳍结构11'的延伸方向垂直的第二沟槽31,当然,在刻蚀所述第一牺牲层30过程中,所述第一牺牲层30表面还可以覆盖有掩膜层(未示出),比如可以为光刻胶或者氮化硅,所述第二沟槽31的底面没有暴露出所述第二牺牲层21',即所述第二沟槽31的底面高于所述第二牺牲层21'的表面。 [0077] Next, referring to FIG 15, the first sacrificial layer 30 is etched to form a fin structure extending in the direction 11 'perpendicular to the extending direction of the second trench 31, of course, the first etching process sacrificial layer 30, the surface of the first sacrificial layer 30 may also be covered with a mask layer (not shown), such as photoresist or silicon nitride may be a bottom surface of the second trench 31 is exposed is not the second sacrificial layer 21 ', i.e., the bottom of the second trench 31 is higher than the second sacrificial layer 21' of the surface.

[0078] 接着在所述第二沟槽31侧壁形成侧墙31',具体形成方法与前述实施例的相类似,不加详述。 [0078] The spacer 31 is then formed on the sidewalls of the second trench 31 'is formed similar to the specific embodiment of the method of the preceding embodiment, without detailed description.

[0079] 接着,请参考图16,在侧壁上形成有侧墙材料的第二沟槽31的基础上继续刻蚀第一牺牲层30,形成第三沟槽32,所述第三沟槽32底部暴露出所述绝缘体上硅的掩埋层12,当然也可以高出掩埋层12,所述第三沟槽32用于形成栅结构,具体形成栅结构的工艺与前述实施例相类似,在此不加详述。 [0079] Next, referring to FIG. 16, a first sacrificial layer is etched to continue forming the basis of the second trench 30 has a sidewall 31 of the material, a third trench 32 is formed on the side wall, the third trench 32 exposing the bottom of the buried insulator layer of silicon 12, buried layer 12 may of course be higher, the third trench 32 for forming the gate structure, particularly the process of forming the gate structure according to a similar embodiment, in this does not add detail.

[0080] 综上所述,本发明的实施例具有以下优点: [0080] In summary, embodiments of the present invention has the following advantages:

[0081] 通过在所述鳍结构周围包围第一牺牲层、通过形成在第一牺牲层中的第二沟槽的侧壁上形成侧墙、以及通过形成在第一牺牲层中的第三沟槽内形成栅结构,这样在形成栅结构和形成栅结构的侧墙过程中,所述鳍结构具有第一牺牲层和/或第二牺牲层的保护,没有受到形成栅结构以及形成栅结构的侧墙的工艺的损伤,因此,鳍结构晶体质量较高,不会象现有技术中的受损伤的鳍结构对形成的鳍式场效应晶体管的性能产生影响。 [0081] By around the fin structure surrounds the first sacrificial layer, is formed by spacers on the sidewalls of the second trench is formed in the first sacrificial layer, and by a third groove formed in the first sacrificial layer groove formed gate structure, the gate structure is formed so that the process of sidewall gate structure formed in the first fin structure having a protective sacrificial layer and / or the second sacrificial layer is not formed by the gate structure and forming a gate structure damage process spacers, and therefore, high quality crystal structure of the fin, is not damaged as in the prior art fin structure affect the performance of FinFETs formed.

[0082] 另外,在本发明的实施例中,在所述侧墙的形成过程中,有硬质掩膜层作为阻挡,因此,更不会对鳍结构造成损伤,从而也不会影响后续形成的鳍式场效应晶体管的性能。 [0082] Further, in the embodiment of the present invention, during formation of the sidewall, a hard mask as a barrier layer, and therefore, will not cause damage to the fin structure, thereby not affecting the subsequent formation the performance of the FinFET.

[0083] 以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制。 [0083] The above, only the preferred embodiments of the invention only, and not limitation of the present invention in any form. 任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。 Any skilled in the art, without departing from the scope of the technical solution of the present invention, can take advantage of the above-described methods and technical content disclosed that many possible variations and modifications of the technical solution of the present invention, as equivalent variations or modifications equivalent embodiments example. 因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。 Thus, all without departing from the technical solutions of the present invention, any simple modification based on the technical essence of the present invention made of the above Example, equivalents, modifications and variations, provided they fall within the scope of protection of the present invention.

Claims (18)

1.一种鳍式场效应晶体管的形成方法,其特征在于,包括: 提供衬底,所述衬底上形成有鳍结构和位于鳍结构上的第二牺牲层、以及包围所述鳍结构和第二牺牲层的第一牺牲层; 形成第二沟槽,所述第二沟槽延伸方向与所述鳍结构的延伸方向垂直,所述第二沟槽底部高于所述第二牺牲层的表面; 在所述第二沟槽的侧壁上形成侧墙; 沿形成有侧墙的第二沟槽刻蚀所述第一牺牲层,形成第三沟槽,所述第三沟槽暴露出所述鳍结构;以及在所述第三沟槽内形成栅结构,所述栅结构横跨所述鳍结构。 1. A method of forming a fin field-effect transistor, comprising: providing a substrate, and is formed with a fin structure in the second sacrificial layer on the fin structure on the substrate, and surrounds the fin structure and the first sacrificial layer of the second sacrificial layer; forming a second trench, said second trench extending direction of the extending direction of the vertical fin structure, a second bottom of the second trench is higher than the sacrificial layer surface; formed on sidewalls of the second trench side walls; a second trench etching the first sacrificial layer is formed along the sidewall, forming a third trench, the third trench to expose the fin structure; and a gate structure formed in the third trench, the gate structure across said fin structure.
2.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,若所述衬底是绝缘体上硅,所述鳍结构和第一牺牲层形成方法包括: 形成第二牺牲层; 刻蚀第二牺牲层和绝缘体上硅的顶层硅,暴露出绝缘体上硅的掩埋层,形成鳍结构;以及形成第一牺牲层,所述第一牺牲层覆盖所述暴露出的掩埋层和刻蚀后的第二牺牲层。 2. The method of forming a fin field effect transistor according to claim 1, wherein, when said substrate is a silicon on insulator, said fin structure and the method of the first sacrificial layer comprises: forming a second sacrificial layer ; etching the second sacrificial layer and the top silicon layer silicon-on-insulator, exposing the buried layer of silicon-on-insulator, forming a fin structure; and forming a first sacrificial layer, the buried layer of the first sacrificial layer covering the exposed and the second sacrificial layer after etching.
3.如权利要求2所述的鳍式场效应晶体管的形成方法,其特征在于,所述第二沟槽的形成方法包括:刻蚀所述第一牺牲层,形成所述第二沟槽。 3. The method of forming a fin field effect transistor according to claim 2, characterized in that the method of forming the second trench comprises: etching the first sacrificial layer, forming the second trench.
4.如权利要求3所述的鳍式场效应晶体管的形成方法,其特征在于,所述第三沟槽还暴露出绝缘体上硅的掩埋层。 4. The method of forming a fin field effect transistor according to claim 3, characterized in that, the third trench to expose a buried layer of silicon further on-insulator.
5.如权利要求2所述的鳍式场效应晶体管的形成方法,其特征在于,所述第二牺牲层通过氧化绝缘体上硅的顶层硅形成。 5. The method of forming a fin field effect transistor according to claim 2, wherein said second sacrificial layer of silicon oxide is formed through the top layer of silicon on insulator.
6.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,若所述衬底是体硅,所述鳍结构和第一牺牲层形成方法包括: 在所述衬底上形成第一牺牲层; 在所述第一牺牲层中形成第一沟槽,所述第一沟槽暴露出所述衬底; 在所述第一沟槽内通过外延生长工艺形成鳍结构,所述鳍结构的上表面低于第一牺牲层上表面;以及在所述第一沟槽内的所述鳍结构的上表面形成第二牺牲层,所述第二牺牲层的上表面低于所述第一牺牲层的上表面。 6. A method for forming a finFET 1 claim, wherein, if the substrate is a silicon body, said fin structure and the first sacrificial layer forming method comprising: said substrate forming a first sacrificial layer; forming a first trench in the first sacrificial layer, exposing the substrate, the first trench; forming a fin structure by an epitaxial growth process in the first trench, the the upper surface of said fin structure is lower than the upper surface of the first sacrificial layer; and an upper surface of the fin structure in the first trench to form a second sacrificial layer, the upper surface of the second sacrificial layer below the said upper surface of the first sacrificial layer.
7.如权利要求6所述的鳍式场效应晶体管的形成方法,其特征在于,所述第三沟槽未暴露出所述衬底。 7. The method of forming a fin field effect transistor according to claim 6, wherein the third trench does not expose the substrate.
8.如权利要求6所述的鳍式场效应晶体管的形成方法,其特征在于,所述外延生长工艺的温度为600°C〜900°C。 8. A method of forming a fin field effect transistor according to claim 6, wherein said epitaxial growth process temperature of 600 ° C~900 ° C.
9.如权利要求6所述的鳍式场效应晶体管的形成方法,其特征在于,所述第二沟槽的形成方法包括: 在所述第一牺牲层和第二牺牲层上形成硬质掩膜层,所述硬质掩膜层与所述第二牺牲层材质不同; 将所述硬质掩膜层磨平;以及刻蚀磨平的硬质掩膜层和所述第一牺牲层,形成第二沟槽。 The method of forming a fin field effect transistor of claim 6 to claim 9, characterized in that the method of forming the second trench comprises: forming a hard mask on the first sacrificial layer and the second sacrificial layer film, the hard mask layer and the second sacrificial layer materials are different; the polished hard mask layer; and etching the polished hard mask layer and the first sacrificial layer, forming a second trench.
10.如权利要求9所述的鳍式场效应晶体管的形成方法,其特征在于,所述硬质掩膜层包含氮化硅。 10. The method of forming a fin field effect transistor according to claim 9, wherein said hard mask layer comprises silicon nitride.
11.如权利要求6所述的鳍式场效应晶体管的形成方法,其特征在于,所述第二牺牲层是通过氧化所述鳍结构的上表面形成。 The method of forming a fin field effect transistor 11. The claim 6, wherein the second sacrificial layer is formed by oxidizing the surface of the fin structure.
12.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,所述鳍结构的高度为20nm 〜lOOnm。 12. The method of forming a fin field effect transistor according to claim 1, wherein said fin structure height of 20nm ~lOOnm.
13.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,所述侧墙的厚度为IOnm 〜30nm。 13. The method of forming a fin field effect transistor according to claim 1, wherein said spacer has a thickness of IOnm ~30nm.
14.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,所述侧墙材料层包括多晶硅。 14. The method of forming a fin field effect transistor according to claim 1, wherein said spacer material layer comprises polysilicon.
15.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,所述栅结构的形成方法包括:在第三沟槽中沉积栅介质层;在栅介质层上形成栅极材料层;对所述栅极材料层和硬质掩膜层进行化学机械研磨,停止于第一牺牲层。 15. The method of forming a fin field effect transistor according to claim 1, characterized in that the method of forming the gate structure comprises: depositing a gate dielectric layer in the third trench; forming a gate on the gate dielectric layer material layer; the gate material layer and the hard mask layer by chemical mechanical polishing, sacrificial layer to the first stop.
16.如权利要求15所述的鳍式场效应晶体管的形成方法,其特征在于,所述栅介质层包括高k介电材料。 A method of forming a fin field effect transistor 16. The claim 15, wherein the gate dielectric layer comprises a high k dielectric material.
17.如权利要求15所述的鳍式场效应晶体管的形成方法,其特征在于,所述栅极的材料为金属。 The method of forming a fin field effect transistor 17. The of claim 15, wherein said gate electrode material is a metal.
18.如权利要求1所述的鳍式场效应晶体管的形成方法,其特征在于,所述第一牺牲层包括氧化硅。 18. The method of forming a fin field effect transistor according to claim 1, wherein said first sacrificial layer comprises silicon oxide.
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