CN103187260A - Formation method of fin field effect transistor - Google Patents
Formation method of fin field effect transistor Download PDFInfo
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- CN103187260A CN103187260A CN2011104597183A CN201110459718A CN103187260A CN 103187260 A CN103187260 A CN 103187260A CN 2011104597183 A CN2011104597183 A CN 2011104597183A CN 201110459718 A CN201110459718 A CN 201110459718A CN 103187260 A CN103187260 A CN 103187260A
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Abstract
A formation method of a fin field effect transistor comprises the following steps: providing a substrate, forming a fin structure, a second sacrificial layer located on the fin structure and a first sacrificial layer surrounding the fin structure and the second sacrificial layer; forming a second groove, wherein the extending direction of the second groove is vertical to the extending direction of the fin structure, and the bottom of the second groove is higher than the surface of the second sacrificial layer; forming a sidewall on a side wall of the second groove; sculpturing the first sacrificial layer along the second groove with the sidewall, forming a third groove, wherein the third groove is exposed out from the fin structure; and forming a gate structure in the third groove, wherein the gate structure stretches across the fin structure. The method can prevent the fin structure from being damaged and prevent sidewall residuum from forming on the fin structure, so that the formation of the fin field effect transistor with high performance is ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of fin formula field effect transistor.
Background technology
As everyone knows, transistor is the key element in the integrated circuit.In order to improve transistorized operating rate, need to improve transistorized drive current.Because transistorized drive current is proportional to transistorized grid width, therefore to improve drive current again, just need to increase grid width.But, increase grid width and conflict mutually with the downsizing demand of the size of semiconductor own, fin formula field effect transistor (FinFET) so develop.
In the prior art, the formation method of fin formula field effect transistor (FinFET) comprising: substrate is provided; At the method formation fin structure of described substrate by etching; Method by etching forms the grid structure at described substrate and fin structure; Form side wall in described grid structure both sides.Be the formation method that the Chinese patent application of CN102074506A discloses a kind of fin formula field effect transistor as publication No..
In said method, when forming the grid structure, etching technics can damage the sidewall of described fin structure.In addition, in the forming process of described side wall, the sidewall of fin structure also can sustain damage and can adhere to one deck side wall residue.The damage of above-mentioned fin structure and the side wall residue on the fin structure all will have influence on follow-up formed device performance.
Therefore, need to propose a kind of formation method of new fin formula field effect transistor, avoid fin structure is produced damage and adheres to the side wall residue at fin structure, and then avoid described damage and side wall residue to cause adverse effect for follow-up formed device.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of fin formula field effect transistor, avoids fin structure is caused damage and forms the side wall residue at fin structure, and then guarantees the formation of high performance fin formula field effect transistor.
For addressing the above problem, the embodiment of the invention provides a kind of formation method of fin formula field effect transistor, comprising:
Substrate is provided, is formed with fin structure on the described substrate and is positioned at second sacrifice layer on the fin structure and surrounds described fin structure and first sacrifice layer of second sacrifice layer;
Form second groove, the described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
Sidewall at described second groove forms side wall;
Described first sacrifice layer of second etching groove along being formed with side wall forms the 3rd groove, and described the 3rd groove exposes described fin structure; And
Form the grid structure in described the 3rd groove, described grid structure is across described fin structure.
Alternatively, if described substrate is silicon-on-insulator, described fin structure and the first sacrifice layer formation method comprise:
Form second sacrifice layer;
The top layer silicon of etching second sacrifice layer and silicon-on-insulator exposes the buried layer of silicon-on-insulator, forms fin structure; And
Form first sacrifice layer, described first sacrifice layer covers second sacrifice layer after the described buried layer that exposes and the etching.
Alternatively, the formation method of described second groove comprises: described first sacrifice layer of etching forms described second groove.
Alternatively, described the 3rd groove also exposes the buried layer of silicon-on-insulator.
Alternatively, described second sacrifice layer forms by the top layer silicon of silicon on the oxide isolated body.
Alternatively, if described substrate is body silicon, described fin structure and the first sacrifice layer formation method comprise:
Form first sacrifice layer at described substrate;
Form first groove in described first sacrifice layer, described first groove exposes described substrate;
Form fin structure by epitaxial growth technology in described first groove, the upper surface of described fin structure is lower than the first sacrifice layer upper surface; And
The upper surface of the described fin structure in described first groove forms second sacrifice layer, and the upper surface of described second sacrifice layer is lower than the upper surface of described first sacrifice layer.
Alternatively, described the 3rd groove does not expose described substrate.
Alternatively, the temperature of described epitaxial growth technology is 600 ℃～900 ℃.
Alternatively, the formation method of described second groove comprises:
Form hard mask layer at described first sacrifice layer and second sacrifice layer, described hard mask layer is different with the described second sacrifice layer material;
Described hard mask layer is polished; And
The hard mask layer that etching polishes and described first sacrifice layer form second groove.
Alternatively, described hard mask layer comprises silicon nitride.
Alternatively, described second sacrifice layer is the upper surface formation by the described fin structure of oxidation.
Alternatively, the height of described fin structure is 20nm～100nm.
Alternatively, the thickness of described side wall is 10nm～30nm.
Alternatively, described spacer material layer comprises polysilicon.
Alternatively, the formation method of described grid structure comprises: deposit gate dielectric layer in the 3rd groove; Form gate material layers at gate dielectric layer; Described gate material layers and hard mask layer are carried out cmp, stop at first sacrifice layer.
Alternatively, described gate dielectric layer comprises high-k dielectric material.
Alternatively, the material of described grid is metal.
Alternatively, described first sacrifice layer comprises silica.
Compared with prior art, embodiments of the invention have the following advantages:
By around described fin structure, surrounding first sacrifice layer; by forming side wall on the sidewall that is formed on second groove in first sacrifice layer; and by being formed on formation grid structure in the 3rd groove in first sacrifice layer; forming the grid structure and forming in the side wall process of grid structure like this; described fin structure has the protection of first sacrifice layer and/or second sacrifice layer; the damage of technology that is not subjected to forming the grid structure and forms the side wall of grid structure; therefore; the fin structure crystal mass is higher, and the fin structure that can not resemble damaged of the prior art exerts an influence to the performance of the fin formula field effect transistor that forms.
In addition, in an embodiment of the present invention, in the forming process of described side wall, hard mask layer is arranged as stopping, therefore, more can not cause damage to fin structure, thereby also can not influence the performance of the fin formula field effect transistor of follow-up formation.
Description of drawings
Fig. 1 is the schematic flow sheet of formation method of the fin formula field effect transistor of one embodiment of the invention;
Fig. 2～5, Fig. 7～8 and Figure 10～16th, the middle 3-D solid structure schematic diagram of the formation method of the fin formula field effect transistor of one embodiment of the invention;
Fig. 6 and 9 is the middle cross-sectional view of the fin formula field effect transistor of one embodiment of the invention.
Embodiment
In the prior art, the formation method of fin formula field effect transistor can cause damage to fin structure, and forms the side wall residue at fin structure, thereby causes the performance of fin formula field effect transistor to descend.At the problems referred to above, embodiments of the invention provide a kind of formation method of fin formula field effect transistor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
The embodiment of the invention provides a kind of formation method of fin formula field effect transistor, please refer to Fig. 1, and described method comprises:
Step S1 provides substrate, is formed with fin structure on the described substrate and is positioned at second sacrifice layer on the fin structure and surrounds described fin structure and first sacrifice layer of second sacrifice layer;
Step S2 forms second groove, and the described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
Step S3 forms side wall at the sidewall of described second groove;
Step S4 along described described first sacrifice layer of second etching groove that is formed with side wall, forms the 3rd groove, and described the 3rd groove exposes described fin structure; And
Step S5 forms the grid structure in described the 3rd groove, described grid structure is across described fin structure.
Following mask body is in conjunction with Fig. 2～Figure 16, the technical scheme that the embodiment of the invention is provided is described in detail, Fig. 2～Fig. 5, Fig. 7～8 and Figure 10～16th, the middle 3-D solid structure schematic diagram of the formation method of the fin formula field effect transistor of one embodiment of the invention, Fig. 6 and Fig. 9 are the middle cross-sectional view of the fin formula field effect transistor of one embodiment of the invention.
At first, please refer to Fig. 2, execution in step S1 provides substrate 1, is formed with fin structure 4 on the described substrate 1 and is positioned at second sacrifice layer 5 on the fin structure 4 and surrounds described fin structure 4 and first sacrifice layer 2 of second sacrifice layer 5.In embodiments of the present invention, described substrate 1 can be body silicon, can certainly be silicon-on-insulator, is that example is illustrated with the substrate for body silicon hereinafter.Described first sacrifice layer 2 can comprise silica.
Described fin structure and first sacrifice layer, 2 formation methods comprise: please refer to Fig. 2, form first sacrifice layer 2 at described substrate 1.
Then, please refer to Fig. 3, described first sacrifice layer 2 of etching forms first groove 3 in described first sacrifice layer 2, and described first groove 3 exposes described substrate 1.
Then, please refer to Fig. 4, form fin structure 4 by epitaxial growth technology in described first groove 3, the upper surface of described fin structure 4 is lower than the upper surface of first sacrifice layer 2.
Then, please continue with reference to figure 4, the upper surface of the described fin structure 4 in described first groove 3 forms second sacrifice layer 5, and the upper surface of described second sacrifice layer 5 is lower than the upper surface of described first sacrifice layer 2.
As one embodiment of the present of invention, the height of described fin structure can be about 20nm～100nm, and the temperature of described epitaxial growth technology can be about 600 ℃～900 ℃.
Need to prove, in embodiments of the present invention, described fin structure 4 forms by silicon epitaxy, relative prior art, the damage that described fin structure is subjected to when not being subjected to forming fin structure self as etching of the prior art, the fin structure crystal mass that extension forms is relatively good, and also can not sustain damage in follow-up formation grid structural manufacturing process.
In addition, described second sacrifice layer 5 will be as the hard mask layer of follow-up formation and the resilient coating between the fin structure 4, and prevent from producing over etching in the process of follow-up formation second groove, thereby avoid described over etching that described fin structure 2 is caused damage,
In embodiments of the present invention, described second sacrifice layer 5 forms by the upper surface of the described fin structure 4 of oxidation.
Then, please refer to Fig. 4～5, execution in step S2 forms second groove 7, and described second groove, 7 bearing of trends are vertical with the bearing of trend of described fin structure 4, and described second groove 7 bottoms are higher than the surface of described second sacrifice layer 5.In embodiments of the present invention, the formation method of described second groove 7 comprises: please refer to Fig. 4, form hard mask layer 6 at described first sacrifice layer 2 and second sacrifice layer 5, described hard mask layer 6 is different with described second sacrifice layer, 5 materials; Then, described hard mask layer 6 is polished; Then, please refer to Fig. 5, hard mask layer 6 and described first sacrifice layer 2 along the direction etching vertical with the bearing of trend of fin structure 4 polishes form described second groove 7.
In embodiments of the present invention, described hard mask layer 6 can comprise silicon nitride, by cmp described hard mask layer 6 is polished, the described hard mask layer that polishes 6 of etching and described first sacrifice layer 2, the method that forms second groove 7 comprises: form the patterned first photoresist (not shown), the side wall position correspondence of described patterned first photoresist layer and follow-up formation at hard mask layer 6; Be the described hard mask layer 6 of mask etching and first sacrifice layer 2 with described patterned photoresist, form described second groove 7.
Need to prove, in embodiments of the present invention, in the etching process that forms described second groove 7, need carry out etching to described hard mask layer 6 and 2 two kinds of materials of described first sacrifice layer, because described first sacrifice layer 2 and second sacrifice layer, 5 materials approach, if etch away the hard mask layer 6 on described second sacrifice layer 5 fully, will produce the over etching to described second sacrifice layer 5, thereby described fin structure 4 is caused damage.Therefore, should also keep a part of hard mask layer 6 on second sacrifice layer 5 in described second groove 7, the hard mask layer 6 of described reservation is used for forming the described fin structure of process protection of side wall and grid structure follow-up.Please refer to Fig. 6, Fig. 6 is that Fig. 5 is along the cross-sectional view on y-z plane.
Then, please refer to Fig. 7, execution in step S3 on the sidewall of described second groove 7, forms side wall 8, be used in follow-up source/drain region provides one section transitional region when spreading, prevents that follow-up source/leakage injection is too many to the raceway groove diffusion.In embodiments of the present invention, the formation method of side wall 8 comprises: deposition spacer material layer in described second groove 7; Form patterned second photoresist, the grid locations of structures correspondence of described patterned second photoresist layer and follow-up formation at described spacer material layer; Form side wall 8 with the described spacer material layer of the described patterned second photoresist layer etching.In embodiments of the present invention, described spacer material layer can be polysilicon.
In embodiments of the present invention, the thickness of described side wall 8 can be about 10nm～30nm.
Need to prove in the formation etching process of described side wall 8, the hard mask layer 6 of described reservation is arranged as stopping that fin structure 4 surfaces can not produce damage.
Then, please refer to Fig. 8, execution in step S4.First sacrifice layer 2 of the described fin structure of etching both sides forms the 3rd groove 9, and described the 3rd groove 9 exposes described fin structure 2, so that the follow-up grid structure that forms in described the 3rd groove 9.In embodiments of the present invention, still keep described first sacrifice layer 2 of a part on the substrate in described the 3rd groove 9, be used for isolated gate structure and substrate.Please refer to Fig. 9, Fig. 9 is that Fig. 8 is along the cross-sectional view on x-y plane.
Need to prove, as shown in Figure 9, the hard mask layer 6 of described reservation will be consumed in the etching process of above-mentioned formation the 3rd groove 9 behind described second sacrifice layer 5 on the described fin structure and formation second groove, described the 3rd groove 9 exposes described fin structure 2, so that the follow-up grid structure that forms at described fin structure.
Then, please refer to Figure 10, execution in step S5.In described the 3rd groove 9, form grid structure 10.In an embodiment of the present invention, the formation method of described grid structure 10 comprises: heavy gate dielectric layer (not shown) in the 3rd groove 9; Form the grid (not shown) at described gate dielectric layer; Described grid and hard mask layer 6 are carried out cmp, stop at first sacrifice layer 2.As one embodiment of the present of invention, described gate dielectric layer can comprise high-k dielectric material, and described grid can be metal gates.
Need to prove that described grid structure 10 is to form by depositing operation, prior art can not damaged fin structure 4 relatively.
At last, please refer to Figure 11, in embodiments of the present invention, the formation method of fin formula field effect transistor also comprises: after forming described grid structure 10, remove the hard mask layer 6 on described second sacrifice layer 5; Carry out source/leakage mixes in the both sides of described fin structure 10; Remove described second sacrifice layer 5.
In the above-described embodiments, be that body silicon is that example is illustrated with substrate, described substrate can also be silicon-on-insulator.If substrate is silicon-on-insulator, the method of the fin formula field effect transistor of the formation method embodiment of the invention is similar, difference is: please refer to Figure 12, form second sacrifice layer 21 on top layer silicon 11 surfaces of silicon-on-insulator 10 earlier, described second sacrifice layer 21 can form by the top layer silicon 11 of silicon 10 on the oxide isolated body; Then, please refer to Figure 13, the top layer silicon 11 of etching second sacrifice layer 21 and silicon-on-insulator 10 exposes the buried layer 12 of described silicon-on-insulator 10, forms fin structure 11 ' and second sacrifice layer 21 '; Then, please refer to Figure 14, form first sacrifice layer 30, described first sacrifice layer 30 covers second sacrifice layer 21 ' after the described buried layer that exposes 12 and the etching.
Then, please refer to Figure 15, described first sacrifice layer 30 of etching is to form bearing of trend second groove 31 vertical with the bearing of trend of described fin structure 11 ', certainly, in described first sacrifice layer of etching 30 processes, described first sacrifice layer 30 surfaces can also be coated with the mask layer (not shown), such as being photoresist or silicon nitride, the bottom surface of described second groove 31 does not expose described second sacrifice layer 21 ', and namely the bottom surface of described second groove 31 is higher than the surface of described second sacrifice layer 21 '.
Then form side wall 31 ' at described second groove, 31 sidewalls, specifically form the similar of method and previous embodiment, do not add detailed description.
Then, please refer to Figure 16, etching first sacrifice layer 30 is continued on the basis that is formed with second groove 31 of spacer material at sidewall, form the 3rd groove 32, described the 3rd groove 32 bottom-exposed go out the buried layer 12 of described silicon-on-insulator, can certainly exceed buried layer 12, and described the 3rd groove 32 is used to form the grid structure, technology and the previous embodiment of concrete formation grid structure are similar, do not add detailed description at this.
In sum, embodiments of the invention have the following advantages:
By around described fin structure, surrounding first sacrifice layer; by forming side wall on the sidewall that is formed on second groove in first sacrifice layer; and by being formed on formation grid structure in the 3rd groove in first sacrifice layer; forming the grid structure and forming in the side wall process of grid structure like this; described fin structure has the protection of first sacrifice layer and/or second sacrifice layer; the damage of technology that is not subjected to forming the grid structure and forms the side wall of grid structure; therefore; the fin structure crystal mass is higher, and the fin structure that can not resemble damaged of the prior art exerts an influence to the performance of the fin formula field effect transistor that forms.
In addition, in an embodiment of the present invention, in the forming process of described side wall, hard mask layer is arranged as stopping, therefore, more can not cause damage to fin structure, thereby also can not influence the performance of the fin formula field effect transistor of follow-up formation.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (18)
1. the formation method of a fin formula field effect transistor is characterized in that, comprising:
Substrate is provided, is formed with fin structure on the described substrate and is positioned at second sacrifice layer on the fin structure and surrounds described fin structure and first sacrifice layer of second sacrifice layer;
Form second groove, the described second groove bearing of trend is vertical with the bearing of trend of described fin structure, and described second channel bottom is higher than the surface of described second sacrifice layer;
Sidewall at described second groove forms side wall;
Described first sacrifice layer of second etching groove along being formed with side wall forms the 3rd groove, and described the 3rd groove exposes described fin structure; And
Form the grid structure in described the 3rd groove, described grid structure is across described fin structure.
2. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, if described substrate is silicon-on-insulator, described fin structure and the first sacrifice layer formation method comprise:
Form second sacrifice layer;
The top layer silicon of etching second sacrifice layer and silicon-on-insulator exposes the buried layer of silicon-on-insulator, forms fin structure; And
Form first sacrifice layer, described first sacrifice layer covers second sacrifice layer after the described buried layer that exposes and the etching.
3. the formation method of fin formula field effect transistor as claimed in claim 2 is characterized in that, the formation method of described second groove comprises: described first sacrifice layer of etching forms described second groove.
4. the formation method of fin formula field effect transistor as claimed in claim 3 is characterized in that, described the 3rd groove also exposes the buried layer of silicon-on-insulator.
5. the formation method of fin formula field effect transistor as claimed in claim 2 is characterized in that, described second sacrifice layer forms by the top layer silicon of silicon on the oxide isolated body.
6. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, if described substrate is body silicon, described fin structure and the first sacrifice layer formation method comprise:
Form first sacrifice layer at described substrate;
Form first groove in described first sacrifice layer, described first groove exposes described substrate;
Form fin structure by epitaxial growth technology in described first groove, the upper surface of described fin structure is lower than the first sacrifice layer upper surface; And
The upper surface of the described fin structure in described first groove forms second sacrifice layer, and the upper surface of described second sacrifice layer is lower than the upper surface of described first sacrifice layer.
7. the formation method of fin formula field effect transistor as claimed in claim 6 is characterized in that, described the 3rd groove does not expose described substrate.
8. the formation method of fin formula field effect transistor as claimed in claim 6 is characterized in that, the temperature of described epitaxial growth technology is 600 ℃～900 ℃.
9. the formation method of fin formula field effect transistor as claimed in claim 6 is characterized in that, the formation method of described second groove comprises:
Form hard mask layer at described first sacrifice layer and second sacrifice layer, described hard mask layer is different with the described second sacrifice layer material;
Described hard mask layer is polished; And
The hard mask layer that etching polishes and described first sacrifice layer form second groove.
10. the formation method of fin formula field effect transistor as claimed in claim 9 is characterized in that, described hard mask layer comprises silicon nitride.
11. the formation method of fin formula field effect transistor as claimed in claim 6 is characterized in that, described second sacrifice layer is the upper surface formation by the described fin structure of oxidation.
12. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the height of described fin structure is 20nm～100nm.
13. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the thickness of described side wall is 10nm～30nm.
14. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, described spacer material layer comprises polysilicon.
15. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, the formation method of described grid structure comprises: deposit gate dielectric layer in the 3rd groove; Form gate material layers at gate dielectric layer; Described gate material layers and hard mask layer are carried out cmp, stop at first sacrifice layer.
16. the formation method of fin formula field effect transistor as claimed in claim 15 is characterized in that described gate dielectric layer comprises high-k dielectric material.
17. the formation method of fin formula field effect transistor as claimed in claim 15 is characterized in that, the material of described grid is metal.
18. the formation method of fin formula field effect transistor as claimed in claim 1 is characterized in that, described first sacrifice layer comprises silica.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979202A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN107887327A (en) * | 2016-09-29 | 2018-04-06 | 格芯公司 | Self-aligning grid length is controlled in vertical transistor replacement gate flow |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050095794A1 (en) * | 2003-10-22 | 2005-05-05 | Park Je-Min | Method of fabricating recess channel array transistor |
| US20050199948A1 (en) * | 2004-03-09 | 2005-09-15 | Lee Jong-Wook | Fin field effect transistors with epitaxial extension layers and methods of forming the same |
| US20050199920A1 (en) * | 2004-03-11 | 2005-09-15 | Deok-Hyung Lee | Fin field effect transistors with low resistance contact structures and methods of manufacturing the same |
| KR20060027440A (en) * | 2004-09-22 | 2006-03-28 | 삼성전자주식회사 | Capacitively coupled junction finfet(fin field effect transistor), method of manufacturing for the same and cmos(complementary metal oxide semiconductor) transistor employing the same |
| JP2006339514A (en) * | 2005-06-03 | 2006-12-14 | Toshiba Corp | Semiconductor device and method of manufacturing same |
| US20080293215A1 (en) * | 2005-08-30 | 2008-11-27 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions |
| KR20090066930A (en) * | 2007-12-20 | 2009-06-24 | 주식회사 하이닉스반도체 | Method for forming saddle fin type transistor |
| US20090283829A1 (en) * | 2008-05-13 | 2009-11-19 | International Business Machines Corporation | Finfet with a v-shaped channel |
| TW201003796A (en) * | 2008-07-02 | 2010-01-16 | Promos Technologies Inc | Method for preparing FinFET device |
| CN102148159A (en) * | 2009-12-21 | 2011-08-10 | 万国半导体股份有限公司 | Method of forming a self-aligned charge balanced power DMOS |
-
2011
- 2011-12-31 CN CN201110459718.3A patent/CN103187260B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050095794A1 (en) * | 2003-10-22 | 2005-05-05 | Park Je-Min | Method of fabricating recess channel array transistor |
| US20050199948A1 (en) * | 2004-03-09 | 2005-09-15 | Lee Jong-Wook | Fin field effect transistors with epitaxial extension layers and methods of forming the same |
| US20050199920A1 (en) * | 2004-03-11 | 2005-09-15 | Deok-Hyung Lee | Fin field effect transistors with low resistance contact structures and methods of manufacturing the same |
| KR20060027440A (en) * | 2004-09-22 | 2006-03-28 | 삼성전자주식회사 | Capacitively coupled junction finfet(fin field effect transistor), method of manufacturing for the same and cmos(complementary metal oxide semiconductor) transistor employing the same |
| JP2006339514A (en) * | 2005-06-03 | 2006-12-14 | Toshiba Corp | Semiconductor device and method of manufacturing same |
| US20080293215A1 (en) * | 2005-08-30 | 2008-11-27 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions |
| KR20090066930A (en) * | 2007-12-20 | 2009-06-24 | 주식회사 하이닉스반도체 | Method for forming saddle fin type transistor |
| US20090283829A1 (en) * | 2008-05-13 | 2009-11-19 | International Business Machines Corporation | Finfet with a v-shaped channel |
| TW201003796A (en) * | 2008-07-02 | 2010-01-16 | Promos Technologies Inc | Method for preparing FinFET device |
| CN102148159A (en) * | 2009-12-21 | 2011-08-10 | 万国半导体股份有限公司 | Method of forming a self-aligned charge balanced power DMOS |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979202A (en) * | 2014-04-04 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN104979202B (en) * | 2014-04-04 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN107887327A (en) * | 2016-09-29 | 2018-04-06 | 格芯公司 | Self-aligning grid length is controlled in vertical transistor replacement gate flow |
| CN107887327B (en) * | 2016-09-29 | 2021-11-05 | 格芯(美国)集成电路科技有限公司 | Controlling self-aligned gate length in vertical transistor replacement gate flow |
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| Publication number | Publication date |
|---|---|
| CN103187260B (en) | 2016-03-16 |
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