CN104979202B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN104979202B CN104979202B CN201410135884.1A CN201410135884A CN104979202B CN 104979202 B CN104979202 B CN 104979202B CN 201410135884 A CN201410135884 A CN 201410135884A CN 104979202 B CN104979202 B CN 104979202B
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Abstract
The present invention provides a kind of forming method of transistor, comprising: provides substrate；Source region, drain region are formed in the substrate, and the substrate between the source region and drain region is as channel region；The sacrificial layer for covering the source region, drain region and channel region is formed over the substrate；The sacrificial layer is patterned, to form the opening for exposing the channel region in sacrificial layer；Metal gates are formed in said opening；Remove remaining sacrificial layer.The forming method of transistor of the present invention eliminates the step of forming pseudo- grid structure, an etching technics is only carried out during forming opening, reduce influence of the etching technics to opening shape looks, so as to and then improve the performance of the transistor with the metal gates so that the metal gates being formed in the opening have preferable pattern.It is formed before opening in the sacrificial layer, the sacrificial layer is handled without chemical mechanical grinding, and the pollutant in sacrificial layer and opening is less, is beneficial to the performance of transistor.
Description
Technical field
The present invention relates to semiconductor fields, and in particular to a kind of forming method of transistor.
Background technique
For the performance for improving transistor, the prior art has developed high-K dielectric layer/metal gate structure transistor.Usually
Metal gates are formed using rear metal gate process.
Specifically, the step of rear metal gate process includes: first to cover polysilicon layer on substrate, is carried out to polysilicon layer
Etching forms pseudo- grid；Then interlayer dielectric layer is filled between pseudo- grid, then the pseudo- grid in interlayer dielectric layer are removed by etching,
To form opening in the pseudo- grid situ, metal material is filled, in said opening later to form metal gates.
However, etching technics may make pseudo- grid be formed not in the step of performing etching to polysilicon layer, forming pseudo- grid
The pattern of rule.In addition, the etching for removing pseudo- grid is also possible to generate bad shadow to the pattern of opening in the etching for removing pseudo- grid
Ring, the technological factor of etching process so twice all may all cause opening bad appearance (such as opening side wall may
Form the irregular pattern such as ladder-like), increase the probability of the metal gates bad appearance formed in the opening, it is golden to having
The performance for belonging to the transistor of grid has an adverse effect.It should also be noted that, after filling interlayer dielectric layer between pseudo- grid,
It needs to carry out chemical mechanical grinding to interlayer dielectric layer before removing pseudo- grid, makes the interlayer dielectric layer and pseudo- grid surface phase
It flushes, in order to remove the pseudo- grid.However, pollutant is easily accessible interlayer Jie during carrying out chemical mechanical grinding
In matter layer and pseudo- grid structure, interlayer dielectric layer and pseudo- grid structure are polluted, to be easy when removing pseudo- grid in the opening
Pollutant is formed, and then will affect the reliability of the transistor with metal gates.
Summary of the invention
Problems solved by the invention is to provide a kind of Transistor forming method, improves the performance of transistor.
To solve the above problems, the present invention provides a kind of Transistor forming method, comprising:
Substrate is provided；
Source region, drain region are formed in the substrate, and the substrate between the source region and drain region is as channel region；
The sacrificial layer for covering the source region, drain region and channel region is formed over the substrate；
The sacrificial layer is patterned, to form the opening for exposing the channel region in sacrificial layer；
Metal gates are formed in said opening；
Remove remaining sacrificial layer.
Optionally, in the step of substrate surface forms sacrificial layer, the material of the sacrificial layer is hydrogen silsesquioxane
Alkane.
Optionally, the sacrificial layer of hydrogen silsesquioxane is formed using deposition or the method for spin coating.
Optionally, include: the step of the opening of the formation exposing channel region in sacrificial layer
Bar shaped photoresist is formed in the sacrificial layer surface, the bar shaped photoresist is corresponding with the aperture position；
The partial sacrificial layer exposed to the bar shaped photoresist is exposed processing, the portion for exposing the bar shaped photoresist
The material of sacrificial layer is divided to convert；
The unconverted sacrificial layer that the bar shaped photoresist blocks is removed, to form the opening.
Optionally, the material of the sacrificial layer is hydrogen silsesquioxane, the partial sacrifice exposed to the bar shaped photoresist
Layer is exposed processing, and the material for the partial sacrificial layer that the bar shaped photoresist exposes is converted into the oxide of silicon.
Optionally, the step of being exposed processing to bar shaped photoresist exposed portion sacrificial layer includes: to the item
Shape photoresist exposed portion sacrificial layer carries out electron beam exposure or uv-exposure.
Optionally, the transistor is fin formula field effect transistor, forms source region, drain region, source region and drain region in the substrate
Between substrate include: as the step of channel region
Etched substrate to form fin over the substrate, and the fin is used to form the channel region, to the fin
Both ends are doped, to form source-drain area；
The step of forming the sacrificial layer for covering the source region, drain region and channel region over the substrate includes: to be formed to cover
Cover the sacrificial layer of the fin；
The step of opening for exposing the channel region is formed in sacrificial layer includes: to form extending direction to hang down with the fin
Straight strip gab；
The step of forming metal gates in said opening includes: to be developed across in the metal gates of the fin.
Optionally, it is formed after fin, is formed before source-drain area over the substrate, formed be located at fin over the substrate
Isolation structure between portion makes the fin be higher than the isolation structure.
Optionally, the fin exposes the height of isolation structure in the range of 30 nanometers to 60 nanometers.
Optionally, the thickness of the sacrificial layer is in the range of 100 nanometers to 250 nanometers.
Optionally, the material of the sacrificial layer is hydrogen silsesquioxane, unconverted sacrificial layer is being removed, described in being formed
In the step of opening, the unconverted sacrificial layer is removed using tetramethyl ammonium hydroxide solution.
Optionally, it after forming the opening, is formed before metal gates in said opening, in the opening wall
And sacrificial layer surface forms dielectric layer.
Optionally, in said opening formed metal gates the step of include:
Metal layer is formed above the dielectric layer of portion and sacrificial layer surface in the opening;
Chemical mechanical grinding is carried out to the metal layer, metal layer and dielectric layer until removing sacrificial layer surface are located at
Metal layer in the opening is used to form metal gates.
Optionally, the transistor is CMOS, forms source region, drain region in the substrate, and the substrate between source region and drain region is made
Include: for the step of channel region
Source and drain doping is carried out to the substrate, the lining to form source region, drain region in the substrate, positioned at source region, drain region
Bottom is the channel region；
The step of forming the sacrificial layer for covering the source region, drain region and channel region over the substrate includes: described
The sacrificial layer is covered on substrate；
The step of opening for exposing the channel region is formed in sacrificial layer includes: to form extending direction and the channel region
The identical opening of extending direction；
The step of forming metal gates in said opening includes: to be formed between the source region, drain region on channel region
, extending direction metal gates identical with the channel region extending direction.
Compared with prior art, technical solution of the present invention has the advantage that
During the forming method of transistor of the present invention forms metal gates, using the opening being formed in sacrificial layer
The metal gates are formed, the step of forming pseudo- grid structure is eliminated, primary etching work is only carried out during forming opening
Skill reduces influence of the etching technics to opening shape looks, can form pattern and preferably be open, so as to so as to be formed in described open
Metal gates in mouthful have preferable pattern, and then improve the performance of the transistor with the metal gates.
The opening formed in the sacrificial layer is for defining size and the position of metal gates, the shape in the sacrificial layer
Before opening, the sacrificial layer is without chemical mechanical grinding processing, and therefore, the pollutant in sacrificial layer and opening is less,
The metal gates better performances formed in sacrificial layer split shed.
Further, the material of the sacrificial layer is hydrogen silsesquioxane, is formed in sacrificial layer and exposes the channel region
The step of opening includes: to form bar shaped photoresist, the bar shaped photoresist and the aperture position phase in the sacrificial layer surface
It is corresponding；Processing is exposed to the partial sacrificial layer that the bar shaped photoresist exposes, the part that the bar shaped photoresist exposes is sacrificial
The material of domestic animal layer converts；Unconverted sacrificial layer is removed, to form the opening.Processing is exposed to partial sacrificial layer
During, the hydrogen silsesquioxane that bar shaped photoresist exposes is converted into silica, after removing photoresist, using tetramethyl hydrogen-oxygen
Change ammonium salt solution and removes remaining hydrogen silsesquioxane, selection of the tetramethyl ammonium hydroxide solution to hydrogen silsesquioxane and silica
It is relatively high, substantially silica will not be caused to damage, therefore can etch by a step and remove hydrogen silsesquioxane completely, and
And remove hydrogen silsesquioxane after the opening side wall it is more smooth, the metal gates shape formed in said opening can be made
Looks are more preferable.
Detailed description of the invention
Fig. 1 to Figure 18 is the schematic diagram of each step in one embodiment of forming method of transistor of the present invention.
Specific embodiment
The prior art forms metal gates using pseudo- grid technique and needs twice etching technique, etching technics in pseudo- grid technique
It is easy to make the bad appearance of metal gates, have an adverse effect to the performance of metal gates and transistor.
In order to solve the above technical problem, the present invention provides a kind of Transistor forming methods, comprising: provides substrate；It is serving as a contrast
Source region, drain region are formed in bottom, the substrate between source region and drain region is as channel region；It is formed over the substrate and covers the source
The sacrificial layer in area, drain region and channel region；The sacrificial layer is patterned, exposes the channel to be formed in sacrificial layer
The opening in area, forms metal gates in said opening；Remove remaining sacrificial layer.
During the forming method of transistor of the present invention forms metal gates, using the opening being formed in sacrificial layer
The metal gates are formed, the step of forming pseudo- grid structure is eliminated, primary etching work is only carried out during forming opening
Skill reduces influence of the etching technics to opening shape looks, can form pattern and preferably be open, so as to so as to be formed in described open
Metal gates in mouthful have preferable pattern, and then improve the performance of the transistor with the metal gates.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 18 is the schematic diagram of each step in one embodiment of forming method of transistor of the present invention.This implementation
In example, the transistor is fin formula field effect transistor, but should not therefore limit Transistor forming method of the present invention and be formed
Transistor types, in other embodiments, Transistor forming method of the present invention can be also used for forming CMOS transistor.
It is Fig. 1 along the cross-sectional view of AA` line with reference to Fig. 1 and Fig. 2, Fig. 2, substrate 100 is provided.In the present embodiment, described
Substrate 100 is silicon substrate, and in other embodiments, the substrate 100 can also be germanium silicon substrate or silicon-on-insulator substrate etc.
Other semiconductor substrates do not do any restrictions to this present invention.
It continues to refer to figure 1 and Fig. 2 forms multiple fins (Fin) 201, the fin to the substrate 101 progress photoetching
Portion 201 is used to form source region, drain region and the channel region of fin formula field effect transistor.Specifically, the material of the fin 201 is
Silicon.
It continues to refer to figure 1 and Fig. 2, is formed after multiple fins 201, form isolation structure between multiple fins 201
101, the isolation structure 101 is fleet plough groove isolation structure, and in other embodiments, the isolation structure 101 can also be office
Portion's oxidation isolation.The isolation structure 101 is used for multiple transistor isolations.In other embodiments, institute can not also be formed
State isolation structure 101.
It should be noted that the fin 201 is higher than isolation structure 101, the fin 201 exposes isolation structure 101
For height in the range of 30 nanometers to 60 nanometers, i.e., the height of the subsequent channel region as fin formula field effect transistor is at 30 nanometers
To in the range of 60 nanometers, optionally, in the present embodiment, the height that the fin 201 goes out isolation structure 101 is 45 nanometers.
It is doped at 201 both ends of fin, forms source region, drain region (not shown), form source region, the method in drain region is ability
Domain conventional techniques, details are not described herein by the present invention.
It is cross-sectional view of the Fig. 3 along BB` line with reference to Fig. 3 and Fig. 4, Fig. 4, forms sacrificial layer on 101 surface of substrate
102, the sacrificial layer 102 is used to form opening corresponding with metal gates size, shaped position, with shape in said opening
At metal gates.
Specifically, in the present embodiment, the material of the sacrificial layer 102 is hydrogen silsesquioxane (Hydrogen Silses
Quioxane, HSQ) to form the sacrificial layer 102 of hydrogen silsesquioxane on 101 surface of substrate using the method for spin coating.But
Be the present invention to the forming method of sacrificial layer 102 with no restrictions, in other embodiments, can also be formed using the method for deposition
Sacrificial layer 102, the present invention to the specific material of sacrificial layer 102 also with no restrictions, in other embodiments, the sacrificial layer 102
Material can also contain the material of si-h bond and silicon oxygen bond for other.
The fin 201 is higher than the isolation structure 101, and optionally, the fin 201 exposes the height of isolation structure 101
Degree is in the range of 30 nanometers to 60 nanometers, correspondingly, range of the thickness of the sacrificial layer 102 at 100 nanometers to 250 nanometers
It is interior, to cover the part that the fin 201 exposes isolation structure 101.Specifically, in the present embodiment, the thickness of the sacrificial layer 102
Degree is 110 nanometers.
With reference to Fig. 5 to Fig. 8, the sacrificial layer 102 is patterned, exposes the fin to be formed in sacrificial layer 102
The opening 301 in portion 201.
Specifically, as shown in figs.5 and 6, Fig. 6 is cross-sectional view of the Fig. 5 along CC` line, in the present embodiment, in the hydrogen
102 surface of sacrificial layer of silsesquioxane forms patterned photoresist layer 401, described in the patterned photoresist layer 401
301 positions that are open are corresponding, therefore the shape of patterned photoresist layer 401 is bar shaped, the patterned photoresist layer 401
Exposed portion sacrificial layer 102 is exposed processing to sacrificial layer 102, the partial sacrifice for exposing patterned photoresist layer 401
The material of layer 102 is converted into silica, 102 material of sacrificial layer of the bar-shaped zone under the covering of patterned photoresist layer 401
It is still hydrogen silsesquioxane.
It should be noted that in the present embodiment, the patterned photoresist layer 401 is across two fins 201
Top, but the invention is not limited in this regard, the size of the corresponding metal gates of patterned photoresist layer 401, the figure
The photoresist layer 401 of shape can also be above multiple fins 201.
It should also be noted that, in the present embodiment, the shape of the patterned photoresist layer is bar shaped, but this hair
The bright shape to patterned photoresist layer with no restrictions, in other embodiments, the shape of the patterned photoresist layer
It can also be the other shapes such as pectination, correspondingly, the shape of the opening and metal gates can also be other shapes such as pectination
Shape.
To patterned photoresist layer 401 expose partial sacrificial layer 102 be exposed processing mode can choose for
Electron beam exposure or uv-exposure are exposed processing in the present embodiment by the way of uv-exposure.
Specifically, during being exposed processing to the sacrificial layer 102 by the way of uv-exposure, the figure of bar shaped
The sacrificial layer 102 of 401 covering part of photoresist layer of shape is bar shaped, and the sacrificial layer that patterned photoresist layer 401 exposes
102A is irradiated with ultraviolet radiation, and the silicon-hydrogen bond fracture in hydrogen silsesquioxane, hydrogen ion forms hydrogen discharge, silicon-hydrogen bond fracture
New silicon-oxygen key is formed between silicon and oxygen atom afterwards, so that the hydrogen sesquialter silicon that the patterned photoresist layer 401 of bar shaped exposes
Oxygen alkane is converted into the oxide of silicon, and the sacrificial layer 102B under the covering of patterned photoresist layer 401 is by ultraviolet irradiation,
Material is still hydrogen silsesquioxane, and sacrificial layer 102 includes transformed sacrificial layer 102A and unconverted sacrificial layer at this time
102B。
It should be noted that it should be noted that " oxide of silicon " of the present invention can be expressed as SiOx, also
It is to say, can be the silicon monoxide perhaps mixture of silica etc. or silicon monoxide, silica.
As shown in Figure 7, Figure 8, Fig. 8 is removal after Fig. 7 is exposed processing to sacrificial layer 102 along the cross-sectional view of DD` line
The photoresist layer 401.Specifically, the patterned photoresist layer can be removed by the way of removing or the removing of photoresist by plasma
401。
It is cross-sectional view of the Fig. 9 along EE` line with reference to Fig. 9, Figure 10, Figure 10, removes the unconverted sacrificial layer 102B, surplus
The extending direction strip gab 301 vertical with the fin 201, the opening are formed in remaining transformed sacrificial layer 102A
The fin 201 of 301 bottoms exposed portion.
Specifically, after removing patterned photoresist layer 401, the upper surface of the unconverted sacrificial layer 102B is revealed
Out, the shape of unconverted sacrificial layer 102B is bar shaped, in the present embodiment, since the material of unconverted sacrificial layer 102B is
Hydrogen silsesquioxane, therefore the unconverted sacrificial layer 102B is performed etching using tetramethyl ammonium hydroxide solution, tetramethyl
Base Ammonia is very high to the selection ratio of the oxide of hydrogen silsesquioxane and silicon, therefore can be etched by a step by hydrogen
Silsesquioxane removal is clean, substantially will not be to the remaining sacrificial layer for the oxide for having been converted into silicon in etching process
102A causes to damage, and the side wall of the opening 301 described in this way is more smooth, the hydrogen silsesquioxane for the 301 bottom edges that are open
What is be removed is relatively clean, therefore the subsequent metal gates pattern formed in opening 301 is preferable.
The present invention with no restrictions, in other embodiments, may be used also to the specific method for removing unconverted sacrificial layer 102B
To be performed etching using the solution of entitled CD26 to the unconverted sacrificial layer 102B.
The effect of the opening 301 is size and the position for the metal gates that definition is formed later.Crystal of the present invention in this way
The forming method of pipe eliminates the step of forming pseudo- grid structure during forming metal gates, does not need to be situated between in deposition interlayer
After matter layer, the deposition and etching of polysilicon are carried out, but forms the opening 301 of corresponding metal gates directly in sacrificial layer 102,
Save production cost.
The prior art needs one during forming pseudo- grid during forming opening 301 of corresponding metal gates
Secondary etching also needs to be removed the etching of pseudo- grid, needs twice etching, etch period altogether in this way during forming opening
It is longer, etching process is more complicated, the unstable fabrication error of etching process is more easy to happen, therefore twice etching is unstable
Technological factor all may cause the bad appearance of opening, increase the probability of metal gates bad appearance.
And technical solution of the present invention not necessarily forms pseudo- grid, directly forms metal gates in opening 301, is forming gold in this way
Before belonging to grid, it is only formed the opening 301 of corresponding metal gates by an etching technics, reduces etching technics factor
Adverse effect to 301 patterns of opening, can be effectively improved the pattern of metal gates.
In addition, in the sacrificial layer 102 by etching formed opening 301 before, remove patterned photoresist 103 it
Afterwards, the upper surface unconverted sacrificial layer 102B has been exposed, and can be directly removed to unconverted sacrificial layer 102B
To form opening 301, that is to say, that the remaining sacrificial layer 102A no longer needs to carry out chemical mechanical grinding processing, therefore, remains
The pollutants such as the heavy metal in remaining sacrificial layer 102A and opening 301 are less, and metal gates are formed in more clean ring
It is carried out in border, the metal gates better performances formed in the opening 301 in remaining sacrificial layer 102A.
With reference to Figure 11, Figure 12, Figure 12 is cross-sectional view of the Figure 11 along FF` line, formed in the opening 301 metal gates it
Before, dielectric layer 103 is formed in 301 inner walls of the opening and the surface remaining sacrificial layer 102A.
In the present embodiment, the dielectric layer 103 includes the multilayered structures such as gate dielectric layer, workfunction material, still
The present invention to the specific structure of dielectric layer 103 with no restrictions.
It is cross-sectional view of the Figure 13 along GG` line with reference to Figure 13, Figure 14, Figure 14, it is inside the opening 301 and remaining sacrificial
Metal layer 104 is formed above the dielectric layer 103 on the surface domestic animal layer 102A.
Specifically, in the present embodiment, made using physical vaporous deposition in 103 surface deposited metal layer 104 of dielectric layer
The metal layer 104 covers fin 201 and is higher than 102 surface of sacrificial layer.But the present invention to the forming method of metal layer 104 not
It is limited, in other embodiments, metal layer 104 can also be formed using other methods such as plating.
It is cross-sectional view of the Figure 15 along HH` line with reference to Figure 15, Figure 16, Figure 16, chemical machinery is carried out to the metal layer 104 and is ground
Mill removes extra metal layer 104 and extra dielectric layer 103 until by the dielectric layer 103 on the surface remaining sacrificial layer 102A
It completely removes, the metal layer 104 in the opening 301 forms metal gates.
It is Figure 17 along the cross-sectional view of II` line with reference to Figure 17, Figure 18, Figure 18, removes remaining sacrificial layer 102A, make metal gate
The dielectric layer 104 of pole side wall exposes.Specifically, use wet etching removal material for the remaining sacrificial layer of the oxide of silicon
102A, material is thus formed the fin formula field effect transistors with metal gates.
Removing remaining sacrificial layer 102A using wet etching is advantageous in that the selection of wet etching is relatively high, uses
Wet etching can make metal gates keep preferable pattern, but the present invention while removing remaining sacrificial layer 102A
With no restrictions to the specific method for removing remaining sacrificial layer 102A, it in other embodiments, can also be gone using dry etching
Except the remaining sacrificial layer 102A.
It should also be noted that, in other embodiments, transistor that Transistor forming method of the present invention is formed can be with
For CMOS, the process for forming CMOS is substantially the same with the process for forming fin formula field effect transistor.The difference is that:
During forming CMOS, after substrate is provided, fin is not necessarily formed, source and drain doping is carried out to the substrate,
Source region, drain region are formed in flat substrate, the substrate between source region and drain region is as channel region.
The step of forming the sacrificial layer for covering the source region, drain region and channel region over the substrate includes: described
The sacrificial layer is covered on flat substrate, optionally, the material of the sacrificial layer is hydrogen silsesquioxane.
Extending direction opening identical with the channel region extending direction is formed in sacrificial layer specifically can be in institute
It states sacrificial layer surface and forms bar shaped photoresist, the bar shaped photoresist is corresponding with the aperture position, to the bar shaped photoetching
The partial sacrificial layer that glue exposes is exposed processing, and the partial sacrificial layer that the bar shaped photoresist exposes converts, by hydrogen times
Half siloxanes is converted into the oxide of silicon, removes unconverted sacrificial layer, with the positions and dimensions of the corresponding metal gates of formation
Opening.
Between the source region, drain region on channel region, extending direction and the channel region are formed in said opening
The identical metal gates of extending direction.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of forming method of transistor characterized by comprising
Substrate is provided；
Source region, drain region are formed in the substrate, and the substrate between the source region and drain region is as channel region；
The sacrificial layer for covering the source region, drain region and channel region is formed over the substrate；
The sacrificial layer is patterned, to form the opening for exposing the channel region in sacrificial layer；
Metal gates are formed in said opening；
Remove remaining sacrificial layer；
Wherein, include: the step of the opening of the formation exposing channel region in sacrificial layer
Bar shaped photoresist is formed in the sacrificial layer surface, the bar shaped photoresist is corresponding with the aperture position；
The partial sacrificial layer exposed to the bar shaped photoresist is exposed processing, and the part for exposing the bar shaped photoresist is sacrificial
The material of domestic animal layer converts；Wherein, the step of being exposed processing to bar shaped photoresist exposed portion sacrificial layer include:
Electron beam exposure or uv-exposure are carried out to bar shaped photoresist exposed portion sacrificial layer；Wherein, the material of the sacrificial layer
For the material containing si-h bond and silicon oxygen bond；
The unconverted sacrificial layer that the bar shaped photoresist blocks is removed, to form the opening.
2. forming method as described in claim 1, which is characterized in that in the step of substrate surface forms sacrificial layer,
The material of the sacrificial layer is hydrogen silsesquioxane.
3. forming method as claimed in claim 2, which is characterized in that form hydrogen silsesquioxane using deposition or the method for spin coating
The sacrificial layer of alkane.
4. forming method as claimed in claim 1, which is characterized in that the material of the sacrificial layer is hydrogen silsesquioxane, to described
The partial sacrificial layer that bar shaped photoresist exposes is exposed processing, and the material for the partial sacrificial layer that the bar shaped photoresist exposes turns
Turn to the oxide of silicon.
5. forming method as described in claim 1, which is characterized in that the transistor is fin formula field effect transistor, is being served as a contrast
Source region, drain region are formed in bottom, the substrate between source region and drain region includes: as the step of channel region
For etched substrate to form fin over the substrate, the fin is used to form the channel region, to the fin both ends
It is doped, to form source-drain area；
The step of forming the sacrificial layer for covering the source region, drain region and channel region over the substrate includes: to form covering institute
State the sacrificial layer of fin；
The step of opening for exposing the channel region is formed in sacrificial layer includes: to form extending direction and the fin vertical
Strip gab；
The step of forming metal gates in said opening includes: to be developed across in the metal gates of the fin.
6. forming method as claimed in claim 5, which is characterized in that formed after fin over the substrate, form source and drain
Before area, the isolation structure between fin is formed over the substrate, the fin is made to be higher than the isolation structure.
7. forming method as claimed in claim 6, which is characterized in that the fin exposes the height of isolation structure at 30 nanometers
To in the range of 60 nanometers.
8. forming method as claimed in claim 7, which is characterized in that the thickness of the sacrificial layer is at 100 nanometers to 250 nanometers
In the range of.
9. forming method as described in claim 1, which is characterized in that the material of the sacrificial layer is hydrogen silsesquioxane,
Remove unconverted sacrificial layer, the step of to form the opening in, do not turn using tetramethyl ammonium hydroxide solution removal is described
The sacrificial layer of change.
10. forming method as claimed in claim 1 or 2, which is characterized in that after forming the opening, in the opening
Before middle formation metal gates, wall and sacrificial layer surface form dielectric layer in the opening.
11. forming method as claimed in claim 10, which is characterized in that the step of forming metal gates in said opening is wrapped
It includes:
Metal layer is formed above the dielectric layer of portion and sacrificial layer surface in the opening；
Chemical mechanical grinding is carried out to the metal layer, metal layer and dielectric layer until removing sacrificial layer surface are located at described
Metal layer in opening is used to form metal gates.
12. forming method as described in claim 1, which is characterized in that the transistor is CMOS, forms source in the substrate
Area, drain region, the substrate between source region and drain region include: as the step of channel region
Source and drain doping is carried out to the substrate, to form source region, drain region in the substrate, the substrate positioned at source region, drain region is
The channel region；
The step of forming the sacrificial layer for covering the source region, drain region and channel region over the substrate includes: in the substrate
The upper covering sacrificial layer；
The step of opening for exposing the channel region is formed in sacrificial layer includes: to form extending direction and channel region extension
The identical opening in direction；
In said opening formed metal gates the step of include: to be formed it is between the source region, drain region on channel region, prolong
Stretch direction metal gates identical with the channel region extending direction.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| CN103187289A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for multi-gate field effect transistor |
| CN103187260A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of fin field effect transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7795669B2 (en) * | 2007-05-30 | 2010-09-14 | Infineon Technologies Ag | Contact structure for FinFET device |
-
2014
- 2014-04-04 CN CN201410135884.1A patent/CN104979202B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6413802B1 (en) * | 2000-10-23 | 2002-07-02 | The Regents Of The University Of California | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture |
| CN103187289A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for multi-gate field effect transistor |
| CN103187260A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of fin field effect transistor |
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