CN104979205B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
- Publication number
- CN104979205B CN104979205B CN201410135925.7A CN201410135925A CN104979205B CN 104979205 B CN104979205 B CN 104979205B CN 201410135925 A CN201410135925 A CN 201410135925A CN 104979205 B CN104979205 B CN 104979205B
- Authority
- CN
- China
- Prior art keywords
- layer
- grid structure
- barrier layer
- etching barrier
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides a kind of forming method of transistor; in the rear grid technique of transistor; etch stopper layer surface above source-drain area forms protective layer; etching barrier layer is performed etching; the etching barrier layer on grid structure is thinned; it is thinned after the etching barrier layer on grid structure, the spacing increase between grid structure so that interlayer dielectric layer can be more easily filled between grid structure.During the etching barrier layer being thinned on grid structure; protective layer plays a part of protecting the etching barrier layer above source-drain area to be influenceed from etching; so that after the etching barrier layer being thinned on grid structure; the thickness of etching barrier layer above source-drain area does not change substantially, can provide and be effectively protected for source-drain area.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of forming method of transistor.
Background technology
As the transistor density on integrated circuit improves constantly, the size of grid also constantly reduces with spacing, corresponding grid
The spacing of pole structure also constantly reduces, and during filling interlayer dielectric layer between multiple grid structures, interlayer dielectric layer is very
Difficulty is filled into narrow spacing between multiple grid structures, the interlayer dielectric layer pattern out-of-flatness so formed, and in layer
Between be easy in dielectric layer produce space or crack.
As shown in figure 1, a kind of sectional view of transistor forming process of prior art is shown, with shallow trench isolation junction
Grid structure 04 is formed on structure 03, source-drain area 02 is formed in the substrate 01 that the grid structure 04 exposes, in the grid knot
Interlayer dielectric layer (not shown) is formed on structure 04 and source-drain area 02.Due to being formed after interlayer dielectric layer, it is also necessary to described in etching
Interlayer dielectric layer, formed in interlayer dielectric layer and expose the through hole of source-drain area 02, to form conductive material in through-holes, realized
Source-drain area 02 and periphery circuit electrical connection.
In order to avoid source-drain area 02 sustains damage during the etching interlayer dielectric layer of subsequent technique, it is situated between forming interlayer
Before matter layer, first one layer of etching barrier layer 05 is covered in source-drain area 02 and the surface of grid structure 04.
As shown in figure 1, during etching barrier layer 05 is covered, the etch stopper of the vertex covering of grid structure 04
Layer 05 is more compared with other regions, easily produces the bulge as irised out in Fig. 1 so that and the spacing between grid structure is smaller, so as to
The difficulty that interlayer dielectric layer is filled between grid structure is increased, and the quality of etching barrier layer 05 influences whether source-drain area
02 quality.
Therefore, how while interlayer dielectric layer filling effect between pseudo- grid structure is improved, ensure above source-drain area
The quality of etching barrier layer, turn into those skilled in the art's urgent problem to be solved.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of transistor, in raising interlayer dielectric layer in pseudo- grid structure
Between filling capacity while, ensure source-drain area above etching barrier layer quality.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：
Substrate is provided；
Grid structure is formed over the substrate；
Source-drain area is formed in the substrate that the grid structure exposes；
In the grid structure and source-drain area surface covering etching barrier layer；
Etch stopper layer surface above the source-drain area forms protective layer；
The etching barrier layer is performed etching, the etching barrier layer on grid structure is thinned；
Remove the protective layer；
Interlayer dielectric layer is formed on etching barrier layer after etching.
Optionally, the etching barrier layer is silicon nitride.
Optionally, after the grid structure and source-drain area surface covering etching barrier layer, formed before protective layer,
The forming method also includes：Silicon doping is carried out to the etching barrier layer.
Optionally, the etch stopper layer surface above the source-drain area is formed before protective layer, in the etch stopper
The mask layer of layer surface cover graphics, expose the etching barrier layer above source-drain area.
Optionally, the patterned mask layer is patterned photoresist.
Optionally, after the mask layer of cover graphics, using liquid phase deposition, reveal in the patterned mask layer
Etch stopper layer surface above the source-drain area gone out forms protective layer, before being performed etching to the etching barrier layer, removes
The patterned mask layer.
Optionally, the substrate is silicon substrate, and the material of the protective layer is silica.
Optionally, the step of liquid phase deposition formation protective layer includes：Silicate fluoride solution is passed through in etch stopper layer surface
And water, reaction generation silica.
Optionally, the protective layer is removed using hydrofluoric acid.
Optionally, the grid structure is the pseudo- grid structure for including pseudo- grid, and the forming method also includes：Forming interlayer
After dielectric layer, the pseudo- grid are removed；
Metal gates are formed in pseudo- grid original position.
Optionally, the transistor is fin formula field effect transistor, formed provide substrate after, formed grid structure it
Before, including：Fin is formed on substrate；
The step of formation grid structure, includes：The grid structure of the fin is developed across on the fin；
The step of source-drain area is formed in the substrate that the grid structure exposes includes：In the fin that the grid structure exposes
Middle formation source region and drain region.
Compared with prior art, technical scheme has advantages below：
Etch stopper layer surface above source-drain area forms protective layer, and etching barrier layer is performed etching, and grid is thinned
Etching barrier layer in structure, it is thinned after the etching barrier layer on grid structure, the spacing increase between grid structure so that
Interlayer dielectric layer can be more easily filled between grid structure.The process of etching barrier layer on grid structure is thinned
In, protective layer plays a part of protecting the etching barrier layer above source-drain area to be influenceed from etching so that in thinned grid structure
On etching barrier layer after, the thickness of the etching barrier layer above source-drain area does not change substantially, can be carried for source-drain area
For being effectively protected, while the etching barrier layer being thinned on grid structure can be that interlayer dielectric layer is filled between grid structure
Space is provided, is advantageous to improve the filling effect of interlayer dielectric layer..
Further, hindered in the mask layer of the etch stopper layer surface cover graphics, the etching for exposing active region
Barrier, the patterned mask layer is patterned photoresist, using liquid phase deposition, in the etching of the active region
Barrier layer surface forms protective layer, and the etching barrier layer is silicon nitride, and the material of the protective layer is silica, liquid deposition
The silica that method is formed easily is deposited on material surface, and is difficult on a photoresist deposition, therefore, in liquid phase deposition shape
During protective layer, protective layer is only deposited on the etch stopper layer surface that patterned photoresist exposes substantially, in photoetching
Only deposit a small amount of on glue or do not deposit protective layer substantially, so can directly remove the photoresist that unprotect layer blocks；In addition, also
The etch stopper layer surface for enabling to protective layer to be more accurately only deposited on above source-drain area, reduces because protective layer is formed at
The problem of on grid structure hindering that etching barrier layer is thinned.
Brief description of the drawings
Fig. 1 is a kind of sectional view of Transistor forming method of prior art；
Fig. 2 to Fig. 8 is the sectional view of each step in the embodiment of Transistor forming method one of the present invention.
Embodiment
In the forming method of prior art transistor, the etching barrier layer in source region and drain region is covered in easily in grid structure
Vertex deposition it is excessive and form bulge, the bulge make it that the spacing between grid structure is smaller, increases in grid knot
The difficulty of interlayer dielectric layer is filled between structure.In addition, the process being removed to the bulge is easily to source region and drain region surface
Etching barrier layer produced poly-injury, and have impact on protective effect of the etching barrier layer to source region and drain region.
In order to solve the above-mentioned technical problem, the present invention provides a kind of forming method of transistor.The forming method includes：
Substrate is provided；Grid structure is formed in the substrate surface；Source-drain area is formed in the substrate that the grid structure exposes；Institute
State grid structure and source-drain area surface covering etching barrier layer；Etch stopper layer surface above the source-drain area, which is formed, protects
Sheath；The etching barrier layer is performed etching, the etching barrier layer on grid structure is thinned；Remove the protective layer；Carving
Interlayer dielectric layer is formed on etching barrier layer after erosion.
The present invention forms protective layer by the etch stopper layer surface above the source-drain area so as to etch stopper
Layer perform etching, be thinned grid structure on etching barrier layer bulge during, protective layer plays protection etching barrier layer
The effect influenceed from etching so that after the etching barrier layer bulge being thinned on grid structure, the etching above source-drain area
The thickness on barrier layer does not change substantially, provides and is effectively protected for source-drain area.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to figs. 2 to the sectional view that Fig. 8 is each step in the embodiment of Transistor forming method one of the present invention.Need to illustrate
, in the present embodiment, the transistor is CMOS, but should not therefore limit Transistor forming method of the present invention and be formed
Transistor types, in other embodiments, Transistor forming method of the present invention can be also used for forming fin field effect crystal
Pipe.
With reference to figure 2, there is provided substrate 100, isolation structure 101 is formed in substrate 100.
In the present embodiment, the substrate 100 is silicon substrate, and the substrate 100 can also be germanium silicon substrate or insulator
Other Semiconductor substrates such as upper silicon substrate, any restrictions are not done to this present invention.
Specifically, after substrate 100 is provided, isolation structure 101 is formed also in substrate 100, substrate 100 is divided into more
Individual part, to form the transistor for being isolated structure 101 and keeping apart in different parts.
In the present embodiment, the isolation structure 101 is fleet plough groove isolation structure, in other embodiments, the isolation junction
Structure can also be carrying out local oxide isolation.In other embodiments, the isolation structure 101 can not also be formed.
With continued reference to Fig. 2, multiple grid structures 103 are formed on the substrate 100, in the lining that grid structure 103 exposes
Multiple source-drain areas 102 are formed in bottom 100, in substrate 100 and the surface of grid structure 103 covering etching barrier layer 104.
Rear metal gate process is used in the present embodiment, and grid structure 103 includes pseudo- grid 103A and gate dielectric layer 103B.
Wherein, pseudo- grid 103A material is polysilicon, and in follow-up technique, pseudo- grid 103A is removed, pseudo- grid 103A institutes
Metal material will be filled in position to form metal gates.But the present invention is not limited to pseudo- grid 103A specific material.
Gate dielectric layer 103B material is silica, and gate dielectric layer 103B's functions as metal gates and substrate
Dielectric layer between 100, but the present invention is not limited to gate dielectric layer 103B specific material.
In addition, side wall (not shown) is also formed in pseudo- grid 103A side walls, to protect pseudo- grid 103A.
In the present embodiment, multiple source-drain areas 102 are formed in the substrate 100 that the grid structure 103 exposes.Formed more
The specific method of individual source-drain area 102 is technology customary in the art, and the present invention will not be repeated here.
In the present embodiment, after source-drain area 102 is formed, covered in the substrate 100 and the surface of grid structure 103
Etching barrier layer 104.The effect of the etching barrier layer 104 is, avoids in follow-up etching technics, and source-drain area 102 is carved
Erosion influences and sustained damage.
Specifically, the material of the etching barrier layer 104 is silicon nitride, but the present invention is to the tool of etching barrier layer 104
Body material is not limited, and in other embodiments, the etching barrier layer 104 can also be other materials.
It should be noted that the etching barrier layer 104 in the vertex covering of grid structure 103 is more compared with other regions,
Easily produce the bulge as shown in Fig. 1 circle so that the spacing between grid structure 103 is narrower, in grid structure 103
Between fill interlayer dielectric layer it is more difficult.
It should also be noted that, in the present embodiment, in the substrate 100 and the surface of grid structure 103 covering etching
After barrier layer 104, silicon doping is carried out to the etching barrier layer 104 using silicon nitride as material, such to be advantageous in that, silicon doping
Silicon nitride afterwards is firmer and anti-etching ability is stronger, and causes in the follow-up etching that etching barrier layer 104 is thinned, quarter
The speed of erosion is slower, enhances the controllability of etching, reduces and is damaged to such as pseudo- grid 103A etchings because etch rate is too high
The probability of other structures beyond barrier layer 104.
With reference to figure 3, in the mask layer 105 of the surface cover graphics of etching barrier layer 104, expose on source-drain area 102
The etching barrier layer 104 of side.
In the present embodiment, the patterned mask layer 105 is patterned photoresist.Patterned mask layer 105
Expose the etching barrier layer 104 of the top of source-drain area 102, enable to follow-up protective layer to be only formed at the top of source-drain area 102.
With reference to figure 4, the surface of etching barrier layer 104 above the source-drain area 102 forms protective layer 106.
The surface of etching barrier layer 104 above the source-drain area 102, which forms protective layer 106, to be advantageous in that, follow-up
During the etching barrier layer 104 to be thinned above grid structure 103 is performed etching to etching barrier layer 104, source-drain area 102
Protection of the etching barrier layer 104 of top by the protective layer 106.The etching barrier layer 104 of so top of source-drain area 102 exists
Preferably protection can be provided during being subsequently formed metal gates for source-drain area 102.
In the present embodiment, protective layer 106 of the liquid phase deposition deposition materials for silica is used, specifically, is being etched
Barrier layer 104 and photoresist surface are passed through silicate fluoride solution and water, are reacted with the etching barrier layer 104 using silicon nitride as material
Silica is generated, the silica of deposition forms the protective layer 106.
It is advantageous in that the silica that liquid phase deposition is formed easily deposits using liquid phase deposition deposition protective layer 106
In the surface of material, and it is difficult on a photoresist deposition, therefore, during liquid phase deposition forms protective layer 106,
Protective layer 106 is only deposited on the surface of etching barrier layer 104 that patterned photoresist exposes substantially, and only deposition is few on a photoresist
Amount does not deposit protective layer 106 substantially, in order to the follow-up photoresist for directly removing the covering of unprotect layer.
In addition, the protective layer 106 so deposited is only positioned at the surface of etching barrier layer 104 of the top of source-drain area 102, follow-up
During the etching barrier layer 104 to be thinned above grid structure 103 is performed etching to etching barrier layer 104, only source-drain area
The etching barrier layer 104 of 102 tops is protected, and etching barrier layer 104 on grid structure 103 is exposed so as to be subtracted
It is thin.
Further, using being initially formed patterned photoresist, then the step of protective layer 106 is deposited by liquid phase deposition
Suddenly, enable to protective layer 106 to be more accurately deposited on the surface of etching barrier layer 104 of the top of source-drain area 102, reduce due to protecting
Sheath 106 is formed on grid structure 103, the probability hindered being thinned etching barrier layer 104 to cause.
But the present invention is not limited to the specific material of protective layer 106, the material of the protective layer 106 can also be not
It is same as the other materials of the material of etching barrier layer 104.
The present invention is not also limited to the forming method of protective layer 106, and in other embodiments, the protective layer 106 is also
Mode formed below can be used：The film layer of covering etching barrier layer 104 is first formed with chemical vapour deposition technique, then to the film
Layer carries out photoetching, removes the part film layer, and the film layer on the etching barrier layer 104 of the top of source-drain area 102 of reservation, which is formed, protects
Sheath 106.
With reference to figure 5, the patterned photoresist is removed, specifically, in the present embodiment, institute is removed using cineration technics
State patterned photoresist.During forming protective layer 106 due to liquid phase deposition, silica is easily deposited on material
Surface, and be difficult on a photoresist deposition, therefore only deposition is a small amount of on a photoresist or does not deposit protective layer 106 substantially, because
This, does not allow to be also easy to produce residual when removing the patterned photoresist using cineration technics.
With reference to figure 6, the etching barrier layer 104 is performed etching, so that the etching barrier layer on grid structure 103 is thinned
104.While etching barrier layer 104 being thinned above grid structure 103, the vertex etching barrier layer of grid structure 103
104 bulge is also removed or part removes so that the spacing increase between grid structure 103, between grid structure 103 more
Easily filling interlayer dielectric layer.
Specifically, the material of the etching barrier layer 104 is silicon nitride, using SiCoNi methods to the etching barrier layer
104 perform etching, such to be advantageous in that, the etching intensity of SiCoNi methods is smaller and is easier to control, to etch stopper
During layer 104 performs etching, by adjusting etch period and intensity, it will easily can be carved on the drift angle of grid structure 103
The bulge for losing barrier layer 104 is removed, and the etching barrier layer 104 of the upper surface of grid structure 103 and side wall is thinned, protective layer
Etching barrier layer 104 under 106 coverings is not influenceed then and remained by SiCoNi methods.
But the present invention is not limited to the specific lithographic method for etching the etching barrier layer 104, in other embodiment
In, the etching barrier layer 104 on dry etching or the thinned grid structure 103 of wet etching can also be used.
The etching barrier layer 104 on grid structure 103 is thinned, after the bulge for removing etching barrier layer 104, grid structure
The thickness of etching barrier layer 104 on 103 surfaces is homogeneous, pattern is smooth, and the space so between grid structure 103 will not be by bulge
Occupy so that subsequently relatively easily can fill interlayer dielectric layer between grid structure 103.
With reference to figure 7, the protective layer 106 is removed.
In the present embodiment, because the material of protective layer 106 is silica, so removing the protective layer using hydrofluoric acid
106.Silica can be removed using hydrofluoric acid relatively clean and smaller on the influence of the other structures such as etching barrier layer 104.
But etching agent is not limited used by the protective layer 106 of the invention to removal.
With reference to figure 8, after the protective layer 106 is removed, between the surface of substrate 100 and grid structure 103
Form interlayer dielectric layer 107.
Specifically, in the present embodiment, using chemical vapour deposition technique, in the surface of substrate 100 and grid structure
Interlayer dielectric layer 107 is filled between 103, and causes interlayer dielectric layer 107 to be higher than grid structure 103, the interlayer dielectric layer 107
Material be silica, but the present invention is not limited to the material of interlayer dielectric layer 107.
Due in step before, while by etching barrier layer 104 of the thinned top of grid structure 103, grid structure
The bulge of 103 vertex etching barrier layer 104 is also removed so that the spacing increase between grid structure 103, in grid knot
Filling interlayer dielectric layer 107 is easier between structure 103, the mass of interlayer dielectric layer 107 formed between grid structure 103 is more
It is good, it is not easy to the defects of producing space.
During forming silica using chemical vapour deposition technique, oxidation can be made by reducing the method for sedimentation rate
Silicon is finer and close, so as to improve the anti-etching ability of interlayer dielectric layer 107 so that in the technique of follow-up formation metal gates
In, interlayer dielectric layer 107 can keep good pattern.
After interlayer dielectric layer 107 is formed, cmp is carried out to interlayer dielectric layer 107 to expose pseudo- grid 103A
Surface.
Next the pseudo- grid 103A in grid structure 103 is removed, after removing pseudo- grid 103A, in pseudo- grid 103A original position shapes
Into metal gates.The method for removing pseudo- grid 103A and formation metal gates is technology customary in the art, and the present invention does not make to this
Limitation.
It should be noted that the forming method of transistor of the present invention is not limited to form metal gates crystalline substance using rear grid technique
The embodiment of body pipe, the transistor with polysilicon gate can also be formed, correspondingly, without removing pseudo- grid.
After interlayer dielectric layer is formed, the through hole to be formed and expose source region and drain region is performed etching to interlayer dielectric layer,
During forming through hole, etching barrier layer plays a part of the protection source region and drain region, so as to improve the property of transistor
Energy.
It should be noted that the forming method of transistor of the present invention can be also used for forming fin formula field effect transistor, with
Above-described embodiment difference is, after substrate is provided, is formed before grid structure, including：Fin is formed on substrate.Tool
Body, substrate (such as silicon substrate) is performed etching, forms fin (Fin).
The step of formation grid structure, includes：The grid structure of the fin is developed across on the fin.
The step of source-drain area is formed in the substrate that the grid structure exposes includes：The fin exposed to the grid structure
Middle formation source region and drain region.The etching barrier layer formed afterwards is covered in the grid structure and the grid structure exposes
The surface of fin.
Subsequent step is identical with CMOS forming method, will not be repeated here, in the present embodiment, by the way that grid structure is thinned
The etching barrier layer of vertex, improve the filling capacity of interlayer dielectric layer；Meanwhile also by setting protective layer in etching process
The etching barrier layer on fin surface is protected, to improve protective capability of the etching barrier layer to fin, and then improves fin field effect crystalline substance
The performance of body pipe.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (11)
- A kind of 1. forming method of transistor, it is characterised in that including：Substrate is provided；Grid structure is formed over the substrate；Source-drain area is formed in the substrate that the grid structure exposes；In the grid structure and source-drain area surface covering etching barrier layer；Etch stopper layer surface above the source-drain area forms protective layer；The etching barrier layer is performed etching, the etching barrier layer on grid structure is thinned；Remove the protective layer；Interlayer dielectric layer is formed on etching barrier layer after etching.
- 2. forming method as claimed in claim 1, it is characterised in that the etching barrier layer is silicon nitride.
- 3. forming method as claimed in claim 2, it is characterised in that carved in the grid structure and the covering of source-drain area surface After losing barrier layer, formed before protective layer, the forming method also includes：Silicon doping is carried out to the etching barrier layer.
- 4. forming method as claimed in claim 1, it is characterised in that the etch stopper layer surface shape above the source-drain area Into before protective layer, in the mask layer of the etch stopper layer surface cover graphics, expose the etch stopper above source-drain area Layer.
- 5. forming method as claimed in claim 4, it is characterised in that the patterned mask layer is patterned photoetching Glue.
- 6. forming method as claimed in claim 5, it is characterised in that after the mask layer of cover graphics, using liquid phase Sedimentation, the etch stopper layer surface above the source-drain area that the patterned mask layer exposes forms protective layer, to institute State before etching barrier layer performs etching, remove the patterned mask layer.
- 7. forming method as claimed in claim 6, it is characterised in that the substrate is silicon substrate, the material of the protective layer For silica.
- 8. forming method as claimed in claim 7, it is characterised in that liquid phase deposition formed protective layer the step of include： Etch stopper layer surface is passed through silicate fluoride solution and water, reaction generation silica.
- 9. forming method as claimed in claim 7, it is characterised in that the protective layer is removed using hydrofluoric acid.
- 10. forming method as claimed in claim 1, it is characterised in that the grid structure is the pseudo- grid structure for including pseudo- grid, The forming method also includes：After interlayer dielectric layer is formed, the pseudo- grid are removed；Metal gate is formed in pseudo- grid original position Pole.
- 11. forming method as claimed in claim 1, it is characterised in that the transistor is fin formula field effect transistor, is being carried After substrate, formed before grid structure, including：Fin is formed on substrate；The step of formation grid structure, includes： The grid structure of the fin is developed across on the fin；The step of source-drain area is formed in the substrate that the grid structure exposes is wrapped Include：Source region and drain region are formed in the fin that the grid structure exposes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410135925.7A CN104979205B (en) | 2014-04-04 | 2014-04-04 | The forming method of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410135925.7A CN104979205B (en) | 2014-04-04 | 2014-04-04 | The forming method of transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104979205A CN104979205A (en) | 2015-10-14 |
| CN104979205B true CN104979205B (en) | 2018-02-16 |
Family
ID=54275603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410135925.7A Active CN104979205B (en) | 2014-04-04 | 2014-04-04 | The forming method of transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104979205B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117276202B (en) * | 2023-11-16 | 2024-02-20 | 合肥晶合集成电路股份有限公司 | Forming method of contact hole and semiconductor structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924106A (en) * | 2009-06-15 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005191512A (en) * | 2003-12-01 | 2005-07-14 | Sharp Corp | Manufacturing method for semiconductor device |
| KR100589490B1 (en) * | 2003-12-30 | 2006-06-14 | 동부일렉트로닉스 주식회사 | Method For manufacturing Semiconductor Devices |
| US8741723B2 (en) * | 2012-04-25 | 2014-06-03 | Globalfoundries Inc. | Methods of forming self-aligned contacts for a semiconductor device |
-
2014
- 2014-04-04 CN CN201410135925.7A patent/CN104979205B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924106A (en) * | 2009-06-15 | 2010-12-22 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104979205A (en) | 2015-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI588879B (en) | Process of manufacturing fin-fet device and controlling heights of fin structures | |
| KR101248339B1 (en) | Method to fabricate adjacent silicon fins of differing heights | |
| CN105336571B (en) | The forming method of autoregistration multiple graphics mask | |
| CN104347371B (en) | The forming method of semiconductor structure | |
| CN103579007B (en) | For the post tensioned unbonded prestressed concrete area of isolation formation method of fin formula field effect transistor device | |
| US20140306272A1 (en) | Method of forming a finfet structure | |
| CN105655286A (en) | Forming method of semiconductor structure | |
| CN107346759B (en) | Semiconductor structure and manufacturing method thereof | |
| CN106033742B (en) | The forming method of semiconductor structure | |
| KR20120118232A (en) | Method of manufacturing semiconductor device | |
| CN104425220A (en) | Method for forming pattern | |
| CN104966669A (en) | Totally-surrounding gate structure manufacturing method | |
| CN109686702B (en) | Semiconductor structure and forming method thereof | |
| CN103177948A (en) | Method for forming fin portion of fin field effect tube and fin field effect tube | |
| US10043675B2 (en) | Semiconductor device and method for fabricating the same | |
| CN107045979B (en) | The forming method of semiconductor structure | |
| CN104979205B (en) | The forming method of transistor | |
| CN109962035A (en) | The forming method of semiconductor structure and imaging sensor | |
| CN103839868A (en) | Manufacturing method for shallow-trench isolation structure | |
| CN103632978A (en) | Formation method for semiconductor structure | |
| CN108122762B (en) | Semiconductor structure and forming method thereof | |
| KR100886004B1 (en) | Method for fabricating semiconductor device | |
| CN107731917B (en) | Method for forming semiconductor structure | |
| CN105161414B (en) | The minimizing technology of gate hard mask layer | |
| CN103730361A (en) | Semiconductor device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |