CN104332410B - A kind of manufacture method of fin formula field effect transistor - Google Patents
A kind of manufacture method of fin formula field effect transistor Download PDFInfo
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- CN104332410B CN104332410B CN201410620001.6A CN201410620001A CN104332410B CN 104332410 B CN104332410 B CN 104332410B CN 201410620001 A CN201410620001 A CN 201410620001A CN 104332410 B CN104332410 B CN 104332410B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000011435 rock Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000013517 stratification Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- -1 α-C Inorganic materials 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 13
- 239000000945 filler Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000012876 topography Methods 0.000 description 4
- 229910052582 BN Inorganic materials 0.000 description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 3
- 241001310793 Podium Species 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
Abstract
The present invention provides a kind of manufacture method of fin formula field effect transistor, dielectric layer is being etched back to before forming the fleet plough groove isolation structure between fin, first it is etched back to the preformed hard mask layer in fin upper surface and is allowed to part removal, then cap rock is formed in whole device surface, width of the cap rock equivalent to increase shallow trench filler, and improve the pattern of shallow trench filler, reduce the depth-to-width ratio for being etched back to window, so as to improve the flatness for being etched back to rear surface of shallow trench isolation structure, remaining hard mask layer can keep the side structure that fin exposes simultaneously, the final device performance for improving fin formula field effect transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of manufacture method of fin formula field effect transistor.
Background technology
MOS transistor is adjusted by the electric current of channel region to produce switching signal by applying voltage in grid.But work as
When semiconductor technology enters 45 nanometers with lower node, traditional plane formula MOS transistor dies down to the control ability of channel current,
Cause serious leakage current.I.e. so-called short-channel effect (SCE:Short-channel effects) it is easier to occur.
Due to such, planar CMOS transistor is gradually to three-dimensional (3D) fin formula field effect transistor (Fin Field
Effect Transistor, FinFET) device architecture transition.In FinFET, grid can at least be carried out from both sides to ultra-thin body
Control, there are the grid more much better than than planar MOSFET devices to the control ability of raceway groove, can be good at suppressing short-channel effect,
And relative other devices have the compatibility of more preferable integrated circuit production technology.
Fin formula field effect transistor (Fin FET) is a kind of common multi-gate device, and Fig. 1 shows one kind of prior art
The dimensional structure diagram of fin formula field effect transistor.As shown in figure 1, it is fin formula field effect transistor schematic diagram, fin field
Effect transistor is that this structure is long and narrow, therefore is referred to as fin structure (fin) 12 with an active region protruded from substrate 10；
Formed with shallow trench isolation (STI) 11 between two neighboring fin structure 12；The surface of fin structure 12 and shallow trench isolation 11
Formed with grid structure 13；Source/drain region (not shown) is located in fin structure 12, the both sides of grid structure 13；Channel region then position
In active region between the lower section of grid structure 13, source/drain region (not shown).For Fin FET, the top of fin structure 12
And the part that the side wall of both sides is in contact with grid structure 13 all turns into channel region, i.e., with multiple grid, be advantageous to increase and drive
Streaming current, improve device performance.
FinFET needs the surface topography of flat shallow trench isolation 11.However, the method formed in the prior art is first
Etching forms fin, the then fill oxide between fin, and be etched back to oxide, exposes enough fin height, shallow so as to be formed
Channel isolation.Because the vertical fin of fin structure 12 is unfavorable for the filling of oxide, cause the oxide surface pattern of filling not
Unanimously, and then to be etched back to the surface topography unevenness that oxide process easily causes the shallow trench isolation 11 to be formed.This
Obviously the stability of device will be substantially reduced.
Therefore, it is necessary to a kind of manufacture method of new fin formula field effect transistor, to avoid part drawbacks described above.
The content of the invention
It is an object of the invention to provide a kind of manufacture method of fin formula field effect transistor, it is possible to increase shallow trench is isolated
The flatness of the surface topography of structure.
To solve the above problems, the present invention provides a kind of manufacture method of fin formula field effect transistor, comprise the following steps：
Semiconductor substrate is provided, forms the hard mask layer of predefined thickness on the semiconductor substrate；
Hard mask layer described in selective etch and the Semiconductor substrate, to form fin, the fin both sides formed with
Shallow trench and upper surface still covers the hard mask layer；
The filled media layer in the shallow trench, the upper surface of the dielectric layer and the hard mask layer upper surface flat one
Cause；
The hard mask layer is etched back to certain depth, and lid is formed in the dielectric layer and the fin portion surface exposed
Layer；
Cap rock is removed completely and partly remove the dielectric layer, using technique is etched back to the fin upper surface apart from institute
State the predetermined altitude of dielectric layer upper surface.
Further, the cap rock is formed using sub-atmospheric pressure chemical vapor deposition (SACVD) technique.
Further, methods described also includes：After the cap rock is formed, thermal anneal process is carried out to the cap rock.
Further, the material of the cap rock and the dielectric layer is identical or different.
Further, the dielectric layer is the heap that silica, silicon oxynitride or oxide-nitride-oxide are formed
Stack structure, the cap rock are silica, silicon nitride or silicon oxynitride.
Further, the material of the hard mask layer is SiN, SiON, α-C, SiO2, BN, TiN, in metal silicide
It is at least one.
Further, the depth that is etched back to of the hard mask layer is more than
Further, the technique for being etched back to hard mask layer etches (remote for (wet etch) or remote plasma
Plasma etch), the technique for being etched back to dielectric layer etches for wet etching or remote plasma.
Further, the Semiconductor substrate be pure silicon, silicon-on-insulator (SOI), germanium, germanium silicon, carborundum, GaAs or
Person's germanium on insulator.
Further, the side wall of the shallow trench is vertical structure, and the fin is vertical structure unanimous between the higher and lower levels；Or
The side wall of the shallow trench has a gradient, it is described be etched back to technique after, the fin is located at the part above the dielectric layer
For vertical stratification, and the part being embedded in the dielectric layer is incline structure.
Compared with prior art, the manufacture method of fin formula field effect transistor provided by the invention, it is being etched back to dielectric layer
Before forming the fleet plough groove isolation structure between fin, to be first first etched back to the preformed hard mask layer in fin upper surface and be allowed to
Part removes, and then forms cap rock in whole device surface, and the cap rock and changes equivalent to the width of increase shallow trench filler
The pattern of kind shallow trench filler, reduces the depth-to-width ratio for being etched back to window, rear fleet plough groove isolation structure table is etched back to so as to improve
The flatness in face, while remaining hard mask layer can keep the side structure that fin exposes, and finally improve fin field effect
The device performance of transistor.
Brief description of the drawings
Fig. 1 is a kind of device profile structural representation of fin formula field effect transistor in the prior art；
Fig. 2 is the manufacture method flow chart of the fin formula field effect transistor of one embodiment of the invention；
Fig. 3 A to 3D are the device profile structural representation in the fin formula field effect transistor manufacture method shown in Fig. 2；
Fig. 4 A to 4D are the device profile knot in the fin formula field effect transistor manufacture method of another embodiment of the present invention
Structure schematic diagram.
Embodiment
To become apparent the purpose of the present invention, feature, the embodiment of the present invention is made below in conjunction with the accompanying drawings
Further instruction, however, the present invention can be realized with different forms, it is not considered that being simply confined to described embodiment.
Fig. 2 is refer to, one embodiment of the invention provides a kind of manufacture method of fin formula field effect transistor, including following step
Suddenly：
S1, there is provided Semiconductor substrate, form the hard mask layer of predefined thickness on the semiconductor substrate；
S2, hard mask layer described in selective etch and the Semiconductor substrate are selected, to form fin, fin both sides shape
Into having shallow trench and upper surface still covers the hard mask layer；
S3, the filled media layer in the shallow trench, the upper surface of the dielectric layer are put down with the hard mask layer upper surface
It is smooth consistent；
S4, the hard mask layer is etched back to certain depth, and formed in the dielectric layer and the fin portion surface exposed
Cap rock；
S5, remove cap rock completely using technique is etched back to and partly remove the dielectric layer, to the fin upper surface away from
From the predetermined altitude of the dielectric layer upper surface.
Refer to Fig. 3 A, in step sl, there is provided Semiconductor substrate 300 can be any semi-conducting material and can wrap
Known structure is included, such as gradient layer or oxygen buried layer can be included.In embodiment, Semiconductor substrate 300 includes to mix with right and wrong
Miscellaneous or doping (such as p-type, n-type or combinations thereof) bulk silicon.It can also use and be applied to what semiconductor devices was formed
Other materials.Such as the other materials of germanium, quartz, sapphire and glass can be optionally for Semiconductor substrate 300.It is optional
Ground, Semiconductor substrate 300 can be silicon either on silicon-on-insulator (SOI), germanium, germanium silicon, carborundum, GaAs or insulator
Germanium, the material of Semiconductor substrate 300 described in this implementation is silicon.In the Semiconductor substrate 300 deposit SiN (silicon nitride),
SiON (silicon oxynitride), α-C (Alpha's carbon), SiO2(silica), BN (boron nitride), TiN (titanium nitride) or metal silication
The hard mask materials such as thing form hard mask layer 302 respectively.To realize the good transfer effect of fin photoengraving pattern, hard mask layer
302 be preferably silicon nitride layer, and thickness is much larger than
It is mask with hard mask layer 302 in step s 2 please continue to refer to Fig. 3 A, uses photoetching technique, dry etching work
Skill forms fin 301 by patterning and etching Semiconductor substrate 300.It is shallow trench 306a (fins between adjacent fin 301
301 both sides are formed with shallow trench 306a), the upper surface of fin 301 still covers hard mask layer 302；Remaining hard mask layer 302 exists
Following fin 301 is protected in the ensuing processing step such as etched.The etching gas of the dry etching of this step can be with
It is for example, gas such as hydrogen bromide, sulfur hexafluoride and helium.In the present embodiment, the fin 301 that is formed after etching, its cross-section structure
For the consistent vertical structure (rectangle) of upper and lower width, it can strengthen Electrostatic Control of the grid to raceway groove using the vertical structure, subtract
The area of small whole chip, improves the integration density of device on chip, thus meets the making requirement of some products.
Fig. 3 B are refer to, in step s3, filled media layer (i.e. isolated material) 303, can be used in the shallow trench
Known chemical vapor deposition or physical gas-phase deposition carry out the filling of oxide layer, such as by using tetraethyl orthosilicate
(TEOS) and oxygen forms the dielectric layer 303 as chemical vapor deposition (CVD) technology of precursor, or by will such as oxygen,
Dielectric layer 303 is formed in nitrogen, carbon Plasma inpouring to Semiconductor substrate 300.Then, through CMP process so that
The surface of dielectric layer 303 and the upper surface flush of hard mask layer 302.
Then, Fig. 3 C are refer to, in step s 4, are etched back to cover firmly using wet etching or remote plasma etching technics
Film layer 302 is to certain depth, i.e., remaining certain thickness hard mask layer 302a.Then, sunk using such as sub-atmospheric pressure chemical vapor
The processing procedure that product (SACVD) technique etc. has conformality forms cap rock 304 in device surface, can after the cap rock 304 is formed
To carry out high annealing (such as thermal anneal process) to the cap rock 304 to strengthen its compactness.Cap rock 304 and dielectric layer 303
Material can be with identical, can also be different.Cap rock 304 and dielectric layer 303 are silica in the present embodiment.Cap rock 304 can increase
Add the width (filler width can be regarded as so that filler is extended in outside shallow ridges notch) of filler in shallow trench, to improve
The pattern of shallow trench filler.
Then, Fig. 3 D are refer to, in step s 5, cap rock 304 and dielectric layer 303 is etched back to, forms shallow trench isolation knot
Structure 306.Specifically, remote plasma dry etching or wet-etching technology can be used to be etched back, wherein described wet
Method etching technics is that either hydrochloric acid or phosphoric acid perform etching using the hydrofluoric acid diluted.The presence of cap rock 304, reduce back quarter
The depth-to-width ratio of fenetre mouth, improve the surface topography uniformity of shallow trench filler, so as to improve be etched back to rear shallow trench every
From the flatness of body structure surface.Pattern of the fin during being etched back to of remaining hard mask layer 302a protections below, especially
It is side pattern, while advantageously forms the double step structure of fin 301.In the present embodiment, cap rock 304 is in hard mask layer
302 be etched back to after it is unfilled in the region that is formed, it is self aligned to serve in technique is etched back to, improve technique effect
Rate and etching precision, and then improve device performance.In the present embodiment, after being etched back to, the surface of isolation structure of shallow trench 306
Less than the upper surface of fin 301, the cross-section structure of fin 301 is the consistent vertical structure (rectangle) of upper and lower width, that is, is exposed to
Vertical component 301a above dielectric layer is consistent with the width for the buried regions part 301b being embedded in dielectric layer 303.It is vertical using this
Structure can strengthen Electrostatic Control of the grid to raceway groove, reduce the area of whole chip, improve the integration density of device on chip,
Thus the making requirement of some products is met.Meanwhile regulation is etched back to depth to adjust the podium level between upper and lower two parts
(two-part relative position up and down can also be regarded as), i.e. height ratio between vertical component 301a and buried regions part 301b,
Optimal device performance can be realized.
In the present embodiment, after step s 5, remaining hard mask layer 302a can be removed, can also be retained.Can be with
Continue to carry out ion implanting in the position of fin 301, form source region and drain region, afterwards shape on the channel region between source region and drain region
Into grid oxic horizon and grid.So as to complete the making of fin formula field effect transistor.
Fig. 4 A to 4D are refer to, in another embodiment of the invention, according to the fin formula field effect transistor shown in Fig. 2
Manufacture method flow, by the process parameter control different from Fig. 3 A to 3D, different fin formula field effect transistors can be formed.
For example, in step s 2, the fin 301 formed after etching, its cross-section structure can be trapezoidal, i.e., up-narrow and down-wide structure, its
Preferably effect is played in base angle when isolated material can be filled in follow-up shallow trench, avoids fin vertical structure from being unfavorable for shallow ridges
The shortcomings that groove is filled, can avoid the formation of filling cavity defect.This structure with respect to the structure in Fig. 3 A for, device integrates
Density is relatively large, can meet the making requirement of other products.Fig. 4 D are refer to, and then in step s 5, after being etched back to,
Fin 301 is etched to the different two parts up and down of slope：Vertical component 301a above dielectric layer and it is embedded in medium
Buried regions part 301b in layer 303.And the podium level that regulation is etched back to depth to adjust between upper and lower two parts (can also be seen
It is upper and lower two-part relative position to do), i.e. podium level between vertical component 301a and buried regions part 301b, it is possible to achieve
Optimal device performance.
In summary, the manufacture method of fin formula field effect transistor provided by the invention, being etched back to dielectric layer to be formed
Before fleet plough groove isolation structure between fin, first it is etched back to the preformed hard mask layer in fin upper surface and is allowed to part
Remove, then form cap rock in whole device surface, the cap rock and improves shallow ridges equivalent to the width of increase shallow trench filler
The pattern of groove filler, the depth-to-width ratio for being etched back to window is reduced, the flat of rear surface of shallow trench isolation structure is etched back to so as to improve
Smooth degree, while remaining hard mask layer can keep the side structure that fin exposes, and finally improve fin formula field effect transistor
Device performance.
Obviously, those skilled in the art can carry out the spirit of various changes and modification without departing from the present invention to invention
And scope.So, if these modifications and variations of the present invention belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
- A kind of 1. manufacture method of fin formula field effect transistor, it is characterised in that including：Semiconductor substrate is provided, forms the hard mask layer of predefined thickness on the semiconductor substrate；Hard mask layer described in selective etch and the Semiconductor substrate, to form fin, the fin both sides are formed with shallow ridges Groove and upper surface still covers the hard mask layer；The filled media layer in the shallow trench, the upper surface of the dielectric layer are flat consistent with the hard mask layer upper surface；The hard mask layer is etched back to certain depth, and remaining certain thickness hard mask layer, and in the dielectric layer and sudden and violent The fin portion surface exposed forms cap rock；Cap rock is removed completely and partly remove the dielectric layer, given an account of to fin upper surface distance using technique is etched back to The predetermined altitude of matter layer upper surface.
- 2. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that using sub-atmospheric pressure chemistry vapour Phase depositing operation forms the cap rock.
- 3. the manufacture method of fin formula field effect transistor as claimed in claim 2, it is characterised in that also include：Forming institute After stating cap rock, thermal anneal process is carried out to the cap rock.
- 4. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the cap rock is with being given an account of The material of matter layer is identical or different.
- 5. the manufacture method of fin formula field effect transistor as claimed in claim 4, it is characterised in that the dielectric layer is oxidation The stacked structure that silicon, silicon oxynitride or oxide-nitride-oxide are formed, the cap rock is silica, silicon nitride or nitrogen Silica.
- 6. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the material of the hard mask layer Matter is SiN, SiON, α-C, SiO2, BN, TiN, at least one of metal silicide.
- 7. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the hard mask layer returns Etching depth is more than
- 8. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that be etched back to hard mask layer Technique is that wet etching or remote plasma etch, and the technique for being etched back to dielectric layer is that wet etching or remote plasma are carved Erosion.
- 9. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the Semiconductor substrate is Pure silicon, silicon-on-insulator, germanium, germanium silicon, carborundum, GaAs or germanium on insulator.
- 10. the manufacture method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the side of the shallow trench Wall is vertical structure, and the fin is vertical structure unanimous between the higher and lower levels；It is described or the side wall of the shallow trench has gradient After being etched back to technique, the part that the fin is located above the dielectric layer is vertical stratification, and is embedded in the dielectric layer Part is incline structure.
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| CN201410620001.6A CN104332410B (en) | 2014-11-05 | 2014-11-05 | A kind of manufacture method of fin formula field effect transistor |
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| CN201410620001.6A CN104332410B (en) | 2014-11-05 | 2014-11-05 | A kind of manufacture method of fin formula field effect transistor |
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| CN106409748B (en) * | 2015-08-03 | 2020-11-17 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN107919325A (en) * | 2016-10-10 | 2018-04-17 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of fin formula field effect transistor |
| CN110957219B (en) * | 2018-09-26 | 2023-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111446211B (en) * | 2019-01-17 | 2022-10-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112436051A (en) * | 2020-11-03 | 2021-03-02 | 西安电子科技大学 | 4H-SiC metal semiconductor field effect transistor with symmetrical stepped oxygen buried layer |
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