CN113451121A - Fin manufacturing method of FinFET device - Google Patents
Fin manufacturing method of FinFET device Download PDFInfo
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- CN113451121A CN113451121A CN202010211746.2A CN202010211746A CN113451121A CN 113451121 A CN113451121 A CN 113451121A CN 202010211746 A CN202010211746 A CN 202010211746A CN 113451121 A CN113451121 A CN 113451121A
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- finfet device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 6
- 239000011737 fluorine Substances 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 125000001153 fluoro group Chemical group F* 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 125000001309 chloro group Chemical group Cl* 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical class [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method for fabricating a fin of a FinFET device, comprising: step S1, etching an etching groove (110) on the semiconductor substrate (100) to form a fin (200) between two adjacent etching grooves (110); step S2, applying ODL (300) in the etching groove (110) to make the ODL (300) reach a certain height of the fin (200); step S3, dry etching the portion of the fin (200) above the ODL (300) with fluorine radicals to etch the fin (200) into a tower shape. The fin manufacturing method of the FinFET device is novel in design and high in practicability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fin manufacturing method of a FinFET device.
Background
Fin etching is a conventional step in the FinFET fabrication process. The fin profile is formed post-etch, specifically by using a self-aligned dual-mode (SADP) process including core etch, spacer etch, and core removal techniques, as shown in fig. 1. In the prior art, the shape and the width of the fin are difficult to adjust, the base of the fin is not wide enough, and the fin is easy to bend near the fin cutting area through the contraction processing after FCVD, as shown by the enclosed part of the square frame in figures 2-3.
Disclosure of Invention
The invention provides a fin manufacturing method of a FinFET device aiming at the technical problems.
The technical scheme provided by the invention is as follows:
the invention provides a fin manufacturing method of a FinFET device, which comprises the following steps:
step S1, etching an etching groove on the semiconductor substrate to form a fin between two adjacent etching grooves;
step S2, applying ODL in the etching groove to make the ODL reach a certain height of the fins;
step S3, dry etching the part of the fin above the ODL with fluorine radicals to etch the fin into a tower shape.
In the above-described fin manufacturing method of the present invention, in step S3, the portion of the fin above the ODL is dry-etched using a fluorine group or a chlorine group.
In the above fin fabricating method of the present invention, in step S3, CF is adopted4The portion of the fin above the ODL is dry etched.
The fin manufacturing method comprises the following steps:
step S1, etching an etching groove on the semiconductor substrate to form a fin between two adjacent etching grooves;
step S2, applying ODL in the etching groove to make the ODL reach a certain height of the fins;
step S3, performing oxygen treatment on the portion of the fin above the ODL and performing wet etching to etch the fin into a tower shape.
In the fin manufacturing method of the present invention, after step S3, the fin manufacturing method of the FinFET device of this embodiment further includes: the ODL was removed.
The fin manufacturing method comprises the following steps:
step S1, etching an etching groove on the semiconductor substrate to form a fin between two adjacent etching grooves;
step S2, passivating the outer walls of the fins in situ by using oxygen;
step S3, adopting SiO2Etching and selection of SiAnd selecting the corrosive gas with the ratio of 30-100 to carry out dry etching on the bottom of the etching groove so as to etch the fins into a tower shape.
In the fin manufacturing method of the invention, the etching gas selects He and O2And HBr.
The manufacturing method of the fin of the FinFET device can obtain the tower-shaped fin with two cone angles, and can ensure that the width of the bottom of the fin is wider, which is beneficial to reducing the bending effect of the fin near the fin cutting area in the post FCVD shrinkage process. Meanwhile, the size of the cone angle can be adjusted by adjusting the ODL thickness. The fin manufacturing method of the FinFET device is novel in design and high in practicability.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
fig. 1 illustrates a flow diagram of a method of fabricating a fin of a prior art FinFET device;
fig. 2 is a first photograph of a fin fabricated using the fin fabrication method of the FinFET device of fig. 1;
fig. 3 is a second photograph of a fin fabricated using the fin fabrication method of the FinFET device of fig. 1;
fig. 4 shows a flow diagram of a method of fabricating a fin of a FinFET device in accordance with a first embodiment of the invention;
fig. 5 shows a flow diagram of a method of fabricating a fin of a FinFET device in accordance with a second embodiment of the invention;
fig. 6 shows a flow diagram of a method of fabricating a fin of a FinFET device in accordance with a third embodiment of the invention;
fig. 7 is a photograph of a fin fabricated using the fin fabrication method of the FinFET device shown in fig. 6.
Detailed Description
In order to make the technical purpose, technical solutions and technical effects of the present invention more clear and facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
First embodiment
As shown in fig. 4, fig. 4 is a flow chart illustrating a method for fabricating a fin of a FinFET device according to a first embodiment of the present invention. The embodiment provides a fin manufacturing method of a FinFET device, which comprises the following steps:
step S1, etching an etch trench 110 on the semiconductor substrate 100, so that a fin 200 is formed between two adjacent etch trenches 110;
step S2, applying ODL (Organic underlying Layer)300 in the etch bath 110 to make the ODL300 reach a certain height of the fin 200;
step S3, dry etching the portion of the fin 200 above the ODL300 with fluorine radicals (fluorine chemical) to etch the fin 200 into a tower shape.
In the above-mentioned technical solution, by applying the ODL300 in the etch bath 110, the fluorine group can be prevented from corroding the portion of the fin 200 below the ODL 300.
In step S3, the portion of fin 200 above ODL300 may be dry etched using fluorine or chlorine radicals. Here, the fluorine group may be derived from CF4。
Further, after step S3, the method for fabricating a fin of a FinFET device of this embodiment further includes: ODL300 was removed.
By adopting the fin manufacturing method of the FinFET device of the embodiment, the tower-shaped fin with two cone angles can be obtained, the width of the bottom of the fin can be wider, and the bending effect of the fin near the fin cutting area in the post-FCVD shrinkage process can be reduced. Meanwhile, the size of the taper angle can be realized by adjusting the thickness of the ODL 300.
Second embodiment
As shown in fig. 5, fig. 5 is a flow chart illustrating a method for fabricating a fin of a FinFET device according to a second embodiment of the present invention. The embodiment provides a fin manufacturing method of a FinFET device, which comprises the following steps:
step S1, etching an etch trench 110 on the semiconductor substrate 100, so that a fin 200 is formed between two adjacent etch trenches 110;
step S2, applying ODL (Organic underlying Layer)300 in the etch bath 110 to make the ODL300 reach a certain height of the fin 200;
in step S3, the portion of fin 200 above ODL300 is treated with oxygen and wet etched to etch fin 200 into a tower shape.
In the above technical solution, by applying the ODL300 in the etch bath 110, the portion of the fin 200 below the ODL300 can be prevented from being corroded.
Further, after step S3, the method for fabricating a fin of a FinFET device of this embodiment further includes: ODL300 was removed.
By adopting the fin manufacturing method of the FinFET device of the embodiment, the tower-shaped fin with two cone angles can be obtained, the width of the bottom of the fin can be wider, and the bending effect of the fin near the fin cutting area in the post-FCVD shrinkage process can be reduced. Meanwhile, the size of the taper angle can be realized by adjusting the thickness of the ODL 300.
Third embodiment
As shown in fig. 6, fig. 6 is a flow chart illustrating a method for fabricating a fin of a FinFET device according to a third embodiment of the present invention. The embodiment provides a fin manufacturing method of a FinFET device, which comprises the following steps:
step S1, etching an etch trench 110 on the semiconductor substrate 100, so that a fin 200 is formed between two adjacent etch trenches 110;
step S2, passivating the outer walls of fins 200 in situ with oxygen;
step S3, adopting SiO2And the etching gas with the/Si etching selection ratio of between 30 and 100 carries out dry etching on the bottom of the etching groove 110 so as to etch the fin 200 into a tower shape.
In the above solution, by passivating the outer wall of the fin 200 with oxygen in situ in step S2, the etching of the portion of the fin 200 above the ODL300 by the etching gas in step S3 can be reduced.
The step S3 of the present embodiment adopts the most popular dry etching process today, reactive ion etching. Since corrosion is by contrastThe active groups and active atoms in the reaction cavity and the material are subjected to chemical reaction and plasma (ions and electrons) to bombard the surface of the material. In order to increase the selectivity of the chemical reaction, the chemical composition of the process gas should be made as much as possible more aggressive towards Si than SiO in order to etch away Si2The ability of the cell to perform. For gases typical of etching Si, such as fluorocarbon, chlorine, bromine compounds, studies have shown that extremely high Si/SiO ratios are achieved when plasma etching is used2The corrosion selectivity ratio is He or O2And HBr as the process gas.
Preferably, the etching gas is selected from He and O2And HBr, and correspondingly controlling HBr: O in the plasma by adjusting the flow rates of the HBr and the HBr2The ratio is between 10:1 and 20:1, thereby achieving the purpose of high corrosion selectivity.
By adopting the fin manufacturing method of the FinFET device of this embodiment, a tower-shaped fin with two taper angles can be obtained, and the width of the bottom of the fin can be made wider, which helps reduce the fin bending effect near the fin cutting region during the post-FCVD shrinkage process, as shown by the region surrounded by the box in fig. 7. Meanwhile, the size of the taper angle can be achieved by adjusting the thickness of the ODL300, i.e., by adjusting D1 and D2.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (7)
1. A method for fabricating a fin of a FinFET device, comprising:
step S1, etching an etching groove (110) on the semiconductor substrate (100) to form a fin (200) between two adjacent etching grooves (110);
step S2, applying ODL (300) in the etching groove (110) to make the ODL (300) reach a certain height of the fin (200);
step S3, dry etching the portion of the fin (200) above the ODL (300) with fluorine radicals to etch the fin (200) into a tower shape.
2. The fin manufacturing method according to claim 1, wherein in step S3, a portion of the fin (200) above the ODL (300) is dry-etched using a fluorine group or a chlorine group.
3. The fin manufacturing method according to claim 2, wherein in step S3, CF is adopted4The portion of the fin (200) above the ODL (300) is dry etched.
4. A method for fabricating a fin of a FinFET device, comprising:
step S1, etching an etching groove (110) on the semiconductor substrate (100) to form a fin (200) between two adjacent etching grooves (110);
step S2, applying ODL (300) in the etching groove (110) to make the ODL (300) reach a certain height of the fin (200);
step S3, the portion of the fin (200) above the ODL (300) is treated with oxygen and wet etched to etch the fin (200) into a tower shape.
5. The fin manufacturing method according to any one of claims 1 to 4, wherein after step S3, the fin manufacturing method of the FinFET device of the present embodiment further includes: the ODL (300) is removed.
6. A method for fabricating a fin of a FinFET device, comprising:
step S1, etching an etching groove (110) on the semiconductor substrate (100) to form a fin (200) between two adjacent etching grooves (110);
step S2, passivating the outer wall of the fin (200) in situ by adopting oxygen;
step S3, using SiO2The etching gas with the/Si etching selection ratio of 30-100 carries out dry etching on the bottom of the etching groove (110) so as to etch the fin (200) into a tower shape.
7. The method as claimed in claim 6, wherein the etching gas is selected from He and O2And HBr.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010211746.2A CN113451121A (en) | 2020-03-24 | 2020-03-24 | Fin manufacturing method of FinFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010211746.2A CN113451121A (en) | 2020-03-24 | 2020-03-24 | Fin manufacturing method of FinFET device |
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| Publication Number | Publication Date |
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| CN113451121A true CN113451121A (en) | 2021-09-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010211746.2A Pending CN113451121A (en) | 2020-03-24 | 2020-03-24 | Fin manufacturing method of FinFET device |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290911A (en) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and preparation method thereof |
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| CN102651305A (en) * | 2011-02-25 | 2012-08-29 | 中国科学院微电子研究所 | Method for preparing omega-shaped fin |
| CN103050533A (en) * | 2011-10-14 | 2013-04-17 | 台湾积体电路制造股份有限公司 | Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications |
| US20150340289A1 (en) * | 2014-05-21 | 2015-11-26 | Globalfoundries Inc. | Methods of fabricating semiconductor fin structures |
| CN106847698A (en) * | 2015-12-07 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and the method for improving performance of semiconductor device |
| CN109411415A (en) * | 2018-09-07 | 2019-03-01 | 上海集成电路研发中心有限公司 | A kind of forming method of semiconductor structure |
| CN109962017A (en) * | 2017-12-22 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
-
2020
- 2020-03-24 CN CN202010211746.2A patent/CN113451121A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290911A (en) * | 2007-04-17 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Flash memory and preparation method thereof |
| CN102347237A (en) * | 2010-07-29 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device structure comprising stress layer |
| CN102651305A (en) * | 2011-02-25 | 2012-08-29 | 中国科学院微电子研究所 | Method for preparing omega-shaped fin |
| CN103050533A (en) * | 2011-10-14 | 2013-04-17 | 台湾积体电路制造股份有限公司 | Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications |
| US20150340289A1 (en) * | 2014-05-21 | 2015-11-26 | Globalfoundries Inc. | Methods of fabricating semiconductor fin structures |
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Application publication date: 20210928 |