CN117766392A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a substrate, the substrate comprising: a substrate; a gate structure; a source/drain region; a first dielectric layer; etching the grid structure, and forming a mask groove in the first dielectric layer; forming a cover layer in the mask groove, wherein the top of the cover layer is flush with the first dielectric layer; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer. In the process of forming the source-drain contact layer, the cover layer plays a role of a self-aligned mask, and the difficulty in forming the source-drain contact layer can be effectively reduced through the formation of the cover layer.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

As CMOS device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET can effectively control the short channel effect which is difficult to overcome due to scaling down of the device, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, the grid electrode in the FinFET is arranged around the fin part, so that static electricity can be controlled from three surfaces, and the performance in static electricity control is more outstanding.

As the distance between the contact nodes of the semiconductor device decreases, the critical dimensions (Critical Dimension, CD) of the source and drain contact points in the semiconductor structure also continue to decrease, thereby providing a significant challenge for the formation of the source and drain contact layers.

The prior method for forming the source-drain contact layer has the problem of overlarge difficulty.

Disclosure of Invention

The invention solves the problem of reducing the difficulty of forming a contact layer.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

forming a substrate, the substrate comprising: a substrate; a gate structure located on the substrate; the source drain region is positioned on the substrate at two sides of the grid structure; the first dielectric layer is filled on the source-drain region between the adjacent gate structures, and the top of the first dielectric layer is flush with the top of the gate structures; etching the grid structure, and forming a mask groove in the first dielectric layer; forming a cover layer in the mask groove, wherein the top of the cover layer is flush with the first dielectric layer; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer, wherein the source-drain contact layer is positioned on the source-drain region and is in contact with the source-drain region, and the top of the source-drain contact layer is not lower than the top of the cover layer.

Optionally, the material of the cap layer includes silicon nitride; the material of the first dielectric layer comprises silicon oxide.

Optionally, the thickness of the cover layer is as followsTo->Within the range.

Optionally, the method further comprises: after a cover layer is formed in the mask groove, a hard mask is formed on the cover layer and the first dielectric layer before a source-drain contact layer is formed by taking the cover layer as a mask; and in the step of forming the source-drain contact layer, the cover layer and the hard mask are used as masks.

Optionally, the step of forming the source-drain contact layer includes: forming a contact opening in the first dielectric layer by taking the cover layer and the hard mask as masks, wherein the bottom of the contact opening exposes the source drain region; and forming a source-drain contact layer in the contact opening.

Optionally, the method further comprises: forming a second dielectric layer on the cover layer after forming the cover layer and before forming a hard mask; in the step of forming the source-drain contact layer, the top of the source-drain contact layer is flush with the top of the second dielectric layer.

Optionally, in the step of forming the substrate, the gate structure includes a gate electrode and a gate sidewall, where the gate sidewall is located on a sidewall of the gate electrode; and in the step of etching the gate structure, etching the gate electrode, and reducing the height of the gate electrode to form the mask groove.

Optionally, the method further comprises: after the source-drain contact layer is formed, a gate contact layer and a source-drain connection layer are formed, wherein the gate contact layer is positioned on the gate structure and is electrically connected with the gate structure, and the source-drain connection layer is positioned above the source-drain contact layer and is electrically connected with the source-drain contact layer.

Optionally, the step of forming the gate contact layer and the source drain connection layer includes: forming a gate opening penetrating through the cover layer, wherein the bottom of the gate opening exposes the gate structure; and forming a gate contact layer positioned in the gate opening and a source-drain connection layer positioned on the source-drain contact layer.

Optionally, the method further comprises: etching the source-drain contact layer before forming a gate opening penetrating through the cover layer, and forming a connecting groove on the source-drain contact layer; in the step of forming the gate contact layer positioned in the gate opening and the source-drain connection layer positioned on the source-drain contact layer, the source-drain connection layer is formed in the connection groove and is electrically connected with the rest of the source-drain contact layer.

Optionally, in the step of forming a source-drain contact layer, the source-drain contact layer includes: a conductive layer; a contact layer located on the side wall and the bottom of the conductive layer; and etching the conductive layer to reduce the height of the conductive layer in the step of etching the source-drain contact layer.

Optionally, the material of at least one of the gate contact layer and the source-drain connection layer includes: tungsten.

Optionally, the material of the source-drain contact layer includes cobalt.

Optionally, in the step of forming a substrate, the gate structure is a fully-surrounding gate structure; the substrate further comprises: at least one channel layer stacked on the substrate in a direction perpendicular to the surface of the substrate with a gap therebetween; the gate structure is positioned on the at least one channel layer and surrounds any channel layer; the source drain region is positioned in the at least one channel layer at two sides of the gate structure and is contacted with the side wall of any channel layer.

Correspondingly, the invention also provides a semiconductor structure, which is formed by the forming method of the invention, comprising the following steps:

a substrate, the substrate comprising: a substrate; a gate structure located on the substrate; the source drain region is positioned on the substrate at two sides of the grid structure; a cap layer over the gate structure; the source-drain contact layer is positioned on the source-drain region and is in contact with the source-drain region, and the top of the source-drain contact layer is not lower than the top of the cover layer.

Optionally, the material of the cap layer includes silicon nitride.

Optionally, the thickness of the cover layer is as followsTo->Within the range.

Optionally, the gate structure includes a gate electrode and a gate sidewall, where the gate sidewall is located on the gate electrode sidewall; the grid side wall also extends to the side wall of the cover layer.

Optionally, the method further comprises: the gate contact layer is positioned on the gate structure and is electrically connected with the gate structure, and the source-drain connection layer is positioned above the source-drain contact layer and is electrically connected with the source-drain contact layer.

Optionally, the source-drain contact layer includes: a conductive layer; a contact layer located on the side wall and the bottom of the conductive layer; the contact layer also extends between the cap layer and the source drain connection layer.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the technical scheme, a mask groove is formed by etching the grid structure; forming a cover layer in the mask groove; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer. In the process of forming the source-drain contact layer, the cover layer plays a role of a self-aligned mask, and the difficulty in forming the source-drain contact layer can be effectively reduced through the formation of the cover layer.

In an alternative embodiment of the present invention, the material of the cap layer includes silicon nitride, and the material of the first dielectric layer includes silicon oxide. The silicon nitride and the silicon oxide have larger etching selectivity difference, and the source-drain contact layer is formed by taking the cover layer as a self-aligned mask, so that the difficulty of a forming process can be effectively reduced, and the quality of forming the source-drain contact layer can be effectively improved.

In the alternative scheme of the invention, the source-drain contact layer is etched, and a connecting groove is formed on the source-drain contact layer; and forming a source-drain connection layer in the connection groove, wherein the source-drain connection layer is electrically connected with the rest of the source-drain contact layer. The source-drain contact layer is made of cobalt, and the parasitic capacitance can be effectively controlled due to the reduction of the height of the source-drain contact layer.

Drawings

Fig. 1 to 8 are schematic structural views of steps of a method for forming a semiconductor structure;

fig. 9 to 18 are schematic cross-sectional views illustrating steps of a semiconductor forming method according to an embodiment of the present invention.

Detailed Description

As known from the background art, the method for forming the source-drain contact in the prior art has a problem of great difficulty. The reason for the great difficulty in analyzing the problem by combining a forming method of a semiconductor structure is as follows:

referring to fig. 1-8, there are shown schematic structural diagrams of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate is formed, the substrate including: a substrate 11; a gate structure 12, the gate structure 12 being located on the substrate 11; the source drain region 13 is positioned on the substrate 11 at two sides of the gate structure 12; the first dielectric layer 14 is filled on the source drain region 13 between the adjacent gate structures 12, and the top of the first dielectric layer 14 is flush with the top of the gate structures 12.

Wherein the gate structure 12 is a fully-surrounding gate structure, the substrate further comprises: at least one channel layer 15, the at least one channel layer 15 being stacked on the substrate 11 in a direction perpendicular to the surface of the substrate 11, the at least one channel layer 15 having a gap with the substrate 11; the gate structure 12 is located on the at least one channel layer 15 and surrounds any one of the channel layers 15; the source drain region 13 is located in the at least one channel layer 15 at two sides of the gate structure 12 and contacts with a sidewall of any channel layer 15.

Referring to fig. 2, a capping layer 21, a second dielectric layer 22, a hard mask layer 23, a third dielectric layer 24, and a pattern layer 25 are sequentially formed on the substrate, and the pattern layer 25 is used to define the position and size of a source-drain contact layer 42 (shown in fig. 5).

Referring to fig. 3 and fig. 4, the third dielectric layer 24, the hard mask layer 23, the second dielectric layer 22, the cap layer 21 and the first dielectric layer 14 are sequentially etched by using the pattern layer 25 as a mask, so as to form source-drain contact openings 41, and the bottoms of the source-drain contact openings 41 expose the source-drain regions 13. Specifically, as shown in fig. 3, the third dielectric layer 24 is etched by using the pattern layer 25 as a mask, and an etching opening 31 is formed in the third dielectric layer 24; as shown in fig. 4, the hard mask layer 23, the second dielectric layer 22, the cap layer 21 and the first dielectric layer 14 are further etched along the etching openings 31 until the source drain regions 13 are exposed, so as to form the source drain contact openings 41.

Referring to fig. 5, a source-drain contact layer 42 is formed in the source-drain contact opening 41. Specifically, the step of forming the source-drain contact layer 42 includes: filling the source-drain contact openings 41 with a conductive material; the conductive material is planarized to form the source drain contact layer 42.

Referring to fig. 6 to 8, a gate contact layer 54 on the gate structure 12 and a source drain connection layer 55 on the source drain contact layer 42 are formed. Specifically, the step of forming the gate contact layer 54 and the source-drain connection layer 55 includes: as shown in fig. 6, a fourth dielectric layer 51 is formed on the substrate, and the fourth dielectric layer 51 is located on the source-drain contact layer 42; forming a gate contact opening 52 penetrating through the fourth dielectric layer 51, wherein the bottom of the gate contact opening 52 exposes the gate structure 12; as shown in fig. 7, a connection opening 53 is formed through the fourth dielectric layer 51, the connection opening 53 is located on the source-drain contact layer 42 and the bottom exposes the source-drain contact layer 42; as shown in fig. 8, the gate contact layer 54 located in the gate contact opening 52 and the source-drain connection layer 55 located in the connection opening 53 are formed.

As technology nodes advance and device sizes decrease, the distance between adjacent source and drain regions 13 becomes smaller, the process of defining and forming source and drain contact openings 41 through the pattern layer 25 becomes more difficult, and the risk of short circuits between the formed source and drain contact layers 42 and between the source and drain contact layers 42 and the gate contact layer 54 becomes greater.

Moreover, in order to control the resistance, the material of the source-drain contact layer 42 is often cobalt, and the parasitic capacitance between the source-drain contact layer 42 and the gate contact layer 54, and between the source-drain contact layers 42, is also relatively large.

In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps:

forming a substrate, the substrate comprising: a substrate; a gate structure located on the substrate; the source drain region is positioned on the substrate at two sides of the grid structure; the first dielectric layer is filled on the source-drain region between the adjacent gate structures, and the top of the first dielectric layer is flush with the top of the gate structures; etching the grid structure, and forming a mask groove in the first dielectric layer; forming a cover layer in the mask groove, wherein the top of the cover layer is flush with the first dielectric layer; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer, wherein the source-drain contact layer is positioned on the source-drain region and is in contact with the source-drain region, and the top of the source-drain contact layer is not lower than the top of the cover layer.

According to the technical scheme, a mask groove is formed by etching the grid structure; forming a cover layer in the mask groove; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer. In the process of forming the source-drain contact layer, the cover layer plays a role of a self-aligned mask, and the difficulty in forming the source-drain contact layer can be effectively reduced through the formation of the cover layer.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 9 through 18, schematic cross-sectional structures of steps of an embodiment of a semiconductor forming method of the present invention are shown.

Referring to fig. 9, a substrate is formed, the substrate including: a substrate 110; a gate structure 120, the gate structure 120 being located on the substrate 110; a source drain region 130, wherein the source drain region 130 is located on the substrate 110 at two sides of the gate structure 120; and the first dielectric layer 140 is filled on the source-drain region 130 between the adjacent gate structures 120, and the top of the first dielectric layer 140 is flush with the top of the gate structure 120.

The substrate is adapted to provide a process basis. Wherein the substrate 110 is used to provide a process basis for subsequent process steps.

In some embodiments of the present invention, the material of the substrate 110 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate 110 may be selected from polysilicon or amorphous silicon; the material of the substrate 110 may also be selected from other semiconductor materials such as germanium, gallium arsenide, or silicon germanium compounds. The substrate 110 may also have an epitaxial layer or a silicon-on-epitaxial structure.

The gate structure is used for controlling the opening and closing of the channel.

In some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 includes a gate electrode 121 and a gate sidewall 122, and the gate sidewall 122 is located on a sidewall of the gate electrode 121.

It should be noted that, in some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 is a fully-surrounding gate structure as shown in fig. 9; the substrate further comprises: at least one channel layer 111, the at least one channel layer 111 being stacked on the substrate 110 in a direction perpendicular to a surface of the substrate 110, the at least one channel layer 111 having a gap with the substrate 110; the gate structure 120 is located on the at least one channel layer 111 and surrounds any one of the channel layers 111; the source drain region 130 is located in the at least one channel layer 111 at two sides of the gate structure 120 and contacts with a sidewall of any channel layer 111.

Source drain regions 130 are located on substrate 110 on both sides of gate structure 120.

In some embodiments of the present invention, the gate structure 120 is a fully-surrounding gate structure; the substrate further comprises: at least one channel layer 111, the gate structure 120 surrounding any of the channel layers 111; the source drain regions 130 are in contact with sidewalls of each of the channel layers 111.

Note that, in the gap between the at least one channel layer 111 and the substrate 110 and the gap between the adjacent channel layers 111, a sidewall (not shown) is disposed between the gate structure 120 and the source drain region 130 to isolate the gate structure 120 from the source drain region 130.

The first dielectric layer 140 is located between adjacent gate structures 120 to achieve electrical isolation between adjacent gate structures 120.

Specifically, the material of the first dielectric layer 140 includes silicon oxide. In other embodiments of the present invention, the material of the first dielectric layer 140 may be a low K dielectric material or an ultra low K dielectric material.

Referring to fig. 10, the gate structure 120 is etched to form a mask recess 151 in the first dielectric layer 140.

The mask recess 151 is used to provide space for the formation of a cap layer.

In some embodiments of the present invention, in the step of etching the gate structure 120, the gate electrode 121 is etched, and the height of the gate electrode 121 is reduced to form the mask recess 151. Specifically, the part of the thickness of the gate electrode 121 is etched and removed, and the remaining gate electrode 121 and gate sidewall 122 are surrounded by the first dielectric layer 140 to form the mask recess 151.

In some embodiments of the present invention, a portion of the thickness of the gate electrode 121 is removed by dry etching. Specifically, in the step of removing a portion of the thickness of the gate electrode 121 by dry etching, the process parameters include: the etching gas is Cl and F based gas.

Note that, the gate structure 120 is a fully-surrounding gate structure, and the gate structure 120 surrounds any one of the channel layers 111; in the step of removing a portion of the thickness of the gate electrode 121, a portion of the thickness of the gate electrode 121 on the at least one channel layer 111 is removed to form the mask recess 151.

Referring to fig. 11, a cap layer 152 is formed in the mask recess 151 (shown in fig. 10), and the top of the cap layer 152 is flush with the first dielectric layer 140.

The capping layer 152 is used to serve as a self-aligned mask in a subsequent process, particularly in the process of forming the source-drain contact layer, and the capping layer 152 is used as the self-aligned mask, so that the process difficulty is effectively reduced, and the process window is enlarged.

In some embodiments of the present invention, the material of the first dielectric layer 140 includes silicon oxide; the material of the cap layer 152 comprises silicon nitride. The difference of the etching selectivity between the silicon nitride and the silicon oxide is larger, the material of the cover layer 152 is set to be silicon nitride, and the cover layer 152 is used as a self-aligned mask to form the source-drain contact layer, so that the difficulty of a forming process can be effectively reduced, the quality of forming the source-drain contact layer can be effectively improved, no extra material is introduced, and unnecessary process risks are not caused.

In some embodiments of the invention, the thickness of the cap layer 152 is atTo->Within the range. The thickness of the cap layer 152 is related to the depth of the mask recess 151, and if the thickness of the cap layer 152 is too large, the depth of the mask recess 151 is too large, and the thickness of the remaining gate structure 120 is too small, which may adversely affect the performance of the gate structure 120; the thickness of the cap layer 152, if too small, may affect the implementation of its self-aligned masking function.

Specifically, the step of forming the cap layer 152 includes: depositing a capping material within the mask recess 151, the capping material filling the mask recess 151 and extending onto the first dielectric layer 140; and removing part of the cover layer material higher than the first dielectric layer 140, and forming the cover layer 152 in the mask groove 151.

In the step of depositing the cap layer material in the mask groove 151, the cap layer material is deposited in the mask groove 151 by a film formation mode such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.; in the step of removing the part of the capping material above the first dielectric layer 140, the part of the capping material above the first dielectric layer 140 is removed by chemical mechanical polishing to form the capping layer 152.

Referring to fig. 12 to 15, the first dielectric layer 140 is etched with the cap layer 152 as a mask to form a source-drain contact layer 167 (as shown in fig. 15), the source-drain contact layer 167 is located on the source-drain region 130 and contacts the source-drain region 130, and the top of the source-drain contact layer 167 is not lower than the top of the cap layer 152.

It should be noted that, in some embodiments of the present invention, as shown in fig. 12, after the cap layer 152 is formed in the mask recess 151, a hard mask 162 is formed on the cap layer 152 and the first dielectric layer 140 before the source-drain contact layer 167 is formed by using the cap layer 152 as a mask; in the step of forming the source-drain contact layer 167, the cap layer 152 and the hard mask 162 are used as masks. The hard mask 162 and the cover layer 152 are used as a mask together, so that the effect of the mask can be effectively ensured, the process risk is reduced, and the process window is enlarged.

Specifically, in some embodiments, the material of the hard mask 162 is silicon nitride, and the hard mask 162 may be formed by a film formation method such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

Furthermore, in some embodiments of the present invention, the forming method further includes: after forming the cap layer 152, a second dielectric layer 161 is formed on the cap layer 152 prior to forming a hard mask 162; in the step of forming the source-drain contact layer, the top of the source-drain contact layer is flush with the top of the second dielectric layer 161.

The second dielectric layer 161 is used to provide electrical isolation between adjacent structures and also to provide a good growth surface for the formation of the hard mask 162.

In some embodiments of the present invention, the material of the second dielectric layer 161 is silicon oxide, and the second dielectric layer 162 may be formed by a film formation method such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

In some embodiments of the present invention, the step of forming the source-drain contact layer includes: as shown in fig. 12 to 14, using the capping layer 152 and the hard mask 162 as masks, a contact opening 166 is formed in the first dielectric layer 140, and the bottom of the contact opening 166 exposes the source drain region 130; a source-drain contact layer 167 is formed within the contact opening 166.

Specifically, as shown in fig. 12, a third dielectric layer 163 and a pattern layer 164 are sequentially formed on the hard mask 162, and the pattern layer 164 is used to define the shape and the position of the contact opening 166; as shown in fig. 13, the pattern of the pattern layer 164 is transferred to the third dielectric layer 163, and an etching opening 165 is formed in the third dielectric layer 163, where the etching opening 165 is located on the first dielectric layer 140 between the adjacent gate structures 120; as shown in fig. 14, the hard mask 162 and the second dielectric layer 161 exposed at the bottom of the etched opening 165 are removed along the etched opening 165, and the first dielectric layer 140 between the adjacent gate structures 120 is further removed, so as to form the contact opening 166.

As shown in fig. 15, in the step of forming the source-drain contact layer 167, the source-drain contact layer 167 includes: a conductive layer 167a; a contact layer 167b, the contact layer 167b being located on the sidewall and bottom of the conductive layer 167a. The step of forming the source-drain contact layer 167 within the contact opening 166 thus comprises: forming a contact layer 167b at the bottom and sidewalls of the contact opening 166; the contact openings 166, which are formed with contact layers 167b at the bottom and sidewalls, are filled with a first conductive material to form the conductive layers 167a.

In some embodiments of the present invention, the material of the source-drain contact layer 167 comprises cobalt. Specifically, in the source-drain contact layer 167, the material of the conductive layer 167a is cobalt. The material of the source-drain contact layer 167 is cobalt, so that the stability and the electrical performance of the source-drain contact layer 167 can be effectively improved, and the overall performance of the source-drain contact layer 167 can be effectively improved.

As shown in fig. 15, in some embodiments of the present invention, a second dielectric layer 161 is further formed on the capping layer 152; thus, in the step of forming the source-drain contact layer 167, the top of the source-drain contact layer 167 is flush with the top of the second dielectric layer 161, i.e., the tops of the conductive layer 167a and the contact layer 167b are flush with the top of the second dielectric layer 161.

Referring to fig. 16 to 18, in some embodiments of the invention, the forming method further includes: after forming the source-drain contact layer 167, a gate contact layer 174 (as shown in fig. 18) and a source-drain connection layer 173 (as shown in fig. 18) are formed, the gate contact layer 174 being located on the gate structure 120 and electrically connected to the gate structure 120, the source-drain connection layer 173 being located above the source-drain contact layer 167 and electrically connected to the source-drain contact layer 167.

The gate contact layer 174 is used to electrically connect the gate structure 120 to an external circuit, and the source-drain connection layer 173 is used to electrically connect the source-drain region 130 to the external circuit through the source-drain contact layer 167.

In some embodiments of the present invention, the material of at least one of the gate contact layer 174 and the source-drain connection layer 173 includes: tungsten. The materials of the gate contact layer 174 and the source-drain connection layer 173 are tungsten, so that the stability and performance of connection between the gate structure 120 and the source-drain contact layer 167 and an external circuit can be effectively ensured.

In some embodiments of the present invention, the step of forming the gate contact layer 174 and the source drain connection layer 173 includes: as shown in fig. 17, a gate opening 172 is formed through the cap layer 152, and the bottom of the gate opening 172 exposes the gate structure 120; as shown in fig. 18, a gate contact layer 174 located within the gate opening 172 and a source-drain connection layer 173 located on the source-drain contact layer 167 are formed.

Specifically, the material on the gate structure 120 is etched using the cap layer 152 as a mask to form a gate opening 172 on the gate structure 120.

As shown in fig. 16, the forming method further includes: before forming a gate opening 172 (as shown in fig. 17) penetrating the cap layer 152, etching the source-drain contact layer 167, and forming a connection groove 171 on the source-drain contact layer 167; in the step of forming the gate contact layer 174 located in the gate opening 172 and the source-drain connection layer 173 located on the source-drain contact layer 167, the source-drain connection layer 173 is formed in the connection groove 171, and the source-drain connection layer 173 is electrically connected to the remaining source-drain contact layer 167.

By etching the source-drain contact layer 167 to form the connection groove 171, the height of the source-drain contact layer 167 can be reduced, so that the source-drain connection layer 173 replaces a part of the source-drain contact layer with a thickness, parasitic capacitance can be effectively controlled, and particularly, when the material of the source-drain connection layer 173 comprises tungsten and the material of the source-drain contact layer 167 comprises cobalt, performance of the semiconductor structure can be effectively improved.

In some embodiments of the present invention, in the step of etching the source-drain contact layer 167, the source-drain contact layer 167 is etched by dry etching. Specifically, in the step of etching the source-drain contact layer 167 by dry etching, specific process parameters include: the process gas comprises: cl and F are based gases.

In the step of etching the source/drain contact layer 167, the conductive layer 167a is etched to reduce the height of the conductive layer 167a, and the remaining conductive layer 167a and the contact layer 167b enclose the connection groove 171.

Note that, the gate structure 120 and the conductive layer 167a in the source-drain contact layer 167 are etched to reduce the thickness thereof; in some embodiments, after forming the source-drain connection layer 173 and the gate contact layer 174, the top of the gate structure 120 and the top of the source-drain contact layer 167 are reduced in height. As shown in fig. 18, in some embodiments, the top of the gate structure 120 and the source drain contact layer 167 are flush and below the top of the cap layer 152. Specifically, the top of the gate structure 120 and the source-drain contact layer 167 are both flush with the interface of the cap layer 152 and the gate structure 120.

Correspondingly, the invention further provides a semiconductor structure.

Referring to fig. 18, a schematic cross-sectional structure of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure is formed by the method for forming the semiconductor structure.

The semiconductor structure includes:

a substrate, the substrate comprising: a substrate 110; a gate structure 120, the gate structure 120 being located on the substrate 110; a source drain region 130, wherein the source drain region 130 is located on the substrate 110 at two sides of the gate structure 120; a cap layer 152, the cap layer 152 being located on the gate structure 120; a source-drain contact layer 167, the source-drain contact layer 167 being located on the source-drain region 130 and in contact with the source-drain region 130, the top of the source-drain contact layer 167 being not lower than the top of the cap layer 152.

The substrate is adapted to provide a process basis. Wherein the substrate 110 is used to provide a process basis for subsequent process steps.

In some embodiments of the present invention, the material of the substrate 110 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate 110 may be selected from polysilicon or amorphous silicon; the material of the substrate 110 may also be selected from other semiconductor materials such as germanium, gallium arsenide, or silicon germanium compounds. The substrate 110 may also have an epitaxial layer or a silicon-on-epitaxial structure.

The gate structure 120 is used to control the opening and closing of the channel.

In some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 includes a gate electrode 121 and a gate sidewall 122, and the gate sidewall 122 is located on a sidewall of the gate electrode 121.

It should be noted that, in some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 is a fully-surrounding gate structure as shown in fig. 9; the substrate further comprises: at least one channel layer 111, the at least one channel layer 111 being stacked on the substrate 110 in a direction perpendicular to a surface of the substrate 110, the at least one channel layer 111 having a gap with the substrate 110; the gate structure 120 is located on the at least one channel layer 111 and surrounds any one of the channel layers 111; the source drain region 130 is located in the at least one channel layer 111 at two sides of the gate structure 120 and contacts with a sidewall of any channel layer 111.

Source drain regions 130 are located on substrate 110 on both sides of gate structure 120.

In some embodiments of the present invention, the gate structure 120 is a fully-surrounding gate structure; the substrate further comprises: at least one channel layer 111, the gate structure 120 surrounding any of the channel layers 111; the source drain regions 130 are in contact with sidewalls of each of the channel layers 111.

Note that, in the gap between the at least one channel layer 111 and the substrate 110 and the gap between the adjacent channel layers 111, a sidewall (not shown) is disposed between the gate structure 120 and the source drain region 130 to isolate the gate structure 120 from the source drain region 130.

The first dielectric layer 140 is located between adjacent gate structures 120 to achieve electrical isolation between adjacent gate structures 120.

Specifically, the material of the first dielectric layer 140 includes silicon oxide. In other embodiments of the present invention, the material of the first dielectric layer 140 may be a low K dielectric material or an ultra low K dielectric material.

The substrate is adapted to provide a process basis. Wherein the substrate 110 is used to provide a process basis for subsequent process steps.

In some embodiments of the present invention, the material of the substrate 110 is monocrystalline silicon. In other embodiments of the present invention, the material of the substrate 110 may be selected from polysilicon or amorphous silicon; the material of the substrate 110 may also be selected from other semiconductor materials such as germanium, gallium arsenide, or silicon germanium compounds. The substrate 110 may also have an epitaxial layer or a silicon-on-epitaxial structure.

The gate structure is used for controlling the opening and closing of the channel.

In some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 includes a gate electrode 121 and a gate sidewall 122, and the gate sidewall 122 is located on a sidewall of the gate electrode 121.

It should be noted that, in some embodiments of the present invention, in the step of forming the substrate, the gate structure 120 is a fully-surrounding gate structure as shown in fig. 9; the substrate further comprises: at least one channel layer 111, the at least one channel layer 111 being stacked on the substrate 110 in a direction perpendicular to a surface of the substrate 110, the at least one channel layer 111 having a gap with the substrate 110; the gate structure 120 is located on the at least one channel layer 111 and surrounds any one of the channel layers 111; the source drain region 130 is located in the at least one channel layer 111 at two sides of the gate structure 120 and contacts with a sidewall of any channel layer 111.

Source drain regions 130 are located on substrate 110 on both sides of gate structure 120.

In some embodiments of the present invention, the gate structure 120 is a fully-surrounding gate structure; the substrate further comprises: at least one channel layer 111, the gate structure 120 surrounding any of the channel layers 111; the source drain regions 130 are in contact with sidewalls of each of the channel layers 111.

Note that, in the gap between the at least one channel layer 111 and the substrate 110 and the gap between the adjacent channel layers 111, a sidewall (not shown) is disposed between the gate structure 120 and the source drain region 130 to isolate the gate structure 120 from the source drain region 130.

The first dielectric layer 140 is located between adjacent gate structures 120 to achieve electrical isolation between adjacent gate structures 120.

Specifically, the material of the first dielectric layer 140 includes silicon oxide. In other embodiments of the present invention, the material of the first dielectric layer 140 may be a low K dielectric material or an ultra low K dielectric material.

The capping layer 152 is used to serve as a self-aligned mask in a subsequent process, particularly in the process of forming the source-drain contact layer, and the capping layer 152 is used as the self-aligned mask, so that the process difficulty is effectively reduced, and the process window is enlarged.

In some embodiments of the present invention, the material of the first dielectric layer 140 includes silicon oxide; the material of the cap layer 152 comprises silicon nitride. The difference of the etching selectivity between the silicon nitride and the silicon oxide is larger, the material of the cover layer 152 is set to be silicon nitride, and the cover layer 152 is used as a self-aligned mask to form the source-drain contact layer, so that the difficulty of a forming process can be effectively reduced, the quality of forming the source-drain contact layer can be effectively improved, no extra material is introduced, and unnecessary process risks are not caused.

In some embodiments of the invention, the thickness of the cap layer 152 is atTo->Within the range. The thickness of the cap layer 152 is related to the depth of the mask recess 151, and if the cap layer 152 is too thick, the maskThe film groove 151 has too large a depth, and the remaining gate structure 120 has too small a thickness, which may adversely affect the performance of the gate structure 120; the thickness of the cap layer 152, if too small, may affect the implementation of its self-aligned masking function.

As shown in fig. 18, in some embodiments of the present invention, a gate sidewall 122 is further disposed on the sidewall of the cap layer 152, that is, the gate sidewall 122 further extends onto the sidewall of the cap layer 152, and the top of the gate sidewall 122 is flush with the top of the cap layer 152.

The source-drain contact layer 167 is used to electrically connect the source-drain region 130 to an external circuit.

In some embodiments of the present invention, the source-drain contact layer 167 includes: a conductive layer 167a; a contact layer 167b, the contact layer 167b being located on the side wall and bottom of the conductive layer.

In some embodiments of the present invention, the material of the source-drain contact layer 167 comprises cobalt. Specifically, in the source-drain contact layer 167, the material of the conductive layer 167a is cobalt. The material of the source-drain contact layer 167 is cobalt, so that the stability and the electrical performance of the source-drain contact layer 167 can be effectively improved, and the overall performance of the source-drain contact layer 167 can be effectively improved.

In some embodiments of the present invention, the semiconductor structure further comprises: a gate contact layer 174 and a source-drain connection layer 173, the gate contact layer 174 being on the gate structure 120 and electrically connected to the gate structure 120, the source-drain connection layer 173 being over the source-drain contact layer 167 and electrically connected to the source-drain contact layer 167.

The gate contact layer 174 is used to electrically connect the gate structure 120 to an external circuit, and the source-drain connection layer 173 is used to electrically connect the source-drain region 130 to the external circuit through the source-drain contact layer 167.

In some embodiments of the present invention, the material of at least one of the gate contact layer 174 and the source-drain connection layer 173 includes: tungsten. The materials of the gate contact layer 174 and the source-drain connection layer 173 are tungsten, so that the stability and performance of connection between the gate structure 120 and the source-drain contact layer 167 and an external circuit can be effectively ensured.

In some embodiments of the present invention, the source-drain contact layer 167 includes: a conductive layer 167a and a contact layer 167b; the contact layer 167b also extends to the side wall of the source-drain connection layer 173; in addition, in some embodiments of the present invention, the gate sidewall 122 is further disposed on the sidewall of the cap layer 152; a contact layer 167b and a gate sidewall 122 are disposed between the cap layer 152 and the source-drain connection layer 173.

In summary, forming a mask groove by etching the gate structure; forming a cover layer in the mask groove; and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer. In the process of forming the source-drain contact layer, the cover layer plays a role of a self-aligned mask, and the difficulty in forming the source-drain contact layer can be effectively reduced through the formation of the cover layer.

Furthermore, the material of the cap layer comprises silicon nitride, and the material of the first dielectric layer comprises silicon oxide. The silicon nitride and the silicon oxide have larger etching selectivity difference, and the source-drain contact layer is formed by taking the cover layer as a self-aligned mask, so that the difficulty of a forming process can be effectively reduced, and the quality of forming the source-drain contact layer can be effectively improved.

In addition, etching the source-drain contact layer, and forming a connection groove on the source-drain contact layer; and forming a source-drain connection layer in the connection groove, wherein the source-drain connection layer is electrically connected with the rest of the source-drain contact layer. The source-drain contact layer is made of cobalt, and the parasitic capacitance can be effectively controlled due to the reduction of the height of the source-drain contact layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

forming a substrate, the substrate comprising: a substrate; a gate structure located on the substrate; the source drain region is positioned on the substrate at two sides of the grid structure; the first dielectric layer is filled on the source-drain region between the adjacent gate structures, and the top of the first dielectric layer is flush with the top of the gate structures;

etching the grid structure, and forming a mask groove in the first dielectric layer;

forming a cover layer in the mask groove, wherein the top of the cover layer is flush with the first dielectric layer;

and etching the first dielectric layer by taking the cover layer as a mask to form a source-drain contact layer, wherein the source-drain contact layer is positioned on the source-drain region and is in contact with the source-drain region, and the top of the source-drain contact layer is not lower than the top of the cover layer.

2. The method of forming of claim 1, wherein the material of the cap layer comprises silicon nitride; the material of the first dielectric layer comprises silicon oxide.

3. The method of forming of claim 1, wherein the cap layer has a thickness ofTo->Within the range.

4. The method of forming as claimed in claim 1, further comprising:

after a cover layer is formed in the mask groove, a hard mask is formed on the cover layer and the first dielectric layer before a source-drain contact layer is formed by taking the cover layer as a mask;

and in the step of forming the source-drain contact layer, the cover layer and the hard mask are used as masks.

5. The method of forming of claim 4, wherein the step of forming the source drain contact layer comprises:

forming a contact opening in the first dielectric layer by taking the cover layer and the hard mask as masks, wherein the bottom of the contact opening exposes the source drain region;

and forming a source-drain contact layer in the contact opening.

6. The method of forming as claimed in claim 5, further comprising: forming a second dielectric layer on the cover layer after forming the cover layer and before forming a hard mask;

in the step of forming the source-drain contact layer, the top of the source-drain contact layer is flush with the top of the second dielectric layer.

7. The method of forming a substrate of claim 1, wherein in the step of forming a substrate, the gate structure comprises a gate electrode and a gate sidewall, the gate sidewall being located on the gate electrode sidewall;

and in the step of etching the gate structure, etching the gate electrode, and reducing the height of the gate electrode to form the mask groove.

8. The method of forming as claimed in claim 1, further comprising: after the source-drain contact layer is formed, a gate contact layer and a source-drain connection layer are formed, wherein the gate contact layer is positioned on the gate structure and is electrically connected with the gate structure, and the source-drain connection layer is positioned above the source-drain contact layer and is electrically connected with the source-drain contact layer.

9. The method of forming of claim 7, wherein the step of forming the gate contact layer and the source drain connection layer comprises:

forming a gate opening penetrating through the cover layer, wherein the bottom of the gate opening exposes the gate structure;

and forming a gate contact layer positioned in the gate opening and a source-drain connection layer positioned on the source-drain contact layer.

10. The method of forming as claimed in claim 8, further comprising: etching the source-drain contact layer before forming a gate opening penetrating through the cover layer, and forming a connecting groove on the source-drain contact layer;

in the step of forming the gate contact layer positioned in the gate opening and the source-drain connection layer positioned on the source-drain contact layer, the source-drain connection layer is formed in the connection groove and is electrically connected with the rest of the source-drain contact layer.

11. The method of forming of claim 10, wherein in the step of forming a source drain contact layer, the source drain contact layer comprises: a conductive layer; a contact layer located on the side wall and the bottom of the conductive layer;

and etching the conductive layer to reduce the height of the conductive layer in the step of etching the source-drain contact layer.

12. The method of forming of claim 8, wherein the material of at least one of the gate contact layer and the source drain connection layer comprises: tungsten.

13. The method of forming of claim 1, wherein the material of the source drain contact layer comprises cobalt.

14. The method of forming of claim 1, wherein in the step of forming a substrate, the gate structure is a fully-surrounding gate structure; the substrate further comprises: at least one channel layer stacked on the substrate in a direction perpendicular to the surface of the substrate with a gap therebetween; the gate structure is positioned on the at least one channel layer and surrounds any channel layer; the source drain region is positioned in the at least one channel layer at two sides of the gate structure and is contacted with the side wall of any channel layer.

15. A semiconductor structure formed by the method of forming of any of claims 1 to 14, comprising:

a substrate, the substrate comprising: a substrate; a gate structure located on the substrate; the source drain region is positioned on the substrate at two sides of the grid structure;

a cap layer over the gate structure;

the source-drain contact layer is positioned on the source-drain region and is in contact with the source-drain region, and the top of the source-drain contact layer is not lower than the top of the cover layer.

16. The semiconductor structure of claim 15, wherein the material of the cap layer comprises silicon nitride.

17. The semiconductor structure of claim 15, wherein a thickness of the cap layer is atTo->Within the range.

18. The semiconductor structure of claim 15, wherein the gate structure comprises a gate electrode and a gate sidewall, the gate sidewall being located on the gate electrode sidewall; the grid side wall also extends to the side wall of the cover layer.

19. The semiconductor structure of claim 15, further comprising: the gate contact layer is positioned on the gate structure and is electrically connected with the gate structure, and the source-drain connection layer is positioned above the source-drain contact layer and is electrically connected with the source-drain contact layer.

20. The semiconductor structure of claim 19, wherein the source-drain contact layer comprises: a conductive layer; a contact layer located on the side wall and the bottom of the conductive layer; the contact layer also extends between the cap layer and the source drain connection layer.