CN114864691A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114864691A
CN114864691A CN202110076772.3A CN202110076772A CN114864691A CN 114864691 A CN114864691 A CN 114864691A CN 202110076772 A CN202110076772 A CN 202110076772A CN 114864691 A CN114864691 A CN 114864691A
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China
Prior art keywords
side wall
layer
forming
channel
gate
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CN202110076772.3A
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Chinese (zh)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110076772.3A priority Critical patent/CN114864691A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the semiconductor structure comprises: a substrate; the fin structure is positioned on the substrate and comprises a plurality of channel layers arranged at intervals along the normal direction of the surface of the substrate, and channels are arranged between the adjacent channel layers; the inner side wall is positioned between the adjacent channel layers on the two sides of the channel; the gate structure stretches across the fin structure and is filled in the channel; the first side wall is positioned on the surface of the side wall of the grid structure; the initial cavity is positioned on two sides of the first side wall, the inner side wall and two sides of the channel, and part of the surface of the channel layer is exposed out of the initial cavity; and the grid covering layer covers the top surface of the grid structure, fills part of the initial cavity and surrounds a hole in the initial cavity. The semiconductor structure provided by the embodiment of the invention is beneficial to reducing the parasitic capacitance of a semiconductor device, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a semiconductor structure and a forming method thereof.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is also being shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect.
However, in a fully-enclosed gate transistor, there are serious parasitic capacitances between a gate electrode and plugs (contact-plugs) above a source-drain region and between the gate electrode and the source-drain region, the contact plugs on the gate electrode and the source-drain region are isolated by a gate sidewall, the gate electrode and the source-drain region are isolated by an inner sidewall, the sidewall is generally made of silicon nitride, silicon oxide, or the like, and the parasitic capacitances between the gate electrode and the source-drain region and between the contact plugs are relatively large due to the relatively large dielectric constants of the materials such as silicon nitride, silicon oxide, or the like, so that the delay and the switching power consumption of the device are increased.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor structure and a forming method thereof, wherein air side walls are formed between a grid structure and contact plugs on a source-drain doping layer and between the grid structure and the source-drain doping layer, so that parasitic capacitance is reduced, and the performance of the formed semiconductor structure is improved.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the fin structure is positioned on the substrate and comprises a plurality of channel layers arranged at intervals along the normal direction of the surface of the substrate, and channels are arranged between the adjacent channel layers; the inner side wall is positioned between the adjacent channel layers on the two sides of the channel; the gate structure stretches across the fin structure and is filled in the channel; the first side wall is positioned on the surface of the side wall of the grid structure and positioned on the fin part structure; the initial cavity is positioned on two sides of the first side wall, the inner side wall and two sides of the channel, and part of the surface of the channel layer is exposed out of the initial cavity; and the grid covering layer covers the top surface of the grid structure, fills part of the initial cavity and surrounds a hole in the initial cavity.
Optionally, the method further includes: and the source-drain doping layers are positioned in the fin part structures at two sides of the grid structure.
Optionally, the method further includes: and the dielectric layer is positioned on the substrate and also covers the source-drain doping layer.
Optionally, the method further includes: and the contact plug is positioned in the medium layer and is electrically connected with the source drain doping layer.
Optionally, the gate structure includes a gate oxide layer surrounding the channel layer and a gate layer covering the gate oxide layer.
Correspondingly, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate; forming a fin structure on the substrate, wherein the fin structure comprises a sacrificial layer and a channel layer positioned on the surface of the sacrificial layer; forming a pseudo gate structure crossing the fin structure; forming a first side wall and a second side wall on the surface of the side wall of the dummy gate structure; etching part of the sacrificial layer to form a first groove between the adjacent channel layers; forming an inner side wall in the first groove, wherein the side wall surface of the inner side wall is flush with the side wall surface of the channel layer; removing the pseudo gate structure to form a gate opening; removing the sacrificial layer to form a channel between the adjacent channel layers; forming a gate structure in the gate opening and the channel; removing the second side wall and part of the inner side wall, and forming initial cavities on two sides of the first side wall and on two sides of the rest inner side wall and the channel, wherein the initial cavities expose part of the surface of the channel layer; and forming a grid covering layer on the top surface of the grid structure, wherein the grid covering layer also fills part of the initial cavity and surrounds a hole in the initial cavity.
Optionally, the channel layer and the sacrificial layer are made of different materials; the material of the channel layer comprises silicon or silicon germanium; the material of the sacrificial layer comprises silicon or silicon germanium.
Optionally, the material of the first side wall is different from the material of the second side wall; the first side wall is made of silicon carbonitride, silicon nitride, silicon oxycarbide, silicon carbonitride, aluminum oxide or titanium dioxide; the material of the second side wall comprises silicon nitride or silicon oxycarbide.
Optionally, the material of the inner sidewall includes a low-k dielectric material, an ultra-low-k dielectric material, silicon nitride, or silicon oxynitride.
Optionally, before etching part of the sacrificial layer, the method further includes: and etching the fin part structure by using the second side wall as a mask, and forming source and drain openings in the fin part structure at two sides of the pseudo gate structure.
Optionally, after the inner side wall is formed, a source-drain doping layer is formed in the source-drain opening.
Optionally, before removing the dummy gate structure, the method further includes: and forming a dielectric layer on the substrate, wherein the dielectric layer covers the source-drain doping layer and exposes the top surfaces of the pseudo gate structure, the first side wall and the second side wall.
Optionally, after forming the gate structure, before removing the second sidewall and part of the inner sidewall, the method further includes: and forming an initial covering layer on the gate structure, the first side wall and the second side wall, wherein the top surface of the initial covering layer is flush with the top surface of the dielectric layer.
Optionally, the method for forming the initial capping layer includes: etching part of the gate structure, the first side wall and the second side wall to enable the top surfaces of the gate structure, the first side wall and the second side wall to be lower than the top surface of the dielectric layer; and forming an initial covering layer on the grid structure, the first side wall and the second side wall.
Optionally, after forming the initial capping layer, the method further includes: and forming a contact plug on the source-drain doping layer, wherein the contact plug is also positioned in the medium layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the semiconductor structure provided by the embodiment of the invention, in the semiconductor structure fully surrounding the gate, holes are formed among the gate structure, the source-drain doping layer and the contact plugs on the gate structure and the source-drain doping layer, and the holes are used as the air side walls.
According to the method for forming the semiconductor structure, after the pseudo gate structure is formed, the first side wall and the second side wall are formed on the side wall of the pseudo gate structure, wherein the first side wall protects the gate structure from being damaged in the subsequent process, and the second side wall reserves a space for forming an initial cavity; then removing the second side wall and the inner side wall with partial thickness, and forming initial cavities at two sides of the grid structure and two sides of the inner side wall, wherein the initial cavities provide space for the subsequent formation of holes; when the grid covering layer is formed on the grid structure, the grid covering layer also fills part of the initial cavity, holes are formed in the initial cavity in a surrounding mode, the holes are used as air side walls, the air side walls are formed on two sides of the grid structure and two sides of the inner side wall at the same time, the parasitic capacitance of a formed semiconductor device is favorably reduced, the delay and the switching power consumption are reduced, and therefore the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
It can be known from the background art that a serious parasitic capacitance exists between a Gate structure and a source-drain doping layer of a Gate-all-around (GAA) transistor and between the Gate structure and a contact plug on the source-drain doping layer, and at present, in a Gate-all-around (GAA) transistor, an inner sidewall is formed between the Gate structure and the source-drain doping layer for isolation, and a Gate sidewall is formed between the Gate structure and the contact plug on the source-drain doping layer for isolation.
In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein before a gate structure is formed, a first sidewall and a second sidewall are formed on two sides of a dummy gate structure, after the gate structure is formed, the second sidewall and a part of inner sidewalls are removed by etching, initial cavities are formed in adjacent channel layers on two sides of the first sidewall and two sides of the remaining inner sidewalls, when a gate capping layer is formed on the top of the gate structure, the initial cavities are sealed by the gate capping layer at an opening position of the initial cavities first due to poor hole filling capability of the gate capping layer in the initial cavities, so that holes are enclosed in the initial cavities, the holes serve as air sidewalls, and parasitic capacitances between the gate structure and a source-drain doping layer and a contact plug are significantly reduced due to a small dielectric constant of air, the delay of the device is reduced, and the response speed and the switching power consumption of the switch state are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 1, a substrate 100 is provided.
The material of the substrate 100 is a semiconductor material. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the multicomponent semiconductor material of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional structure perpendicular to an extending direction of a fin structure, and fig. 2 is a schematic cross-sectional structure along the extending direction of the fin structure, a fin structure 200 is formed on the substrate 100, and the fin structure 200 includes a sacrificial layer 210 and a channel layer 220 on a surface of the sacrificial layer 210.
In this embodiment, the method of forming the fin structure 200 includes: forming a fin material film (not shown) on the substrate 100, the fin material film including a sacrificial material film (not shown) disposed at an interval in a normal direction of a surface of the substrate 100 and a channel material film (not shown) on a surface of the sacrificial material film; the fin material film and a portion of the thickness of the substrate 100 are patterned to form a fin structure 200, such that the sacrificial material film forms a sacrificial layer 210, and the channel material film forms a channel layer 220.
It should be noted that the bottom of the fin structure 200 further includes a partially patterned substrate 100.
The sacrificial layer 210 and the channel layer 220 are made of different materials, so that etching damage to the channel layer 220 during subsequent removal of the sacrificial layer 210 can be avoided. Specifically, the material of the sacrificial layer 210 is silicon or silicon germanium; the material of the channel layer 220 is silicon or silicon germanium.
With continuing reference to fig. 1 and 2, further comprising: an isolation structure 110 is formed on the substrate 100, and the isolation structure 110 covers the sidewall of the substrate 100 patterned at the bottom of the fin structure 200.
In this embodiment, the isolation structure 110 is made of silicon oxide.
The method of forming the isolation structure 110 includes: forming an initial isolation film (not shown) on the substrate, the initial isolation film covering sidewalls of the fin structure 200; the initial isolation film is etched back to form the isolation structure 110.
In this embodiment, the process of forming the initial isolation film is a fluid chemical vapor deposition process. The initial isolation film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the initial isolation film is better.
Referring to fig. 3, a dummy gate structure 120 crossing the fin structure 200 is formed on the substrate 100, and the dummy gate structure 120 covers a portion of the top surface and the sidewall surface of the fin structure 200.
Specifically, in the present embodiment, the dummy gate structure 120 is located on the surface of the isolation structure 110 and crosses the fin structure 200.
In this embodiment, the method for forming the dummy gate structure 120 includes: forming a dummy gate dielectric film (not shown) on the substrate 100 to cover the fin structure 200; forming a dummy gate film (not shown) on the dummy gate dielectric film; and etching the pseudo gate film and the pseudo gate dielectric film until the top surface of the fin structure 200 is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer 121, the pseudo gate film forms a pseudo gate layer 122, and the pseudo gate structure 120 is formed.
In this embodiment, a dummy gate capping layer 123 is further formed on the top surface of the dummy gate structure 120.
In this embodiment, the dummy gate dielectric layer 121 is made of silicon oxide; the material of the dummy gate layer 122 is polysilicon.
In this embodiment, the dummy gate cap layer 123 is made of silicon nitride.
After the dummy gate structure 120 is formed, a first sidewall 130 and a second sidewall 140 located on the sidewall of the first sidewall 130 are formed on the sidewall of the dummy gate structure 120.
In this embodiment, a first sidewall 130 and a second sidewall 140 located on the sidewall surface of the first sidewall 130 are specifically formed on the sidewall surfaces of the dummy gate structure 120 and the dummy gate capping layer 123.
The first side wall 130 and the second side wall 140 are made of different materials, the second side wall 140 reserves a space for a subsequent initial cavity, when the second side wall 140 is removed by subsequent etching, the first side wall 130 and the second side wall 140 have etching selection ratios, so that the first side wall 130 can be prevented from being damaged by etching, the first side wall 130 can protect the side wall of a subsequently formed gate structure, and the formed gate structure is prevented from appearance defects and affecting the electrical performance of the semiconductor structure.
In this embodiment, the first side wall 130 is made of silicon carbonitride; in other embodiments, the material of the first sidewall 130 may also be silicon nitride, silicon oxycarbide, silicon carbonitride, aluminum oxide, or titanium dioxide.
In this embodiment, the second sidewall spacers 140 are made of silicon nitride; in other embodiments, the material of the second sidewall 140 may also be silicon oxycarbide.
The thickness of the second sidewall 140 in the extending direction of the fin structure 200 is 3-10 nm. If the thickness of the second side wall 140 is less than 3 nm, the thickness of the initial cavity formed subsequently is small, so that the finally formed hole is small, and the effects of reducing the dielectric constant and reducing the parasitic capacitance are small; if the thickness of the second sidewall 140 is greater than 10 nm, which may result in a larger thickness of the initial cavity formed subsequently, when the gate capping layer is formed, the filling effect of the gate capping layer in the initial cavity is better, and a hole serving as an air sidewall cannot be formed.
Referring to fig. 4, the fin structure 200 is etched by using the second sidewall 140 as a mask, and source-drain openings 201 are formed in the fin structure 200 on both sides of the dummy gate structure 120.
The source-drain opening 201 provides a space for forming a source-drain doping layer subsequently.
In this embodiment, the process of etching the fin structure 200 is anisotropic dry etching. The anisotropic dry etching process is beneficial to forming the source-drain opening 201 with good appearance, and avoids etching damage to the fin structure at the bottom of the pseudo-gate structure, thereby being beneficial to the performance of the formed semiconductor structure.
After the source-drain opening 201 is formed, the sidewalls of the source-drain opening 201 expose the sidewalls of the sacrificial layer 210 and the channel layer 220, a portion of the sacrificial layer 210 is etched, and a first groove 202 is formed between adjacent channel layers 220.
In this embodiment, the first recess 202 is also located between the channel layer 220 and the substrate 100.
The first groove 202 provides a space for forming an inner sidewall later.
In this embodiment, the process of removing a portion of the sacrificial layer 210 is a wet etching process; the wet etching solution has a good selection ratio of silicon to silicon germanium, and can ensure that the shape of silicon is not influenced while the silicon germanium is removed. In this embodiment, the wet etching solution used is: hydrogen chloride gas with the volume percentage of 20-90 percent.
Referring to fig. 5, an inner sidewall 2021 is formed in the first recess 202 (see fig. 4), and a sidewall surface of the inner sidewall 2021 is flush with a sidewall surface of the channel layer 220.
In this embodiment, the inner sidewall 2021 is made of silicon nitride; in other embodiments, the material of the inner sidewall 2021 may also be a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), or silicon oxynitride.
In this embodiment, the method for forming the inner sidewall 2021 includes: forming an inner sidewall film (not shown) on the surfaces of the source-drain opening 201, the first groove 202, the substrate 100 and the dummy gate structure 120; the inner sidewall film is etched until the sidewall surface of the channel layer 120 is exposed, and an inner sidewall 2021 is formed in the first groove 202.
In this embodiment, the inner sidewall 2021 is used to isolate a source-drain doped layer formed subsequently and a gate structure formed subsequently.
In this embodiment, the inner sidewall 2021 also provides support for the channel layer 220 when the sacrificial layer 210 is subsequently removed.
Referring to fig. 6, a source-drain doped layer 300 is formed in the source-drain opening 201.
In this embodiment, the source-drain doping layer 300 is formed by an epitaxial growth process.
The source-drain doping layer 300 has doping ions therein. In this embodiment, an in-situ doping process is used to dope ions.
When the semiconductor device is a P-type device, the source-drain doping layer 300 is made of the following materials: silicon, germanium, or silicon germanium; the doped ions are P-type ions including boron ions and BF 2- Ions or indium ions; when the semiconductor device is an N-type device, the source-drain doping layer 300 is made of the following materials: silicon, gallium arsenide, or indium gallium arsenide; the doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
Referring to fig. 7, after forming the source-drain doping layer 300, a dielectric layer 400 is formed on the substrate 100, and the dielectric layer 400 covers the source-drain doping layer 300 and exposes the top surfaces of the dummy gate structure 120, the first sidewall 130, and the second sidewall 140.
In this embodiment, the dielectric layer 400 is made of silicon oxide; in other embodiments, the material of the dielectric layer 400 may also be silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the method for forming the dielectric layer 500 includes: forming an initial dielectric film (not shown) on the substrate 100, wherein the initial dielectric film covers the surface of the substrate 100, the surfaces of the source-drain doping layers 300, the top surfaces of the first side walls 130, the side walls and the top surfaces of the second side walls 140, and the top surface of the dummy gate capping layer 123; and performing chemical mechanical polishing on the initial dielectric film, and simultaneously removing the dummy gate covering layer 123 by polishing until the top surfaces of the dummy gate structure 120, the first side wall 130 and the second side wall 140 are exposed to form a dielectric layer 400.
The process for forming the initial dielectric film is a deposition process, such as a plasma chemical vapor deposition process or a fluid chemical vapor deposition process.
Referring to fig. 8, after forming the dielectric layer 400, the dummy gate structure 120 is removed to form a gate opening 410, and the gate opening 410 exposes the surface of the uppermost channel layer 220.
In this embodiment, the dummy gate dielectric layer 121 and the dummy gate layer 122 on the surface of the dummy gate dielectric layer 121 are removed.
With continued reference to fig. 8, the sacrificial layer 210 is removed, forming channels 420 between adjacent ones of the channel layers 220.
In this embodiment, the channel 420 is also located between the channel layer 220 and the substrate 100.
The method for removing the sacrificial layer 210 includes a dry etching process or a wet etching process. In this embodiment, the sacrificial layer 210 is removed by a wet etching process, and the wet etching process has a good etching selectivity ratio for the sacrificial layer 210 and the channel layer 220, so as to reduce etching damage to the channel layer 220, and make the topography of the channel layer 220 good.
In this embodiment, the etching solution used in the wet etching process is a hydrogen chloride solution.
Referring to fig. 9, a gate structure 500 is formed within the gate opening 410 and the channel 420, the gate structure 500 surrounding each of the channel layers 220.
The gate structure 500 surrounds the channel layer 220 on four sides, so that the control capability of the channel is enhanced, and the short channel effect can be better suppressed.
In this embodiment, the gate structure 500 includes: a gate oxide layer 510, wherein the gate oxide layer 510 surrounds each of the channel layers 220; and a gate layer 520 covering the gate oxide layer 510.
In this embodiment, the gate oxide layer 510 is made of a high-k dielectric material (the dielectric coefficient is greater than 3.9); the high-k dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.
The material of the gate layer 520 is metal, and the metal material includes one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.
Referring to fig. 10, after the gate structure 500 is formed, an initial capping layer 530 is formed on the gate structure 500, the first sidewalls 130 and the second sidewalls 140, and a top surface of the initial capping layer 530 is flush with a top surface of the dielectric layer 400.
In this embodiment, the initial capping layer 530 is made of silicon nitride; in other embodiments, the material of the initial cap layer 530 may also be silicon carbide or silicon carbonitride.
In this embodiment, the material of the initial capping layer 530 is the same as that of the second sidewall 140, so that the initial capping layer 530 and the second sidewall 140 can be removed at the same time.
In this embodiment, the method for forming the initial capping layer 530 includes: etching back a part of the gate structure 500, the first sidewall spacer 130 and the second sidewall spacer 140, so that the top surfaces of the gate structure 500, the first sidewall spacer 130 and the second sidewall spacer 140 are lower than the top surface of the dielectric layer 400; an initial capping layer 530 is formed on the surfaces of the gate structure 500, the first sidewall spacers 130, and the second sidewall spacers 140.
In this embodiment, the initial covering layer 530 is used to protect the gate structure 500, and prevent the gate structure 500 from being damaged by etching when a contact plug on the source-drain doping layer 300 is formed subsequently.
After the initial capping layer 530 is formed, a contact plug 310 is formed on the source-drain doping layer 300, and the contact plug 310 is located in the dielectric layer 400 and electrically connected to the source-drain doping layer 300.
In this embodiment, the method for forming the contact plug 310 includes: etching the dielectric layer 400 until the top surface of the source-drain doping layer 300 is exposed, and forming a contact hole (not shown) in the dielectric layer 400; the contact hole is filled with a metal layer to form a contact plug 310.
Referring to fig. 11, after the contact plug 310 is formed, the second sidewall 140 and a portion of the inner sidewall 2021 are removed, an initial cavity 600 is formed on two sides of the first sidewall 130 and two sides of the remaining inner sidewall 2021 and the channel 420, and a portion of the surface of the channel layer 220 is exposed from the initial cavity 600.
In this embodiment, the initial cavity 600 also exposes a portion of the surface of the substrate 100.
In this embodiment, removing the second sidewall 140 and part of the inner sidewall 2021 further includes: the initial capping layer 530 is removed to expose the top surface of the gate structure 500.
The method for removing the second sidewall 140, a portion of the inner sidewall 2021 and the initial cap layer 530 includes a wet etching process or a hybrid process of wet etching and dry etching.
In this embodiment, the method for removing the second sidewall 140, part of the inner sidewall 2021 and the initial cap layer 530 is a mixed process of wet etching and dry etching, wherein the etching solution of the wet etching process includes a hot phosphoric acid solution, and the etching gas of the dry etching process includes C x H y F z And gas, wherein x, y and z are natural numbers which are more than or equal to 1.
In this embodiment, the mixed process of the wet etching and the dry etching has an etching selection ratio for the first sidewall 130, the second sidewall 140, the inner sidewall 2021, and the initial capping layer 530, so that when the second sidewall 140, a part of the inner sidewall 2021, and the initial capping layer 530 are removed, the etching damage to the first sidewall 130 is small, so as to protect the gate oxide layer 510 of the gate structure 500 covered by the first sidewall 130 and prevent the gate oxide layer 510 from being damaged by etching.
In this embodiment, the reason for etching the portion of the inner sidewall 2021 is that the remaining portion of the inner sidewall 2021 can prevent the gate oxide layer 510 in the channel 420 from being damaged by etching due to over-etching.
In this embodiment, the initial cavity 600 provides a space for forming an air sidewall later.
Referring to fig. 12, a gate capping layer 700 is formed on the top surface of the gate structure 500, and the gate capping layer 700 further fills a portion of the initial cavity 600 (refer to fig. 11), and a hole 610 is defined in the initial cavity 600.
In this embodiment, the gate capping layer 700 is made of silicon nitride; in other embodiments, the material of the gate capping layer 700 may also be silicon oxycarbide or SiOCH.
In this embodiment, the process of forming the gate capping layer 700 is a chemical vapor deposition process.
In this embodiment, since the width of the initial cavity 600 is small, the hole filling capability of the gate capping layer 700 in the initial cavity 600 is poor, so that under the condition that the initial cavity 600 is not filled with the gate capping layer 700, the initial cavity 600 is sealed by the gate capping layer 700 at the opening position of the initial cavity 600, so as to enclose a hole 610 in the initial cavity 600, and the hole 610 serves as an air side wall, because the dielectric constant of air is small, the parasitic capacitance between the gate structure 500 and the source-drain doping layer 300 and the contact plug 310 is significantly reduced, the delay of a semiconductor device is reduced, and the response speed and the switching power consumption of the switching state are improved.
Correspondingly, the embodiment of the invention also provides a semiconductor structure.
Referring to fig. 12, the semiconductor structure includes: a substrate 100; a fin structure 200 located on the substrate 100, wherein the fin structure 200 includes a plurality of channel layers 220 arranged at intervals along a normal direction of a surface of the substrate 100, and channels 420 (refer to fig. 8) are located between adjacent channel layers 220; inner sidewalls 2021 between adjacent channel layers 220 on both sides of the channel 420; a gate structure 500 spanning the fin structure 200 and filling the channel 420; a first sidewall 130 on a sidewall surface of the gate structure 500 and on the fin structure 200; an initial cavity 600 (refer to fig. 11) located at both sides of the first sidewall 130 and both sides of the inner sidewall 2021 and the channel 420, the initial cavity 600 exposing a portion of the surface of the channel layer 220; a gate capping layer 700 covering the top surface of the gate structure 500, wherein the gate capping layer 700 further fills a portion of the initial cavity 600, and a hole 610 is defined in the initial cavity 600.
In this embodiment, the fin structure 200 further includes a portion of the substrate 100 with a bottom patterned.
In this embodiment, the material of the channel layer 220 is silicon; in other embodiments, the material of the channel layer 220 may also be silicon germanium.
In this embodiment, the gate structure 500 includes: a gate oxide layer 510, wherein the gate oxide layer 510 surrounds each of the channel layers 220; and a gate layer 520 covering the gate oxide layer 510.
In this embodiment, the method further includes: and the source-drain doping layers 300 are positioned in the fin structure 200 at two sides of the gate structure 500.
In this embodiment, the method further includes: and the dielectric layer 400 is positioned on the substrate 100, and the dielectric layer 400 also covers the source-drain doping layer 300.
In this embodiment, the method further includes: and the contact plug 310 is positioned in the dielectric layer 400 and electrically connected with the source-drain doping layer 300.
In this embodiment, the hole 610 serves as an air side wall, the air side wall is not only located between the contact plug 310 and the gate structure 500, but also located between the source-drain doping layer 300 and the gate structure 500, and since the dielectric constant of air is small, the parasitic capacitance between the gate structure 500 and the contact plug 310 and between the source-drain doping layer 300 is favorably reduced, and the performance of the semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A semiconductor structure, comprising:
a substrate;
the fin structure is positioned on the substrate and comprises a plurality of channel layers arranged at intervals along the normal direction of the surface of the substrate, and channels are arranged between the adjacent channel layers;
the inner side wall is positioned between the adjacent channel layers on the two sides of the channel;
the gate structure stretches across the fin structure and is filled in the channel;
the first side wall is positioned on the surface of the side wall of the grid structure and positioned on the fin part structure;
the initial cavity is positioned on two sides of the first side wall, the inner side wall and two sides of the channel, and part of the surface of the channel layer is exposed out of the initial cavity;
and the grid covering layer covers the top surface of the grid structure, fills part of the initial cavity and surrounds a hole in the initial cavity.
2. The semiconductor structure of claim 1, further comprising: and the source-drain doping layers are positioned in the fin part structures at two sides of the grid structure.
3. The semiconductor structure of claim 2, further comprising: and the dielectric layer is positioned on the substrate and also covers the source-drain doping layer.
4. The semiconductor structure of claim 3, further comprising: and the contact plug is positioned in the dielectric layer and is electrically connected with the source drain doping layer.
5. The semiconductor structure of claim 1, wherein the gate structure comprises a gate oxide layer surrounding the channel layer and a gate layer overlying the gate oxide layer.
6. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a fin structure on the substrate, wherein the fin structure comprises a sacrificial layer and a channel layer positioned on the surface of the sacrificial layer;
forming a pseudo gate structure crossing the fin structure;
forming a first side wall and a second side wall on the surface of the side wall of the dummy gate structure;
etching part of the sacrificial layer to form a first groove between the adjacent channel layers;
forming an inner side wall in the first groove, wherein the side wall surface of the inner side wall is flush with the side wall surface of the channel layer;
removing the pseudo gate structure to form a gate opening;
removing the sacrificial layer to form a channel between the adjacent channel layers;
forming a gate structure in the gate opening and the channel;
removing the second side wall and part of the inner side wall, and forming initial cavities on two sides of the first side wall and on two sides of the rest inner side wall and the channel, wherein the initial cavities expose part of the surface of the channel layer;
and forming a grid covering layer on the top surface of the grid structure, wherein the grid covering layer also fills part of the initial cavity and surrounds a hole in the initial cavity.
7. The method of forming a semiconductor structure according to claim 6, wherein a material of the channel layer and the sacrificial layer is different; the material of the channel layer comprises silicon or silicon germanium; the material of the sacrificial layer comprises silicon or silicon germanium.
8. The method for forming the semiconductor structure according to claim 6, wherein a material of the first side wall is different from a material of the second side wall; the first side wall is made of silicon carbonitride, silicon nitride, silicon oxycarbide, silicon carbonitride, aluminum oxide or titanium dioxide; the material of the second side wall comprises silicon nitride or silicon oxycarbide.
9. The method of claim 6, wherein the material of the inner sidewall spacers comprises a low-k dielectric material, an ultra-low-k dielectric material, silicon nitride, or silicon oxynitride.
10. The method of forming a semiconductor structure of claim 6, further comprising, prior to etching a portion of the sacrificial layer: and etching the fin part structure by using the second side wall as a mask, and forming source and drain openings in the fin part structure at two sides of the pseudo gate structure.
11. The method for forming the semiconductor structure according to claim 10, wherein a source-drain doping layer is formed in the source-drain opening after the inner sidewall is formed.
12. The method of forming a semiconductor structure of claim 11, further comprising, before removing the dummy gate structure: and forming a dielectric layer on the substrate, wherein the dielectric layer covers the source-drain doping layer and exposes the top surfaces of the pseudo gate structure, the first side wall and the second side wall.
13. The method of forming a semiconductor structure of claim 12, wherein after forming the gate structure and before removing the second sidewall and a portion of the inner sidewall, further comprising: and forming an initial covering layer on the gate structure, the first side wall and the second side wall, wherein the top surface of the initial covering layer is flush with the top surface of the dielectric layer.
14. The method of forming a semiconductor structure of claim 13, wherein forming the initial capping layer comprises: etching part of the gate structure, the first side wall and the second side wall to enable the top surfaces of the gate structure, the first side wall and the second side wall to be lower than the top surface of the dielectric layer; and forming an initial covering layer on the grid structure, the first side wall and the second side wall.
15. The method of forming a semiconductor structure of claim 13, further comprising, after forming the initial capping layer: and forming a contact plug on the source-drain doping layer, wherein the contact plug is also positioned in the medium layer.
CN202110076772.3A 2021-01-20 2021-01-20 Semiconductor structure and forming method thereof Pending CN114864691A (en)

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