CN113363154B - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN113363154B CN113363154B CN202010146892.1A CN202010146892A CN113363154B CN 113363154 B CN113363154 B CN 113363154B CN 202010146892 A CN202010146892 A CN 202010146892A CN 113363154 B CN113363154 B CN 113363154B
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- 238000000034 method Methods 0.000 title claims abstract description 124
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000008569 process Effects 0.000 claims description 67
- 239000000463 material Substances 0.000 claims description 66
- 238000002955 isolation Methods 0.000 claims description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 238000005530 etching Methods 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 238000010438 heat treatment Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- -1 boron ion Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method for forming a semiconductor structure includes: providing a substrate, wherein the substrate is provided with a fin structure; forming a pseudo gate structure crossing the fin structure on the substrate, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure; forming first grooves in fin structures on two sides of the pseudo gate structure; after forming the first groove, forming a first dielectric layer on the substrate, wherein the dummy gate structure is positioned in the first dielectric layer; removing the pseudo gate structure and the second fin portion layer covered by the pseudo gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin portion layers; forming a gate structure in the gate opening, wherein the gate structure surrounds each first fin part layer; removing the first dielectric layer after forming the gate structure to expose the first groove; and after the first dielectric layer is removed, forming a source-drain doping layer in the first groove. The semiconductor structure formed by the method has better performance.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
With the development of semiconductor technology, the control capability of conventional planar metal-oxide semiconductor field effect transistors on channel current becomes weak, resulting in serious leakage current. Fin field effect transistors (finfets) are an emerging multi-gate device that generally include a fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the fin, and source-drain doped regions in the fin on either side of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a fin field effect transistor of a gate-all-around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin field effect transistor of the gate-around structure is further increased.
However, the performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which improves the stress of a source-drain doped layer so as to improve the performance of the semiconductor structure.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer; forming a pseudo gate structure crossing the fin structure on the substrate, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure; forming first grooves in fin structures on two sides of the pseudo gate structure; after the first groove is formed, a first dielectric layer is formed on the substrate, and the pseudo gate structure is located in the first dielectric layer; removing the dummy gate structure and the second fin portion layer covered by the dummy gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin portion layers; forming a gate structure in the gate opening, wherein the gate structure surrounds each first fin part layer; removing the first dielectric layer after the grid structure is formed, and exposing the first groove; and after the first dielectric layer is removed, forming a source-drain doping layer in the first groove.
Optionally, the method for forming the first groove includes: and etching the fin portion structure by taking the pseudo gate structure as a mask until the substrate surface is exposed, and forming the first grooves in the fin portion structures at two sides of the pseudo gate structure.
Optionally, the method for forming the gate opening includes: removing the pseudo gate structure and forming an initial gate opening in the first dielectric layer; and removing the second fin part layer exposed by the initial gate opening, so that the initial gate opening forms the gate opening.
Optionally, the bottommost layer of the fin structure is a first fin layer; and before the dummy gate structure is formed, forming an isolation structure which covers part of the fin structure on the substrate, wherein the top surface of the isolation structure is lower than the top surface of the first fin layer at the bottommost layer.
Optionally, the method further comprises: after the first groove is formed and before the first dielectric layer is formed, removing part of the second fin portion layer exposed out of the side wall of the first groove, and forming a second groove between adjacent first fin portion layers; forming a first side wall film in the second groove, on the surface of the isolation structure and on the surface of the pseudo gate structure; and after the first side wall film is formed, forming a first dielectric layer on the substrate, wherein the first dielectric layer covers the surface of the first side wall film and the surface of the isolation structure.
Optionally, the method further comprises: after the first dielectric layer is removed and before the source-drain doped layer is formed, etching the first side wall film until the side wall surface and the substrate surface of the first fin portion layer are exposed, and forming a first side wall in the second groove; and after the first side wall is formed, forming a source-drain doped layer, wherein the source-drain doped layer covers the side wall surface of the first side wall and the side wall surface of the first fin part layer.
Optionally, the material of the first side wall film is different from the material of the first dielectric layer, and the material of the first side wall film is different from the material of the isolation structure; the material of the first dielectric layer comprises: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the first side wall film comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the isolation structure comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Optionally, the forming process of the first side wall film includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the method for forming the first dielectric layer includes: forming an initial dielectric film on the surface of the first side wall film, wherein the initial dielectric film covers the top surface and the side wall surface of the pseudo gate structure; and etching the initial dielectric film until the top surface of the pseudo gate structure is exposed, and forming the first dielectric layer on the substrate.
Optionally, a first etching process is used to remove the first dielectric layer, and the etching rate of the first etching process on the first dielectric layer is greater than that on the first side wall film.
Optionally, a second etching process is used to etch the first side wall film, and the etching rate of the second etching process on the first side wall film is greater than the etching rate on the isolation structure.
Optionally, the material of the first fin portion layer is different from the material of the second fin portion layer; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
Optionally, the dummy gate structure includes: the device comprises a dummy gate dielectric layer and a dummy gate layer positioned on the surface of the dummy gate dielectric layer; the method for forming the pseudo gate structure comprises the following steps: forming a pseudo gate dielectric layer film covering the fin structure on the substrate; forming a dummy gate film on the dummy gate dielectric film; and etching the dummy gate dielectric film and the dummy gate film until the top surface of the fin structure is exposed, so that the dummy gate dielectric film forms a dummy gate dielectric layer, the dummy gate film forms a dummy gate layer, and the dummy gate structure is formed.
Optionally, the dummy gate structure further includes: and the second side wall is positioned on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate layer.
Optionally, the gate structure includes: the semiconductor device comprises an interface layer, a gate dielectric layer positioned on the surface of the interface layer and a gate electrode layer positioned on the surface of the gate dielectric layer; the method for forming the gate structure comprises the following steps: forming an interface film on the surface of the gate opening and the surface of the first dielectric layer; forming a gate dielectric film on the surface of the interface film; forming a gate electrode film on the surface of the gate dielectric film, wherein the gate electrode film fills the gate opening; and flattening the gate electrode film, the gate dielectric film and the interfacial film to form the gate structure.
Optionally, the method further comprises: after forming the interface film and the gate dielectric film, performing heat treatment before forming the gate electrode film; the parameters of the heat treatment include: the heat treatment process comprises the following steps: spike annealing or laser annealing, wherein the temperature range of the heat treatment is 850-1200 ℃.
Optionally, the forming process of the source-drain doped layer includes: and (5) an epitaxial growth process.
Optionally, the method further comprises: forming a second dielectric layer on the substrate after forming the source-drain doped layer; and forming a first conductive structure and a second conductive structure in the second dielectric layer, wherein the first conductive structure is electrically connected with the grid structure, and the second conductive structure is electrically connected with the source-drain doped layer.
Optionally, the method further comprises: after the source-drain doped layer is formed, a contact resistance layer is formed on the surface of the source-drain doped layer before the second dielectric layer is formed; and after the contact resistance layer is formed, forming the second dielectric layer on the surface of the contact resistance layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, after the grid structure is formed, the first dielectric layer is removed, and the first groove is exposed; and forming a source-drain doping layer in the first groove. The formation of the source-drain doped layer occurs after the process of forming the gate structure, so that the high-temperature heat treatment process of forming the gate structure can be avoided, the influence on the material of the source-drain doped layer under the high-temperature condition is reduced, the source-drain doped layer is favorably ensured to have larger stress on a channel, the channel has higher carrier mobility, and the performance of the semiconductor structure is favorably improved.
Further, the first side wall film is etched, and the first side wall is formed in the second groove after the first dielectric layer is removed. Because the first side wall film is arranged in the second groove, on the surface of the isolation structure and on the surface of the pseudo gate structure, and because the materials of the first side wall film and the first dielectric layer are different, the first side wall film positioned on the surface of the isolation structure can play a role in protecting in the process of subsequently removing the first dielectric layer, and the isolation structure is prevented from being etched, so that the isolation structure is prevented from being influenced by a process, the isolation structure can play a good role in isolation, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-3 are schematic diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 15 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of existing semiconductor structures is poor.
The following describes the reason why the performance of the semiconductor structure is poor with reference to the drawings, and fig. 1 to 3 are schematic structural views of each step of a semiconductor structure forming method.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 is provided with a fin 110 and an isolation structure 101, the fin 110 includes a plurality of first fin layers 111 overlapped along a normal direction of a surface of the semiconductor substrate 100, and a second fin layer 112 located in two adjacent first fin layers, and the isolation structure 101 covers a part of sidewalls of the fin 110.
Referring to fig. 2, a dummy gate structure 120 is formed across the fin 110; with the dummy gate structure 120 as a mask, the fin portions 110 on both sides of the dummy gate structure 120 are removed, and a recess 121 is formed.
Referring to fig. 3, source and drain doped layers 130 are epitaxially formed in the grooves 121 on both sides of the dummy gate structure 120; after forming the source-drain doped layer 130, removing the dummy gate structure 120 and the second fin layer 112 to form a gate opening (not shown in the figure); a gate structure 150 is formed within the gate opening, the gate structure 150 also being located between adjacent first fin layers 111.
In the above method, the gate opening is used to form the gate structure 150. The gate opening is formed by removing the dummy gate structure 120 and the second fin layer 112 covered by the dummy gate structure 120, so that the gate structure 150 can surround the first fin layer 111, and the gate structure has an enhanced control capability of the channel.
However, after forming the source-drain doped layer 130, the gate opening is formed; the gate structure 150 is formed within the gate opening. The method for forming the gate structure 150 includes: forming an interface film (not shown) within the gate opening; forming a gate dielectric film (not shown) on the interface film surface; forming a gate electrode film (not shown) on the surface of the gate dielectric film, wherein the gate electrode film fills the gate opening; the gate electrode film, gate dielectric film and interfacial film are planarized, and a gate structure 150 is formed within the gate opening. In the process of forming the gate structure 150, high-temperature heat treatment is required, and the high-temperature heat treatment can repair defects of the gate dielectric film, so that the formed gate dielectric layer has fewer defects, and meanwhile, the interface film can be densified, thereby being beneficial to improving the reliability and the turn-on voltage of the semiconductor device. However, the high temperature heat treatment easily affects the material of the formed source-drain doped layer 130, resulting in a reduced stress of the source-drain doped layer 130 on the channel, affecting the carrier mobility in the channel, and making the performance of the formed semiconductor structure poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: after the first groove is formed, a first dielectric layer is formed on the substrate, and the gate structure is located in the first dielectric layer; removing the dummy gate structure and the second fin portion layer covered by the dummy gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin portion layers; forming a gate structure in the gate opening, wherein the gate structure surrounds each first fin part layer; removing the first dielectric layer after the grid structure is formed, and exposing the first groove; and after the first dielectric layer is removed, forming a source-drain doping layer in the first groove. The semiconductor structure formed by the method has better performance.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 15 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a fin structure thereon, where the fin structure includes a plurality of composite fin layers 210 overlapped along a normal direction of a substrate surface, and each composite fin layer 210 includes a second fin layer 212 and a first fin layer 211 located on the surface of the second fin layer.
The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The material of the first fin layer 211 is different from the material of the second fin layer 212; the material of the first fin layer 211 is monocrystalline silicon or monocrystalline germanium silicon; the material of the second fin layer 212 is monocrystalline silicon or monocrystalline silicon germanium.
In this embodiment, the material of the first fin layer 211 is monocrystalline silicon, and the material of the second fin layer 212 is monocrystalline germanium silicon. In other embodiments, the material of the first fin layer is monocrystalline silicon germanium, and the material of the second fin layer is monocrystalline silicon.
In this embodiment, the bottom layer of the fin structure is the first fin layer 211.
With continued reference to fig. 4, an isolation structure 201 is formed on the substrate 200 to cover a portion of the fin structure, and a top surface of the isolation structure 201 is lower than a top surface of the bottommost first fin layer 211.
The isolation structure 201 covers a portion of the bottommost first fin layer 111.
The method of forming the isolation structure 201 includes: forming an isolation structure film (not shown) covering the fin structure on the substrate 200; the isolation structure film is etched back to form the isolation structure 201.
The process of forming the isolation structure film is a deposition process, such as a fluid chemical vapor deposition process. The isolation structure film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the isolation structure film is better.
Referring to fig. 5, a dummy gate structure is formed on the substrate 200 across the fin structure, the dummy gate structure covering a portion of the top surface and the sidewall surface of the fin structure.
Specifically, in this embodiment, the dummy gate structure is located on the surface of the isolation structure 201 and spans the fin structure.
The method for forming the pseudo gate structure comprises the following steps: forming a pseudo gate dielectric layer film (not shown in the figure) covering the fin structure on the substrate 200; forming a dummy gate film (not shown) on the dummy gate dielectric film; and etching the dummy gate dielectric film and the dummy gate film until the top surface of the fin structure is exposed, so that the dummy gate dielectric film forms a dummy gate dielectric layer, the dummy gate film forms a dummy gate layer, and the dummy gate structure is formed.
The dummy gate structure includes: a dummy gate dielectric layer 202 crossing the fin structure and a dummy gate layer 220 located on the surface of the dummy gate dielectric layer 202.
The material of the dummy gate dielectric layer 202 is silicon oxide. The dummy gate layer 220 is made of polysilicon.
In this embodiment, the dummy gate structure further includes: and the second side wall 204 is positioned on the side wall surfaces of the dummy gate dielectric layer 202 and the dummy gate layer 220.
The method for forming the second side wall 204 includes: forming a second side wall material film (not in reality in the figure) on the fin structure surface, the side wall surface of the pseudo gate dielectric layer, the top surface of the pseudo gate layer and the side wall surface; and etching the second side wall material film until the top surface of the dummy gate layer 220 and the surface of the fin structure are exposed, forming a second side wall on the fin structure, wherein the second side wall is positioned on the side wall surfaces of the dummy gate dielectric layer 202 and the dummy gate layer 220.
The second sidewall 204 serves to protect the sidewall of the dummy gate layer 220 from morphology defects in the subsequently formed gate layer, which may affect the electrical performance of the semiconductor structure.
In this embodiment, the top surface of the dummy gate structure further has a dummy gate protection layer 203, and the dummy gate protection layer 203 serves as a planarization stop layer.
The material of the dummy gate protection layer 203 includes silicon oxide or silicon nitride.
Referring to fig. 6, a first recess 205 is formed in the fin structures on both sides of the dummy gate structure.
The first recess 205 provides space for the subsequent formation of source-drain doped layers.
The method for forming the first groove 205 includes: and etching the fin structure by taking the pseudo gate structure as a mask until the surface of the substrate 200 is exposed, and forming the first grooves 205 in the fin structures at two sides of the pseudo gate structure.
The process of removing the fin structures on both sides of the dummy gate structure is anisotropic dry etching. The anisotropic dry etching process is beneficial to forming the first groove 205 with good morphology, and avoids etching damage to the fin structure at the bottom of the pseudo gate structure, thereby being beneficial to the performance of the formed semiconductor structure.
Referring to fig. 7, a portion of the second fin layer 212 exposed from the sidewall of the first recess 205 is removed, and a second recess 206 is formed between adjacent first fin layers 211.
The second recess 206 is located between adjacent first fin layers 211.
The second groove 206 provides space for forming a second sidewall later.
The process of removing a portion of the second fin layer 212 is a wet etching process. The wet etching solution has a good selection ratio to silicon and silicon germanium, and can ensure that the morphology of the silicon is not influenced while the silicon germanium is removed. The wet etching solution used in this embodiment is: the volume percentage of the hydrogen chloride gas is 20-90%, and the temperature is 25-300 ℃.
In other embodiments, a portion of the second fin layer is not removed.
Referring to fig. 8, after the second recess 206 is formed, a first sidewall film 230 is formed in the second recess 206, on the surface of the isolation structure 201, and on the surface of the dummy gate structure.
The first sidewall film 230 provides a material layer for subsequent formation of the first sidewall.
The material of the first sidewall film 230 is different from the material of the isolation structure 201, so that etching damage to the isolation structure 201 is avoided and the isolation effect of the isolation structure 201 is ensured in the subsequent process of etching the first sidewall film 230 to form the first sidewall.
The materials of the first side wall film 230 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the materials of the isolation structure 201 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the first sidewall film 230 is silicon nitride, and the material of the isolation structure 201 is silicon oxide.
The forming process of the first sidewall film 230 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the first sidewall film 230 is also different from the material of the first dielectric layer formed later.
Referring to fig. 9, after the first sidewall film 230 is formed, a first dielectric layer 240 is formed on the substrate 200, and the dummy gate structure is located in the first dielectric layer 240.
The first dielectric layer 240 provides support for the subsequent formation of the gate opening to form a gate structure within the gate opening.
Note that, the dummy gate structure is located in the first dielectric layer 240, and the first dielectric layer 240 covers the surface of the sidewall of the dummy gate structure, so that the gate opening can be formed in the first dielectric layer 240 by removing the dummy gate structure subsequently.
In this embodiment, the first dielectric layer 240 covers the surface of the first sidewall film 230 and the surface of the isolation structure 201.
Specifically, the top surface of the first dielectric layer 240 is flush with the top surface of the dummy gate structure.
The forming method of the first dielectric layer 240 includes: forming an initial dielectric film (not shown in the figure) on the surface of the first side wall film 230, wherein the initial dielectric film covers the top surface and the side wall surface of the pseudo gate structure; the initial dielectric film is etched until the top surface of the dummy gate structure is exposed, and the first dielectric layer 240 is formed on the substrate 200.
The process of forming the initial dielectric film is a deposition process, such as a plasma chemical vapor deposition process or a fluid chemical vapor deposition process.
The process for etching the initial dielectric film comprises the following steps: chemical mechanical polishing process.
The material of the first dielectric layer 240 is different from the material of the first sidewall film 230.
The materials of the first dielectric layer 240 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
Because the first sidewall film 230 covers the sidewall surface and the top surface of the dummy gate structure, the first dielectric layer 240 covers the surface of the first sidewall film 230, so that the first dielectric layer 240 covers the sidewall surface of the dummy gate structure, thereby satisfying the requirement of forming a gate opening by removing the dummy gate structure later, and simultaneously, the first dielectric layer 240 provides support for forming the gate structure.
Referring to fig. 10, the dummy gate structure and the second fin layer 212 covered by the dummy gate structure are removed, and a gate opening 250 is formed in the first dielectric layer 240 and between adjacent first fin layers 211.
The gate opening 250 provides space for the subsequent formation of a gate structure.
The method for forming the gate opening 250 includes: removing the dummy gate structure and forming an initial gate opening (not shown) in the first dielectric layer 240; and removing the second fin portion layer 212 exposed by the initial gate opening, so that the gate opening 250 is formed by the initial gate opening.
In this embodiment, the second fin layer 212 exposed by the initial gate opening is removed by a dry etching process, and the etching selection ratio of the dry etching process to the second fin layer 212 to the etching selection ratio to the first fin layer 211 is 50-200, so that etching damage to the first fin layer 211 is reduced, and the appearance of the first fin layer 211 is better.
Referring to fig. 11, a gate structure 260 is formed in the gate opening 250, and the gate structure 260 surrounds each of the first fin layers 211.
Specifically, in this embodiment, the gate structure 260 is further located between adjacent first fin layers 211, so that the gate structure 260 can surround the first fin layers 211, and the control capability of the gate structure 260 on the channel is increased.
The gate structure 260 includes: an interface layer (not shown), a gate dielectric layer (not shown) on the surface of the interface layer, and a gate electrode layer (not shown) on the surface of the gate dielectric layer.
The method for forming the gate structure 260 includes: forming an interface film (not shown) on the surface of the gate opening 250 and the surface of the first dielectric layer 240; forming a gate dielectric film (not shown) on the interface film surface; forming a gate electrode film (not shown) on the surface of the gate dielectric film, wherein the gate electrode film fills the gate opening 250; and flattening the gate electrode film, the gate dielectric film and the interfacial film to form the gate structure.
In this embodiment, after the interface film and the gate dielectric film are formed, before the gate electrode film is formed, the method further includes: performing heat treatment; the parameters of the heat treatment include: the heat treatment process comprises the following steps: spike annealing or laser annealing, wherein the temperature range of the heat treatment is 850-1200 ℃.
The heat treatment has the following functions: on one hand, repairing the defects of the gate dielectric film so that the formed gate dielectric layer has fewer defects; on the other hand, the interface film can be densified, which is advantageous for improving the reliability of the interface of the first fin layer 211, and thus, the heat treatment is advantageous for improving the reliability and the turn-on voltage of the semiconductor device.
The material of the interface layer comprises silicon oxide. The process of forming the interfacial layer includes an oxidation process. The functions of the interface layer include: the surface of the first fin layer 211 exposed by the gate opening 250 is repaired.
In this embodiment, the gate dielectric layer is made of a high-k dielectric material (dielectric coefficient is greater than 3.9); the high-k dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.
The material of the gate electrode layer is metal, and the metal material comprises one or more of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.
In this embodiment, the top surface of the gate structure is further provided with a gate protection layer 261, where the gate protection layer 261 is used to protect the top surface of the gate structure, so as to prevent the gate structure from being affected by the subsequent process, so as to improve the performance of the formed semiconductor structure.
The materials of the gate protection layer 261 and the first dielectric layer 240 are different, and the materials of the gate protection layer 261 include: silicon oxide or silicon nitride.
In this embodiment, the material of the gate protection layer 261 is silicon nitride.
Referring to fig. 12, after the gate structure 260 is formed, the first dielectric layer 240 is removed to expose the first recess 205.
In this embodiment, the first dielectric layer 230 is removed, exposing the first sidewall film 230 on the bottom surface of the first recess 205.
By removing the first dielectric layer 240 after the gate structure 260 is formed, exposing the first recess 205, and then forming a source-drain doped layer in the first recess 205, the formation of the source-drain doped layer can be avoided after the process of forming the gate structure 260, thereby reducing the influence on the material of the source-drain doped layer under the high temperature condition, and being beneficial to ensuring that the source-drain doped layer has larger stress on a channel and that the channel has higher carrier mobility, thus being beneficial to improving the performance of the semiconductor structure.
The first dielectric layer 240 is removed by a first etching process, and the etching rate of the first dielectric layer 240 by the first etching process is greater than the etching rate of the first sidewall film 230. In this embodiment, the first etching process is a dry etching process, and the process parameters include: the etching gas comprises NH 3 、NF 3 And He, where NH 3 The flow rate of the water is 50 to 800 standard milliliters/minute, NF 3 The flow rate of the (C) is 30-300 standard milliliters/minute, the flow rate of the He is 500-3000 standard milliliters/minute, and the pressure is 2-30 Torr.
Because the material of the first dielectric layer 240 is different from the material of the first sidewall film 230, a larger etching selectivity ratio between the first dielectric layer 240 and the first sidewall film 230 can be satisfied. Meanwhile, the first sidewall film 230 is disposed in the second groove 206 (shown in fig. 7), on the surface of the isolation structure 201, and on the surface of the dummy gate structure, so that in the process of subsequently removing the first dielectric layer 240, the first sidewall film 230 can protect the isolation structure 201 disposed at the bottom of the first sidewall film 230, and avoid etching the isolation structure 201, thereby ensuring that the isolation structure 201 is not affected by the process, so that the isolation structure 201 can perform a better isolation function, and performance of the formed semiconductor structure is improved.
Referring to fig. 13, the first sidewall film 230 is etched until the sidewall surface of the first fin layer 211 and the surface of the substrate 200 are exposed, and a first sidewall 270 is formed in the second recess 206.
The first sidewall 270 serves to electrically isolate the gate structure 260 located in the gate opening 250 from the subsequently formed source/drain doped layer, thereby meeting the process requirements.
The method for etching the first sidewall film 230 includes: the first sidewall film 230 is etched with the dummy gate structure as a mask, and the first sidewall 270 is formed in the second groove 206, where the sidewall of the first sidewall 270 is flush with the sidewall of the second sidewall 204.
The second etching process is used to etch the first sidewall film 230, and the etching rate of the second etching process on the first sidewall film 230 is greater than the etching rate on the isolation structure 201. In this embodiment, the second etching process is a dry etching process, and the process parameters include: the etching gas used comprises CH 3 F、N 2 And O 2 Wherein CH is 3 F has a flow rate of 10-100 ml/min, NF 3 The flow rate of the catalyst is 50-500 standard milliliters/minute, O 2 The flow rate of (2) is 10 to 200 ml/min.
Referring to fig. 14, after the first dielectric layer 240 is removed, a source-drain doped layer 280 is formed in the first recess 205.
In this embodiment, after the first sidewall film 230 is etched to form the first sidewall 270, a source-drain doped layer 280 is formed in the first recess 205.
The process for forming the source-drain doped layer 280 includes: and (5) an epitaxial growth process.
The source/drain doped layer 280 has doped ions therein. In this embodiment, in the process of forming the source/drain doped layer 280, an in-situ doping process is used to dope ions.
When the semiconductor device is a P-type device, the materials of the source-drain doped layer 280 include: silicon, germanium or silicon germanium; the doped ion is P-type ion including boron ion and BF 2- Ions or indium ions; when the semiconductor device is an N-type device, the materials of the source-drain doped layer 280 include: silicon, gallium arsenide or indium gallium arsenide; the doping ions are N-type ions, including phosphorus ions or arsenic ions.
Referring to fig. 15, a contact resistor layer 281 is formed on the surface of the source/drain doped layer 280.
The contact resistance layer 281 is used to reduce the contact resistance between the source/drain doped layer 280 and the first conductive structure formed later, thereby improving the performance of the formed semiconductor structure.
The method for forming the contact resistance layer 281 includes: forming a metal layer (not shown) on the surface of the source/drain doped layer 280, the gate structure 260 and the surface of the isolation structure 201; annealing to react the metal layer with the surface of the source/drain doped layer 280 to form the contact resistor layer 281; after the contact resistance layer 281 is formed, the unreacted metal layer is removed.
The materials of the contact resistance layer 281 include: titanium silicon compound.
With continued reference to fig. 15, after forming the source/drain doped layer 280, a second dielectric layer 290 is formed on the substrate 200.
In this embodiment, after the contact resistance layer 281 is formed, a second dielectric layer 290 is formed on the surface of the contact resistance layer 281.
The second dielectric layer 290 is used to provide support for forming the first conductive structure and the second conductive structure.
The materials of the second dielectric layer 290 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the second dielectric layer 290 is silicon oxide.
With continued reference to fig. 15, a first conductive structure 291 and a second conductive structure 291 are formed in the second dielectric layer 290, the first conductive structure 291 is electrically connected to the gate structure 260, and the second conductive structure 292 is electrically connected to the source-drain doped layer 280.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer;
forming a pseudo gate structure crossing the fin structure on the substrate, wherein the pseudo gate structure covers part of the top surface and the side wall surface of the fin structure;
forming first grooves in fin structures on two sides of the pseudo gate structure;
after the first groove is formed, a first dielectric layer is formed on the substrate, and the pseudo gate structure is located in the first dielectric layer;
removing the dummy gate structure and the second fin portion layer covered by the dummy gate structure, and forming gate openings in the first dielectric layer and between adjacent first fin portion layers;
forming a gate structure in the gate opening, wherein the gate structure surrounds each first fin part layer;
removing the first dielectric layer after the grid structure is formed, and exposing the first groove;
after the first dielectric layer is removed, a source-drain doping layer is formed in the first groove;
the bottommost layer of the fin structure is a first fin layer; forming an isolation structure covering part of the fin structure on the substrate before forming the pseudo gate structure, wherein the top surface of the isolation structure is lower than the top surface of the first fin layer at the bottommost layer;
after the first groove is formed and before the first dielectric layer is formed, removing part of the second fin portion layer exposed out of the side wall of the first groove, and forming a second groove between adjacent first fin portion layers; forming a first side wall film in the second groove, on the surface of the isolation structure and on the surface of the pseudo gate structure; after the first side wall film is formed, forming a first dielectric layer on a substrate, wherein the first dielectric layer covers the surface of the first side wall film and the surface of the isolation structure;
after the first dielectric layer is removed and before the source-drain doped layer is formed, etching the first side wall film until the side wall surface and the substrate surface of the first fin portion layer are exposed, and forming a first side wall in the second groove; and after the first side wall is formed, forming a source-drain doped layer, wherein the source-drain doped layer covers the side wall surface of the first side wall and the side wall surface of the first fin part layer.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first recess comprises: and etching the fin portion structure by taking the pseudo gate structure as a mask until the substrate surface is exposed, and forming the first grooves in the fin portion structures at two sides of the pseudo gate structure.
3. The method of forming a semiconductor structure of claim 1, wherein the method of forming a gate opening comprises: removing the pseudo gate structure and forming an initial gate opening in the first dielectric layer; and removing the second fin part layer exposed by the initial gate opening, so that the initial gate opening forms the gate opening.
4. The method of claim 1, wherein a material of the first sidewall film and a material of the first dielectric layer are different, and a material of the first sidewall film and a material of the isolation structure are different; the material of the first dielectric layer comprises: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the first side wall film comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride; the isolation structure comprises the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
5. The method of forming a semiconductor structure of claim 1, wherein the first sidewall film forming process comprises: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
6. The method of forming a semiconductor structure of claim 1, wherein the method of forming a first dielectric layer comprises: forming an initial dielectric film on the surface of the first side wall film, wherein the initial dielectric film covers the top surface and the side wall surface of the pseudo gate structure; and etching the initial dielectric film until the top surface of the pseudo gate structure is exposed, and forming the first dielectric layer on the substrate.
7. The method of claim 1, wherein a first etching process is used to remove the first dielectric layer, and the first etching process has a greater etching rate for the first dielectric layer than for the first sidewall film.
8. The method of claim 1, wherein a second etching process is used to etch the first sidewall film, and wherein the second etching process etches the first sidewall film at a rate greater than the isolation structure.
9. The method of claim 1, wherein a material of the first fin layer and a material of the second fin layer are different; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
10. The method of forming a semiconductor structure of claim 1, wherein the dummy gate structure comprises: the device comprises a dummy gate dielectric layer and a dummy gate layer positioned on the surface of the dummy gate dielectric layer; the method for forming the pseudo gate structure comprises the following steps: forming a pseudo gate dielectric film covering the fin structure on the substrate; forming a dummy gate film on the dummy gate dielectric film; and etching the dummy gate dielectric film and the dummy gate film until the top surface of the fin structure is exposed, so that the dummy gate dielectric film forms a dummy gate dielectric layer, the dummy gate film forms a dummy gate layer, and the dummy gate structure is formed.
11. The method of forming a semiconductor structure of claim 10, wherein the dummy gate structure further comprises: and the second side wall is positioned on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate layer.
12. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises: the semiconductor device comprises an interface layer, a gate dielectric layer positioned on the surface of the interface layer and a gate electrode layer positioned on the surface of the gate dielectric layer; the method for forming the gate structure comprises the following steps: forming an interface film on the surface of the gate opening and the surface of the first dielectric layer; forming a gate dielectric film on the surface of the interface film; forming a gate electrode film on the surface of the gate dielectric film, wherein the gate electrode film fills the gate opening; and flattening the gate electrode film, the gate dielectric film and the interfacial film to form the gate structure.
13. The method of forming a semiconductor structure of claim 12, further comprising: after forming the interface film and the gate dielectric film, performing heat treatment before forming the gate electrode film; the heat treatment process comprises the following steps: spike annealing or laser annealing, wherein the temperature range of the heat treatment is 850-1200 ℃.
14. The method of forming a semiconductor structure of claim 1, wherein the forming process of the source-drain doped layer comprises: and (5) an epitaxial growth process.
15. The method of forming a semiconductor structure of claim 1, further comprising: forming a second dielectric layer on the substrate after forming the source-drain doped layer; and forming a first conductive structure and a second conductive structure in the second dielectric layer, wherein the first conductive structure is electrically connected with the grid structure, and the second conductive structure is electrically connected with the source-drain doped layer.
16. The method of forming a semiconductor structure of claim 15, further comprising: after the source-drain doped layer is formed, a contact resistance layer is formed on the surface of the source-drain doped layer before the second dielectric layer is formed; and after the contact resistance layer is formed, forming the second dielectric layer on the surface of the contact resistance layer.
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| CN109427582A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109994547A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| CN109427582A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109994547A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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