CN113629142B - Semiconductor structure and method for forming semiconductor structure - Google Patents

Semiconductor structure and method for forming semiconductor structure Download PDF

Info

Publication number
CN113629142B
CN113629142B CN202010374194.7A CN202010374194A CN113629142B CN 113629142 B CN113629142 B CN 113629142B CN 202010374194 A CN202010374194 A CN 202010374194A CN 113629142 B CN113629142 B CN 113629142B
Authority
CN
China
Prior art keywords
layer
forming
region
dielectric layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010374194.7A
Other languages
Chinese (zh)
Other versions
CN113629142A (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010374194.7A priority Critical patent/CN113629142B/en
Publication of CN113629142A publication Critical patent/CN113629142A/en
Application granted granted Critical
Publication of CN113629142B publication Critical patent/CN113629142B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Geometry (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure comprises: a substrate comprising a first region and a second region, and a source doped layer located on a substrate surface of the first region; a vertical nanowire located on the source doped layer; and the grid structure is positioned on the side wall surface of the vertical nanowire and the surface of the second region substrate. Thus, the performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
With further advances in semiconductor technology, integrated circuit devices are becoming smaller in size, and conventional fin field effect transistors (finfets) have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a gate-all-around (GAA) structure field effect transistor is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin type field effect transistor with the channel gate-around structure is further increased, thereby improving the performance of the semiconductor device.
However, the performance of semiconductor devices is still in need of improvement.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a method for forming the semiconductor structure so as to improve the performance of a semiconductor device.
In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region, and a source doped layer located on a substrate surface of the first region; a vertical nanowire located on the source doped layer; and the grid structure is positioned on the side wall surface of the vertical nanowire and the surface of the second region substrate.
Optionally, the method further comprises: and a buffer layer positioned between the substrate surface and the source doped layer.
Optionally, the material of the buffer layer is different from the material of the source doped layer.
Optionally, the material of the buffer layer includes silicon germanium.
Optionally, the method further comprises: and the dielectric layer is positioned on the surface of the source doped layer, surrounds the grid structure, comprises a first dielectric layer positioned on a first area and a second area, is positioned on the surface of the first dielectric layer, and is provided with an opening between the substrate of the second area and the first dielectric layer.
Optionally, the dielectric layer further includes a second dielectric layer located on the first dielectric layer surface, the substrate surface and the gate structure surface, and the second dielectric layer surface is lower than the top surface of the vertical nanowire.
Optionally, the method further comprises: a first electrical interconnect structure located on the source doped layer, the first electrical interconnect structure being electrically interconnected with the source doped layer; a second electrical interconnect structure located atop the vertical nanowire, the second electrical interconnect structure being electrically interconnected with the vertical nanowire; and a third electrical interconnect structure on the gate structure on the substrate surface of the second region, the third electrical interconnect structure being electrically interconnected with the gate structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region and a second region; forming a source doped layer on the surface of the substrate of the first region; forming a vertical nanowire on the source doped layer; and forming a grid structure on the side wall surface of the vertical nanowire and the surface of the second region substrate.
Optionally, the method for forming the source doped layer includes: forming a source doping material layer on the surface of the substrate before forming the vertical nanowire; after forming the source doping material layer, removing the source doping material layer of the second region.
Optionally, the method further comprises: forming a dielectric layer on the surface of the source doped layer, wherein the dielectric layer surrounds the gate structure, and the method for forming the dielectric layer comprises the following steps: and forming a first dielectric layer on the first region and the second region, wherein part of the grid structure is positioned on the surface of the first dielectric layer of the second region, and an opening is formed between the first dielectric layer of the second region and the substrate.
Optionally, the method for forming the dielectric layer further includes: and after the first dielectric layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, the surface of the substrate and the surface of the grid structure, wherein the surface of the second dielectric layer is lower than the top surface of the vertical nanowire.
Optionally, the method for forming the gate structure includes: forming an initial gate structure on the surface of the vertical nanowire and the surface of the source doped material layer of the second region before forming the first dielectric layer; and after the second dielectric layer is formed, the second dielectric layer is used as a mask, and the initial gate structure is etched back until the top surface and part of the side wall surface of the vertical nanowire are exposed.
Optionally, the method for forming the first dielectric layer includes: forming a first dielectric material layer on the surface of the source doping material layer after forming the vertical nanowire and before forming the initial gate structure; forming a first mask layer on the surface of the initial gate structure and the surfaces of the first dielectric material layers of the first region and the second region after forming the initial gate structure; and etching the first dielectric material layer by taking the first mask layer as a mask until the surface of the source doped material layer is exposed.
Optionally, the method for removing the source doped material layer of the second region includes: after the first dielectric layer is formed, etching the source doping material layer by taking the first mask layer as a mask until the surface of the substrate is exposed, so as to form an initial source doping layer; and after the initial source doping layer is formed, continuing to etch the initial source doping layer on the surface of the second region by taking the first mask layer as a mask until the opening is formed between the first dielectric layer and the substrate of the second region.
Optionally, the process of etching the initial source doped material layer includes a wet etching process, and an etching liquid component of the wet etching process includes hydrofluoric acid, hydrogen peroxide and acetic acid.
Optionally, the method further comprises: a buffer layer is formed on the substrate surface prior to forming the source dopant material layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor structure provided by the technical scheme of the invention, the source doped layer is positioned on the substrate surface of the first region, and the gate structure is positioned on the side wall surface of the vertical nanowire and the substrate surface of the second region, so that the source doped layer overlapped with the gate structure on the substrate surface of the second region is reduced in the direction vertical to the substrate surface, thereby reducing the parasitic capacitance formed between the gate structure and the source doped layer, and further improving the performance of the semiconductor structure.
Accordingly, in the method for forming a semiconductor structure provided by the technical scheme of the invention, since the source doped layer is formed on the substrate surface of the first region and the gate structure is formed on the sidewall surface of the vertical nanowire and the substrate surface of the second region, the overlapping part between the source doped layer and the gate structure of the second region is reduced in the direction vertical to the substrate surface, thereby reducing the parasitic capacitance formed between the gate structure and the source doped layer and further improving the performance of the semiconductor structure.
Further, since the buffer layer is formed on the surface of the substrate before the source doped material layer is formed, on one hand, the buffer layer can be used as an etching stop layer, and through the buffer layer, when the source doped material layer of the second region is removed subsequently, the damage of the etching process for removing the source doped material layer of the second region to the substrate can be reduced, so that the performance of the semiconductor structure is improved; on the other hand, the material of the buffer layer can be selected to enable the crystal lattice of the source-drain doped layer formed on the buffer layer to be matched with the crystal lattice of the substrate, so that the performance of the semiconductor structure is further improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure;
fig. 2 to 8 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices is still in need of improvement. The analysis will now be described with reference to specific examples.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure.
Referring to fig. 1, the semiconductor structure includes: a substrate 100, and a source doped layer 110 on the substrate 100; the semiconductor device comprises a channel column 130 positioned on the source doped layer 110 and a first dielectric layer 120 positioned on the surface of the source doped layer 110, wherein the first dielectric layer 120 covers part of the side wall surface of the channel column 130.
In a direction perpendicular to the substrate, the tops of the channel pillars 130 have doped regions (not shown) whose channel pillar 130 portions function as drains for vertical nanowire transistors.
The source doped layer 110 serves as the source of the vertical nanowire transistor. Thus, a channel can be formed in the channel pillar 130.
The semiconductor structure further includes: the gate structure 140 is located on the surface of the first dielectric layer 120 and on the sidewall surface of the channel pillar 130; a first conductive plug 161 located on the source doped layer 110, the first conductive plug 161 being electrically interconnected with the source doped layer 110; a second conductive plug 162 located on the top surface of the channel pillar 130, the second conductive plug 162 being electrically interconnected with the channel pillar 130 portion of the doped region; a third conductive plug 163 on the gate structure 140 on the surface of the first dielectric layer 120, the third conductive plug 163 being electrically interconnected with the gate structure 140; a second dielectric layer 150 surrounding the gate structure 140, the channel pillar 130, the first conductive plug 161, the second conductive plug 162, and the third conductive plug 163.
However, in the above structure, since the source doping layer 110, the first dielectric layer 120, and the gate structure 140 on the surface of the substrate 100 overlap in a direction perpendicular to the substrate 100, parasitic capacitance is easily generated between the overlapped source doping layer 110 and gate structure 140, thereby making the performance of the semiconductor structure poor.
In order to solve the technical problem, the embodiment of the invention provides a semiconductor structure, which is characterized in that a source doped layer on the surface of a substrate is positioned in a first region, and an opening is formed between a gate structure on a second region and the substrate in the second region, so that the overlapping part between the gate structure and the source doped layer is reduced, and the performance of the semiconductor structure is improved.
Fig. 2 to 8 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 including a first region I and a second region II; forming a source doping material layer 210 on the surface of the substrate 200; after forming the source doping material layer 210, vertical nanowires 220 are formed on the source doping material layer 210.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
The process of forming the source doping material layer 210 includes an epitaxial growth process.
In this embodiment, the source doped material layer 210 is doped in situ while the source doped material layer 210 is formed by epitaxial growth.
When the subsequently formed gate structure is used to form a P-type device, the material of the source doped material layer 210 includes silicon, germanium or silicon germanium; the doped ions are P-type ions, and the doped ions comprise boron ions, boron fluoride ions or indium ions.
When the subsequently formed gate structure is used to form an N-type device, the material of the source doped material layer 210 includes silicon, gallium arsenide, or indium gallium arsenide; the doped ions are N-type ions, and the doped ions comprise phosphorus ions, arsenic ions or antimony ions.
In this embodiment, a barrier layer 221 is formed on top of the vertical nanowire 220 at the same time as the vertical nanowire 220 is formed.
The method of forming the vertical nanowire 220 and the barrier layer 221 includes: forming a vertical nanowire material layer (not shown) on the surface of the source doped material layer 210; forming a barrier material layer (not shown) on the surface of the vertical nanowire material layer; forming a vertical nanowire mask layer on the surface of part of the barrier material layer; and etching the barrier material layer and the vertical nanowire material layer by taking the vertical nanowire mask layer as a mask until the surface of the source doping material layer 210 is exposed.
The process of forming the vertical nanowire material layer includes a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process, or an epitaxial growth process.
In this embodiment, the process of forming the vertical nanowire material layer is an epitaxial growth process.
The process of forming the barrier material layer includes a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process, or an oxidation process, such as a thermal oxidation process, or the like.
In this embodiment, the process of forming the barrier material layer includes a thermal oxidation process.
The process of etching the barrier material layer and the vertical nanowire material layer includes a dry etching process or a wet etching process.
In this embodiment, the process of etching the barrier material layer and the vertical nanowire material layer is a dry etching process, and parameters of the dry etching process include: the gas used comprises CH 3 F、N 2 And O 2 Wherein the CH 3 F has a flow rate of 10sccm to 200S sccm, N 2 The flow rate of the catalyst is in the range of 20sccm to 300sccm, the O 2 The flow range of (2) is 5 sccm-200 sccm; the time range is 5 seconds to 200 seconds.
The material of the vertical nanowire 220 is a semiconductor material.
In this embodiment, the material of the vertical nanowire 220 is silicon.
In other embodiments, the vertical nanowire material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator or germanium-on-insulator, and the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In this embodiment, the material of the blocking layer 221 includes at least one of silicon nitride, silicon oxynitride, and silicon carbonitride boride.
The barrier layer 221 serves to protect the top surface of the vertical nanowire 220, thereby reducing the top surface of the vertical nanowire 220 from damage during a subsequent etching process of the semiconductor structure.
In other embodiments, no barrier layer is formed.
In this embodiment, before the source doping material layer 210 is formed, a buffer layer 201 is formed on the surface of the substrate 200.
Since the buffer layer 201 is formed on the surface of the substrate 200 before the source doping material layer 210 is formed, on one hand, the buffer layer 201 can be used as an etching stop layer, and by using the buffer layer 201, the damage of the etching process for removing the source doping material layer 210 of the second region II to the substrate 200 can be reduced when the source doping layer is formed by removing the source doping material layer 210 of the second region II, thereby improving the performance of the semiconductor structure. On the other hand, the material of the buffer layer 201 may be selected, for example, the material of the buffer layer 201 is silicon germanium, so that the lattice of the source-drain doped layer and the lattice of the substrate 200 are more matched, thereby further improving the performance of the semiconductor structure.
The process of forming the buffer layer 201 includes a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process, or an epitaxial growth process.
In this embodiment, the process of forming the buffer layer 201 is an epitaxial growth process.
In this embodiment, the material of the buffer layer 201 is different from the material of the source doped material layer. Accordingly, the material of the buffer layer 201 is different from the material of the source doped layer. Thereby, the buffer layer 201 can function as an etching stop layer.
In this embodiment, the material of the buffer layer 201 includes silicon germanium.
Since the material of the substrate 200 is silicon and the material of the buffer layer 201 is silicon germanium, an electrical interconnection between the source doped layer and the substrate 200 can be achieved through the buffer layer 201.
In other embodiments, no buffer layer is formed.
Referring to fig. 3, after forming the vertical nanowire 220, a first dielectric material layer 230 is formed on the surface of the source doped material layer 210; an initial gate structure is formed on the surface of the vertical nanowire 220 and the surface of the source doped material layer 210 of the second region II.
Specifically, forming the initial gate structure on the surface of the vertical nanowire 220 and the surface of the source doped material layer 210 of the second region II means that, after forming the first dielectric material layer 230, an initial gate structure 240 is formed on the surface of the vertical nanowire 220 and the surface of the first dielectric material layer 230 of the second region II.
The first dielectric material layer 230 provides material for subsequent formation of the first dielectric layer.
The materials of the first dielectric material layer 230 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the first dielectric material layer 230 is silicon oxide.
In this embodiment, the process of forming the first dielectric material layer 230 includes a deposition process, a spin-on process, or an oxidation process.
The initial gate structure 240 includes: an initial gate dielectric layer 241 on the surface of the vertical nanowire 220 and the first dielectric material layer 230 of the second region II, an initial work function layer 242 on the surface of the initial gate dielectric layer, and an initial gate electrode layer 243 on the surface of the initial work function layer.
The initial gate structure 240 provides material for a subsequently formed gate structure that includes a gate dielectric layer, a work function layer on a surface of the gate dielectric layer, and a gate electrode layer on a surface of the work function layer. The initial gate dielectric layer provides materials for the gate dielectric layer, the initial work function layer provides materials for the work function layer, and the initial gate electrode layer provides materials for the gate electrode layer.
In this embodiment, the material of the initial gate dielectric layer is a material with a high dielectric constant (K value is greater than 3.9), including silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide, and the like. In other embodiments, the material of the initial gate dielectric layer comprises silicon oxide.
The material of the initial work function layer comprises titanium nitride.
The material of the initial gate electrode layer comprises a metallic material, such as one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the material of the initial gate electrode layer is tungsten.
In this embodiment, the method for forming the initial gate structure 240 includes: forming a gate structure material layer on the surface of the vertical nanowire 220 and the surface of the first dielectric material layer 230 of the second region II, wherein the gate structure material layer includes a gate dielectric material layer (not shown) on the surface of the vertical nanowire 220 and the surface of the first dielectric material layer 230 of the second region II, a work function material layer (not shown) on the surface of the gate dielectric material layer, and a gate electrode material layer (not shown) on the surface of the work function material layer; forming a gate structure mask layer on the surface of the gate electrode material layer, wherein the gate structure mask layer exposes a part of the gate electrode material layer on the surface of the first dielectric material layer 230; and etching the gate structure material layer by taking the gate structure mask layer as a mask until the surface of the first dielectric material layer 230 is exposed.
In this embodiment, the process of etching the gate structure material layer includes a dry etching process or a wet etching process.
In this embodiment, after the initial gate structure 240 is formed, the gate structure mask layer is removed.
Referring to fig. 4, a first dielectric layer 231 is formed on the first region I and the second region II.
The method for forming the first dielectric layer 231 includes: after forming the initial gate structure 240, forming a first mask layer 250 on the surface of the initial gate structure 240 and on the surface of the first dielectric material layer 230 of the first and second regions I and II; the first dielectric material layer 230 is etched using the first mask layer 250 as a mask until the surface of the source doped material layer 210 is exposed.
The process of etching the first dielectric material layer 230 includes a wet etching process or a dry etching process.
In this embodiment, the process of etching the first dielectric material layer 230 is a wet etching process.
In this embodiment, the process of forming the first mask layer 250 includes a deposition process or a spin-coating process.
In this embodiment, the material of the first mask layer 250 includes an organic filling material.
Referring to fig. 5, after the source doping material layer 210 is formed, the source doping material layer 210 of the second region II is removed to form a source doping layer 211 on the surface of the substrate 200 of the first region I, and a vertical nanowire 220 is formed on the source doping layer 211.
Since the source doped layer 211 is formed on the surface of the substrate 200 in the first region I and the gate structure is subsequently formed on the sidewall surface of the vertical nanowire 220 and the surface of the substrate 200 in the second region II, an overlapping portion between the source doped layer 211 and the gate structure in the second region II is reduced in a direction perpendicular to the surface of the substrate 200, thereby reducing parasitic capacitance formed between the gate structure and the source doped layer 211 and further improving performance of the semiconductor structure.
Specifically, in this embodiment, after the first dielectric layer 231 is formed, the source doped material layer 210 of the second region II is removed.
Thus, the first dielectric layer 231 of the second region II has an opening 232 between the substrate 200.
Specifically, in this embodiment, the opening 232 between the first dielectric layer 231 of the second region II and the substrate 200 means that the opening 232 is formed between the first dielectric layer 231 of the second region II and the buffer layer 201.
In this embodiment, the method for removing the source doped material layer 210 of the second region II includes: after forming the first dielectric layer 231, etching the source doped material layer 210 with the first mask layer 250 as a mask until the surface of the substrate 200 is exposed, so as to form an initial source doped layer (not shown); after the initial source doping layer is formed, etching the initial source doping layer on the surface of the second region II by using the first mask layer 250 as a mask is continued until the opening 232 is formed between the first dielectric layer 231 and the substrate 200 of the second region II.
In this embodiment, after the first dielectric layer 231 is formed, the source doped material layer 210 is etched until the surface of the substrate 200 is exposed, that is, until the surface of the buffer layer 201 is exposed, with the first mask layer 250 as a mask.
In this embodiment, the process of etching the initial source doped layer 210 includes a wet etching process.
In this embodiment, the etching solution component of the wet etching process includes hydrofluoric acid, hydrogen peroxide and acetic acid.
The wet etching process further comprises the following technological parameters: the volume ratio of hydrofluoric acid to hydrogen peroxide is in the range of 1/3 to 2/3; the volume ratio of hydrofluoric acid to acetic acid is in the range of 1/5 to 1/2; the temperature is 25 degrees celsius to 95 degrees celsius.
In this embodiment, after the source doping layer 211 is formed, the first mask layer 250 is removed.
Referring to fig. 6, after the first mask layer 250 is removed, a second dielectric layer 260 is formed on the surface of the first dielectric layer 231, the surface of the substrate 200, and the sidewall of the initial gate structure 240, and the surface of the second dielectric layer 260 is lower than the top surface of the vertical nanowire 220.
The first dielectric layer 231 and the second dielectric layer 260 form a dielectric layer 261, and the dielectric layer 261 surrounds a gate structure formed later.
The second dielectric layer 260 is used to form the dielectric layer 261 on the one hand, and on the other hand, as a mask layer when the initial gate structure 240 is etched back subsequently, so as to protect the initial gate structure 240 from being etched in the etching back process, and reduce damage of the etching back process to the initial gate structure 240, thereby forming the gate structure 270 with better morphology, and improving performance of the semiconductor structure.
In this embodiment, the process of forming the second dielectric layer 260 includes a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process, or a spin-on process.
The materials of the second dielectric layer 260 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the second dielectric layer 260 is silicon oxide.
Referring to fig. 7, after the second dielectric layer 260 is formed, the initial gate structure 240 is etched back using the second dielectric layer 260 as a mask until the top surface and part of the sidewall surface of the vertical nanowire 220 are exposed, so as to form a gate structure 270 on the sidewall surface of the vertical nanowire 220 and the surface of the second region II substrate 200.
Specifically, in this embodiment, the second dielectric layer 260 is formed on the surface of the gate structure 270, and a portion of the gate structure 270 is located on the surface of the first dielectric layer 231 in the second region II.
The gate structure 270 includes: the gate dielectric layer 271 is located on the sidewall surface of the vertical nanowire 220 and the surface of the first dielectric layer 230, the work function layer 272 is located on the surface of the gate dielectric layer 271, and the gate electrode layer 273 is located on the surface of the work function layer 272.
In this embodiment, the process of etching back the initial gate structure 240 includes a wet etching process or a dry etching process.
In this embodiment, after the gate structure 270 is formed, the blocking layer 221 is removed.
Referring to fig. 8, a first electrical interconnection structure 291 is formed on the surface of the source doped layer 211, and the first electrical interconnection structure 291 is electrically interconnected with the source doped layer 211.
In this embodiment, a second electrical interconnect structure 292 is also formed on the vertical nanowire 220, the second electrical interconnect structure 292 being electrically interconnected with the vertical nanowire 220.
In this embodiment, a third electrical interconnection structure 293 is further formed on the gate structure 270 on the surface of the first dielectric layer 231, and the third electrical interconnection structure 293 is electrically interconnected with the gate structure 270.
In this embodiment, before forming the first electrical interconnection structure 291, the second electrical interconnection structure 292, and the third electrical interconnection structure 293, a third dielectric layer 280 is formed on the surface of the second dielectric layer 260, and the surface of the third dielectric layer 280 is higher than the top surface of the vertical nanowire 220.
In this embodiment, the process of forming the third dielectric layer 280 includes a deposition process, such as a chemical vapor deposition process or an atomic layer deposition process, or a spin-on process.
The materials of the third dielectric layer 280 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the third dielectric layer 280 is silicon oxide.
In this embodiment, the method for forming the first electrical interconnection structure 291 includes: forming a first opening (not shown) in the dielectric layer and the third dielectric layer 280, the first opening exposing the surface of the source doped layer 211; the first electrical interconnect structure 291 is formed within the first opening.
In this embodiment, the material of the first electrical interconnect structure 291 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the method of forming the second electrical interconnect structure 292 includes: forming a second opening (not shown) in the third dielectric layer 280 and the top of the vertical nanowire 220; the second electrical interconnect structure 292 is formed within the second opening.
In this embodiment, the material of the second electrical interconnect structure 292 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the method for forming the third electrical interconnection structure 293 includes: forming a third opening (not shown) in the second dielectric layer 260 and the third dielectric layer 280, wherein the third opening exposes the gate structure 270 on the surface of the first dielectric layer 231; the third electrical interconnect structure 293 is formed within the third opening.
In this embodiment, the material of the third electrical interconnection structure 293 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
Correspondingly, the embodiment of the present invention further provides a semiconductor structure formed by the above forming method, please continue to refer to fig. 8, which includes: a substrate 200, wherein the substrate 200 comprises a first region I and a second region II, and a source doped layer 211 positioned on the surface of the substrate 200 of the first region I; a vertical nanowire 220 located on the source doped layer 211; and a gate structure 270 located on a sidewall surface of the vertical nanowire 220 and on a surface of the second region II substrate 200.
Since the source doped layer 211 is located on the surface of the substrate 200 in the first region I and the gate structure 270 is located on the sidewall surface of the vertical nanowire 220 and the surface of the substrate 200 in the second region II, the source doped layer 211 overlapping the gate structure 270 on the surface of the substrate 200 in the second region II is reduced in the direction perpendicular to the surface of the substrate 200, thereby reducing parasitic capacitance formed between the gate structure 270 and the source doped layer 211 and further improving the performance of the semiconductor structure.
The material of the substrate 200 is a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. Among them, the iii-v group element-made multi-element semiconductor material includes InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
The source doped layer 211 has doped ions therein.
When the gate structure 270 is used to form a P-type device, the material of the source doped layer 211 comprises silicon, germanium, or silicon germanium; the doped ions are P-type ions, and the doped ions comprise boron ions, boron fluoride ions or indium ions.
When the gate structure 270 is used to form an N-type device, the material of the source doped layer 211 includes silicon, gallium arsenide, or indium gallium arsenide; the doped ions are N-type ions, and the doped ions comprise phosphorus ions, arsenic ions or antimony ions.
The material of the vertical nanowire 220 is a semiconductor material.
In this embodiment, the material of the vertical nanowire 220 is silicon.
In other embodiments, the vertical nanowire material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon on insulator, or germanium on insulator. Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In this embodiment, the gate structure 270 includes: a gate dielectric layer 271 on the sidewall of the vertical nanowire 220; and a gate electrode layer 273 positioned on the surface of the gate dielectric layer 271 and the surface of the second region II substrate 200.
In this embodiment, the gate structure 270 further includes a work function layer 272 between the gate dielectric layer 271 and the gate electrode layer 273.
In this embodiment, the gate dielectric layer 271 is made of a material with a high dielectric constant (K value is greater than 3.9), including silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, tantalum oxide, lanthanum oxide, and the like. In other embodiments, the gate dielectric layer material includes silicon oxide.
The material of the work function layer 272 includes titanium nitride.
The material of the gate electrode layer 273 includes a metal material such as one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the material of the gate electrode layer 273 is tungsten.
In this embodiment, the semiconductor structure further includes: a buffer layer 201 between the surface of the substrate 200 and the source doped layer 211.
In this embodiment, the material of the buffer layer 201 is different from the material of the source doped layer 211.
In this embodiment, the material of the buffer layer 201 includes silicon germanium.
In this embodiment, the semiconductor structure further includes: a barrier layer 221 on top of the vertical nanowires 220.
In this embodiment, the barrier layer 221 is made of at least one of silicon nitride, silicon oxynitride, and silicon carbonitride boride.
In this embodiment, the semiconductor structure further includes: and a dielectric layer 261 positioned on the surface of the source doped layer 211, wherein the dielectric layer 261 surrounds the gate structure 270.
In this embodiment, the dielectric layer 261 includes: a first dielectric layer 231 on the first region I and the second region II, a portion of the gate structure 270 is located on the surface of the first dielectric layer 231, and an opening 232 is formed between the substrate 200 of the second region II and the first dielectric layer 231.
The material of the first dielectric layer 231 includes: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the first dielectric layer 231 is silicon oxide.
In this embodiment, the dielectric layer 261 further includes: and a second dielectric layer 260 positioned on the surface of the first dielectric layer 231, the surface of the substrate 200 and the surface of the gate structure 270, wherein the surface of the second dielectric layer 260 is lower than the top surface of the vertical nanowire 220.
The materials of the second dielectric layer 260 include: at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the second dielectric layer 260 is silicon oxide.
In this embodiment, the semiconductor structure further includes: a first electrical interconnect structure 291 located on the source doped layer 211, the first electrical interconnect structure 291 being electrically interconnected with the source doped layer 211; a second electrical interconnect structure 292 located atop the vertical nanowire 220, the second electrical interconnect structure 292 being electrically interconnected with the vertical nanowire 220; a third electrical interconnect structure 293 located on the gate structure 270 on the surface of the substrate 200 of the second region II, the third electrical interconnect structure 293 being electrically interconnected with the gate structure 270.
In this embodiment, the material of the first electrical interconnect structure 291 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the material of the second electrical interconnect structure 292 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the material of the third electrical interconnection structure 293 includes one or more of tungsten, cobalt, copper, nickel, titanium, and titanium nitride.
In this embodiment, the semiconductor structure further includes a third dielectric layer 280 located on the surface of the second dielectric layer 260, where the third dielectric layer 280 covers the sidewall surface of the vertical nanowire 220, and the third dielectric layer 280 surrounds the first electrical interconnection structure 291, the second electrical interconnection structure 292, and the third electrical interconnection structure 293.
The materials of the third dielectric layer 280 include: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.
In this embodiment, the material of the third dielectric layer 280 is silicon oxide.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region, and a source doped layer located on a substrate surface of the first region;
a vertical nanowire located on the source doped layer;
the grid structure is positioned on the side wall surface of the vertical nanowire and the surface of the second region substrate;
the dielectric layer is positioned on the surface of the source doping layer, surrounds the grid structure, comprises a first dielectric layer positioned on a first area and a second area, is positioned on the surface of the first dielectric layer, and is provided with an opening between a substrate of the second area and the first dielectric layer;
the dielectric layer further comprises a second dielectric layer, the second dielectric layer is located on the surface of the first dielectric layer, the surface of the substrate of the second region and the surface of the gate structure, and the opening is located between the source doped layer and the second dielectric layer of the second region.
2. The semiconductor structure of claim 1, further comprising: and a buffer layer positioned between the substrate surface and the source doped layer.
3. The semiconductor structure of claim 2, wherein a material of the buffer layer is different from a material of the source doped layer.
4. The semiconductor structure of claim 3, wherein a material of the buffer layer comprises silicon germanium.
5. The semiconductor structure of claim 1, wherein the second dielectric layer surface is lower than the vertical nanowire top surface.
6. The semiconductor structure of claim 1, further comprising: a first electrical interconnect structure located on the source doped layer, the first electrical interconnect structure being electrically interconnected with the source doped layer; a second electrical interconnect structure located atop the vertical nanowire, the second electrical interconnect structure being electrically interconnected with the vertical nanowire; and a third electrical interconnect structure on the gate structure on the substrate surface of the second region, the third electrical interconnect structure being electrically interconnected with the gate structure.
7. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region;
forming a source doped layer on the surface of the substrate of the first region;
forming a vertical nanowire on the source doped layer;
forming a grid structure on the side wall surface of the vertical nanowire and the surface of the second region substrate;
forming a dielectric layer on the surface of the source doped layer, wherein the dielectric layer surrounds the gate structure, and the method for forming the dielectric layer comprises the following steps: forming a first dielectric layer on the first region and the second region, wherein part of the grid structure is positioned on the surface of the first dielectric layer of the second region, and an opening is formed between the first dielectric layer of the second region and the substrate;
and after the first dielectric layer is formed, forming a second dielectric layer on the surface of the first dielectric layer, the surface of the substrate and the surface of the gate structure.
8. The method of forming a semiconductor structure of claim 7, wherein the method of forming the source doped layer comprises: forming a source doping material layer on the surface of the substrate before forming the vertical nanowire; after forming the source doping material layer, removing the source doping material layer of the second region.
9. The method of forming a semiconductor structure of claim 8, wherein a surface of said second dielectric layer is lower than a top surface of said vertical nanowire.
10. The method of forming a semiconductor structure of claim 9, wherein the method of forming the gate structure comprises: forming an initial gate structure on the surface of the vertical nanowire and the surface of the source doped material layer of the second region before forming the first dielectric layer; and after the second dielectric layer is formed, the second dielectric layer is used as a mask, and the initial gate structure is etched back until the top surface and part of the side wall surface of the vertical nanowire are exposed.
11. The method of forming a semiconductor structure of claim 10, wherein the method of forming the first dielectric layer comprises: forming a first dielectric material layer on the surface of the source doping material layer after forming the vertical nanowire and before forming the initial gate structure; forming a first mask layer on the surface of the initial gate structure and the surfaces of the first dielectric material layers of the first region and the second region after forming the initial gate structure; and etching the first dielectric material layer by taking the first mask layer as a mask until the surface of the source doped material layer is exposed.
12. The method of forming a semiconductor structure of claim 11, wherein the removing the source dopant material layer of the second region comprises: after the first dielectric layer is formed, etching the source doping material layer by taking the first mask layer as a mask until the surface of the substrate is exposed, so as to form an initial source doping layer; and after the initial source doping layer is formed, continuing to etch the initial source doping layer on the surface of the second region by taking the first mask layer as a mask until the opening is formed between the first dielectric layer and the substrate of the second region.
13. The method of forming a semiconductor structure of claim 12, wherein the process of etching the initial source dopant material layer comprises a wet etch process, the etch liquid composition of the wet etch process comprising hydrofluoric acid, hydrogen peroxide, and acetic acid.
14. The method of forming a semiconductor structure of claim 8, further comprising: a buffer layer is formed on the substrate surface prior to forming the source dopant material layer.
CN202010374194.7A 2020-05-06 2020-05-06 Semiconductor structure and method for forming semiconductor structure Active CN113629142B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010374194.7A CN113629142B (en) 2020-05-06 2020-05-06 Semiconductor structure and method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010374194.7A CN113629142B (en) 2020-05-06 2020-05-06 Semiconductor structure and method for forming semiconductor structure

Publications (2)

Publication Number Publication Date
CN113629142A CN113629142A (en) 2021-11-09
CN113629142B true CN113629142B (en) 2023-11-21

Family

ID=78376645

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010374194.7A Active CN113629142B (en) 2020-05-06 2020-05-06 Semiconductor structure and method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN113629142B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877353A (en) * 2009-04-28 2010-11-03 日本优尼山帝斯电子株式会社 Semiconductor device and manufacture method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8823085B2 (en) * 2012-08-08 2014-09-02 Unisantis Electronics Singapore Pte. Ltd. Method for producing a semiconductor device and semiconductor device
US9882047B2 (en) * 2016-02-01 2018-01-30 International Business Machines Corporation Self-aligned replacement metal gate spacerless vertical field effect transistor
US10658246B2 (en) * 2018-08-27 2020-05-19 International Business Machines Corporation Self-aligned vertical fin field effect transistor with replacement gate structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877353A (en) * 2009-04-28 2010-11-03 日本优尼山帝斯电子株式会社 Semiconductor device and manufacture method thereof

Also Published As

Publication number Publication date
CN113629142A (en) 2021-11-09

Similar Documents

Publication Publication Date Title
US10177237B2 (en) Etch stop for airgap protection
US11948839B2 (en) Power reduction in finFET structures
US9590085B2 (en) Method and structure for III-V FinFET
US8617956B2 (en) Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device
US20240170337A1 (en) Dielectric liner for field effect transistors
US20230137307A1 (en) Integrated circuit with backside trench for nanosheet removal
US10923581B2 (en) Method for forming semiconductor structure
US20230187511A1 (en) Integrated circuit structure and manufacturing method thereof
US20230307456A1 (en) Complementary field effect transistor with hybrid nanostructure
CN113629142B (en) Semiconductor structure and method for forming semiconductor structure
CN113363321B (en) Semiconductor structure and forming method thereof
CN114078707B (en) Semiconductor structure and forming method thereof
CN112992679B (en) Semiconductor structure and forming method thereof
CN113629143B (en) Semiconductor structure and method for forming semiconductor structure
CN113629141B (en) Semiconductor structure and forming method thereof
CN111146198B (en) Semiconductor structure and manufacturing method thereof
US20230307523A1 (en) Structure and formation method of semiconductor device with gate stack
CN113629140B (en) Semiconductor structure and forming method thereof
CN113363211B (en) Semiconductor structure and forming method thereof
CN113363154B (en) Method for forming semiconductor structure
US20230343834A1 (en) Semiconductor gate and contact formation
US20230395721A1 (en) Source/drain contact landing
US20230268403A1 (en) Semiconductor device having front side and back side source/drain contacts
CN115566065A (en) Semiconductor structure
CN113113356A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant