CN111146198B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN111146198B CN111146198B CN201811311036.6A CN201811311036A CN111146198B CN 111146198 B CN111146198 B CN 111146198B CN 201811311036 A CN201811311036 A CN 201811311036A CN 111146198 B CN111146198 B CN 111146198B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure may include a substrate, an epitaxial layer disposed on the substrate, a conductive feature disposed in the epitaxial layer, and a diffusion barrier layer disposed on a plurality of sidewalls of the conductive feature. The conductive member has a protrusion higher than the epitaxial layer.
Description
Technical Field
The present invention relates generally to semiconductor technology, and more particularly to semiconductor devices having conductive features.
Background
Laterally Diffused Metal Oxide Semiconductor (LDMOS) has become a Semiconductor device frequently used in various electronic products because of its advantages of high operating efficiency, good gain characteristics, and easy integration with other circuits.
However, since the ldmos has a conductive member connecting the source and the conductive end of the substrate, when a subsequent manufacturing process (e.g., a high temperature thermal manufacturing process) is performed, the dopant in the conductive member often diffuses into the surrounding devices, which deteriorates the electrical properties of the ldmos. Furthermore, as the lateral diffused metal oxide semiconductor is scaled down, the effect of dopant diffusion of the conductive feature is more significant, thereby limiting the scaling limit of the lateral diffused metal oxide semiconductor, resulting in an inability to reduce the source-drain Resistance (RDSON), resulting in an inability to further improve the performance of the lateral diffused metal oxide semiconductor.
Therefore, although the conventional Laterally Diffused Metal Oxide Semiconductor (LDMOS) has been generally satisfactory, there still exist many problems, and how to improve the conventional laterally diffused metal oxide semiconductor has become one of the issues of considerable importance in the industry.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor structure, which may include: a substrate; an epitaxial layer disposed on the substrate; the conductive component is arranged in the epitaxial layer and is provided with a protruding part higher than the epitaxial layer; and a diffusion barrier layer disposed on the plurality of sidewalls of the conductive feature. In one embodiment, the width of the protrusion is greater than the width of the conductive feature in the epitaxial layer. In one embodiment, the protrusion covers a top surface of the diffusion barrier layer. In one embodiment, the diffusion barrier layer comprises one or more dielectric barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer over the barrier oxide layer.
In one embodiment, the semiconductor structure may further comprise: a source region disposed in the epitaxial layer, wherein the diffusion barrier layer contacts the source region and separates the source region and the conductive feature. In one embodiment, the conductive feature is disposed between two Laterally Diffused Metal Oxide Semiconductors (LDMOS), and the conductive feature passes through a common source of the LDMOS.
Some embodiments of the present invention provide methods of fabricating a semiconductor structure, which may include: providing a substrate; forming an epitaxial layer on a substrate; forming a mask structure on the epitaxial layer, wherein the mask structure has an opening exposing a portion of the epitaxial layer; using the mask structure as an etching mask to remove the exposed epitaxial layer to form a trench; forming a diffusion barrier layer on a plurality of side walls of the trench; forming a conductive feature in the trench, the conductive feature having a protrusion above the epitaxial layer; and removing the mask structure.
In an embodiment, the width of the protrusion is greater than the width of the conductive feature in the trench. In one embodiment, the protrusion covers a top surface of the diffusion barrier layer. In one embodiment, the mask structure includes one or more dielectric layers. In one embodiment, the mask structure includes a first oxide layer and a nitride layer formed on the first oxide layer. In one embodiment, the mask structure further includes a second oxide layer formed on the nitride layer. In one embodiment, the mask structure is a plurality of dielectric layers, and the removing of the mask structure comprises: removing part of the mask structure and retaining a dielectric layer closest to the epitaxial layer; and removing the remaining mask structure after removing part of the mask structure.
In one embodiment, the diffusion barrier layer comprises one or more dielectric barrier layers. In one embodiment, the diffusion barrier layer includes a barrier oxide layer and a barrier nitride layer formed over the barrier oxide layer. In one embodiment, the method for fabricating a semiconductor structure further comprises: a source region is formed in the epitaxial layer, and a diffusion barrier layer contacts the source region and separates the source region and the conductive feature. In one embodiment, the conductive feature is formed between two Laterally Diffused Metal Oxide Semiconductors (LDMOS), and the conductive feature passes through a common source of the LDMOS.
Drawings
The embodiments of the invention will be understood more fully from the detailed description given below and from the accompanying drawings. It is emphasized that, in accordance with industry standard practice, many of the features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Figures 1-15 are cross-sectional views of various stages in the formation of a semiconductor structure according to some embodiments of the present invention; fig. 8-10 are cross-sectional views of various stages of removing a mask structure according to some embodiments, and fig. 11-13 are cross-sectional views of various stages of removing a mask structure according to other embodiments.
Description of the symbols:
100-a semiconductor structure;
10-substrate;
12-epitaxial layer;
14-a mask structure;
15-opening;
16a, 16b to a first oxide layer;
18-groove;
20-diffusion barrier layer;
22-barrier oxide layer;
24 barrier nitride layer;
26-conductive material;
28-a conductive member;
30-a protrusion;
32a, 32 b-nitride layer;
34-a second oxide layer;
36-contact doping region;
38-the first well zone;
40-a source region;
42-second well zone;
44 to the drain region;
46-a gate structure;
48-gate dielectric layer;
50-a gate electrode;
52-gate silicide layer;
54-spacer;
55-insulating layer;
56-conducting layer;
58-interlayer dielectric layer;
60-contact plug;
62-a conductive member;
s1, S2-side wall.
Detailed Description
The following provides many different embodiments, or examples, for implementing different features of embodiments of the invention. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the specification to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. These iterations are for simplicity and clarity and do not in themselves represent a particular relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below … …," "below … …," "below," "above … …," "above," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated. Such spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is rotated to other orientations (rotated 90 degrees or otherwise), the spatially relative descriptors used herein should be interpreted as such with respect to the rotated orientation.
Fig. 1-7 and 14-15 are diagrams of different stages in forming the semiconductor structure 100 shown in fig. 15, according to some embodiments of the present invention. Referring to fig. 1, in the present embodiment, a substrate 10 is provided. The substrate 10 may comprise silicon or other semiconductor material, or the substrate 10 may comprise other elemental semiconductor material, such as germanium (Ge). In some embodiments, the substrate 10 may be made of a compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 10 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In the present embodiment, the substrate 10 may be a P-type substrate. In some embodiments, the substrate 10 is doped with a dopant, which may be or include boron, gallium, indium, aluminum, or combinations thereof.
Subsequently, an epitaxial layer 12 is formed on the substrate 10. In some embodiments, the formation of the epitaxial layer 12 includes forming the epitaxial layer 12 on the substrate 10 using an epitaxial growth (epi growth) process. In the present embodiment, the epitaxial layer 12 may be P-type. In some embodiments, the epitaxial growth process may be, for example, Metal Organic Chemical Vapor Deposition (MOCVD), plasma-enhanced CVD (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Liquid Phase Epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other similar processes, or a combination thereof.
Then, a mask structure 14 is formed on the epitaxial layer 12, wherein the mask structure 14 has an opening 15 exposing a portion of the epitaxial layer 12. In some embodiments, the mask structure 14 includes one or more dielectric layers. In the present embodiment, the mask structure 14 is a first oxide layer. The thickness of the first oxide layer is, for example, about 2000 angstroms to about 5000 angstroms. The material of the first oxide layer may be or include silicon dioxide or other suitable oxide. The first oxide layer can be formed by thermal oxidation (CVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like. In some embodiments, the forming of the mask structure 14 includes forming a mask material on the epitaxial layer 12, and then patterning the mask material to form the mask structure 14.
Referring to fig. 2, a trench 18 is formed by removing the exposed epitaxial layer 12 through the opening 15 using the mask structure 14 as an etching mask. The depth of the trench 18 is, for example, about 1.5 μm to about 1.9 μm. The step of removing the exposed epitaxial layer 12 may include performing an etching process using dry etching, wet etching or a combination thereof. The wet etch may include a dip etch, a spray etch, combinations thereof, or other suitable fabrication processes. The dry etching process may include a capacitively coupled plasma etching (capacitively coupled plasma etching), an inductively coupled plasma etching (inductively coupled plasma etching), an electron cyclotron resonance plasma etching (electron cyclotron resonance plasma etching), a combination thereof, or other suitable processes. The etching process may be stopped after a certain period of time without penetrating the epitaxial layer 12. Therefore, the trench 18 exposes the epitaxial layer 12 but does not expose the substrate 10.
In addition, when the epitaxial layer 12 is removed to form the trench 18, the first oxide layer as an etching mask is also partially consumed and becomes thinner. In some embodiments, the thickness of the first oxide layer (e.g., the first oxide layer shown in fig. 1) is, for example, about 2000 a to about 5000 a before removing a portion of the epitaxial layer 12 to form the trench 18. When etching a portion of the epitaxial layer 12 to form the trench 18 within the thickness range of the first oxide layer, the thickness of the first oxide layer is sufficient to protect the device under the first oxide layer from damage, and a portion of the first oxide layer remains after the trench 18 is formed. The thickness of the first oxide layer remaining after forming trench 18 is, for example, about 1500 angstroms to about 2500 angstroms.
Referring to fig. 3, a diffusion barrier layer 20 is formed on the sidewalls S1, S2 of the trench 18. In some embodiments, the diffusion barrier layer 20 comprises one or more dielectric barrier layers. In the present embodiment, the diffusion barrier layer 20 includes a barrier oxide layer 22 formed directly on the sidewalls S1, S2 and a barrier nitride layer 24 formed on the barrier oxide layer. By disposing the barrier oxide layer 22 between the barrier nitride layer 24 and the epitaxial layer 12, the problem of excessive stress generated by the direct contact between the barrier nitride layer 24 and the epitaxial layer 12 can be solved. In some embodiments, barrier oxide layer 22 may be or include silicon dioxide or other suitable oxide. The barrier nitride layer 24 may be or include silicon nitride or other suitable nitride.
In some embodiments as shown in fig. 3, barrier oxide layer 22 has a thickness of, for example, about 70 a to about 120 a, and barrier nitride layer 24 has a thickness of, for example, about 140 a to about 190 a. In other embodiments, the diffusion barrier layer 20 may be only a single layer of barrier oxide 22. The thickness of the single layer of barrier oxide 22 is, for example, about 200 a to about 300 a.
Referring to fig. 4, after forming the diffusion barrier layer 20, a conductive material 26 is formed on the epitaxial layer 12 to cover the trench 18 and the surface of the mask structure 14. Referring to fig. 5, a planarization process is then performed on the conductive material 26 to expose the upper surface of the mask structure 14. The planarization process is, for example, Chemical Mechanical Polishing (CMP).
Referring to fig. 6, an etching process is then performed on the conductive material 26 to etch the upper surface of the conductive material 26 to be lower than the upper surface of the mask structure 14 and higher than the upper surface of the epitaxial layer 12, so as to form a conductive element 28 in the trench 18, wherein the conductive element 28 has a protrusion 30 higher than the epitaxial layer 12. In some embodiments, the width of the protrusion 30 is greater than the width of the conductive feature 28 in the trench 18. In some embodiments, the protrusion 30 covers the top surface of the diffusion barrier layer 20, as shown in fig. 6.
It should be noted that, since the conductive feature 28 in the trench 18 is prone to form a seam (seam), when the height of the top surface of the conductive feature 28 is lower than or equal to the height of the top surface of the epitaxial layer 12, the seam may penetrate the top surface of the conductive feature 28, which may cause problems such as erosion during a subsequent cleaning step and short-circuiting of a subsequently formed line. Therefore, the conductive element 28 having the protrusion 30 higher than the epitaxial layer 12 of the present invention can prevent the seam in the conductive element 28 from penetrating the top surface of the conductive element 28, thereby preventing the possible problems caused by the subsequent manufacturing process. In one embodiment, the height of the protrusion 30 is 200 to 800 angstroms.
Further, the conductive features 28 may be P-type conductive features. In some embodiments, the conductive features 28 are doped with dopants. The dopant may be or include boron, gallium, indium, aluminum, or combinations thereof. It should be noted that, since the diffusion barrier layer 20 is disposed between the conductive element 28 and the epitaxial layer 12, the diffusion barrier layer 20 can prevent the dopant of the conductive element 28 from diffusing to the surroundings during the subsequent manufacturing process (such as a high temperature thermal manufacturing process), thereby avoiding affecting the electrical properties of the surrounding devices.
In addition, generally, when the semiconductor structure 100 shown in fig. 15 is subsequently manufactured in a reduced size, the diffusion of the dopants of the conductive feature 28 may have a more significant effect on the peripheral devices, however, since the diffusion barrier layer 20 is disposed between the conductive feature 28 and the epitaxial layer 12, the dopants of the conductive feature 28 may not affect the peripheral devices even if the semiconductor structure 100 is reduced in size. Thus, the size of the semiconductor structure 100 can continue to be reduced without limitation, thereby reducing the source-drain resistance (R)DSON) To improve the performance of the semiconductor structure 100.
In some embodiments, the bottom surface of the trench 18 may be a flat bottom surface or a U-shaped bottom surface. When the bottom surface of the trench 18 is a U-shaped bottom surface, the area of the conductive element 28 in direct contact with the epitaxial layer 12 may be increased to increase the flow of the operating current, thereby improving the performance of the subsequently fabricated semiconductor structure 100.
Referring to fig. 7, the mask structure 14 is removed. The removal of the mask structure 14 includes removing the mask structure 14 using hot phosphoric acid, hydrofluoric acid, or a combination thereof. In the present embodiment, the mask structure 14 is a single-layer first oxide layer. The first oxide layer is removed, for example, by using hydrofluoric acid.
Fig. 8-10 are diagrams of different stages of a step of removing the mask structure 14 according to further embodiments of the present invention. The embodiments shown in fig. 8-10 are similar to the embodiments of fig. 1-7, with the main difference being the composition and removal of the mask structure 14, and therefore only fig. 8-10 are shown for illustrative purposes.
It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same or similar reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Referring to fig. 8, in this embodiment, the mask structure 14 is a plurality of dielectric layers. The mask structure 14 includes a first oxide layer 16a and a nitride layer 32a formed on the first oxide layer 16 a. The thickness of the first oxide layer 16a is, for example, about 300 to 700 angstroms. The nitride layer 32a is, for example, about 400 angstroms to about 900 angstroms. The material of the first oxide layer 16a may be or include silicon dioxide or other suitable oxide. The nitride layer 32a may be or include silicon nitride or other suitable nitride. In some embodiments, the nitride layer 32a may be formed by Chemical Vapor Deposition (CVD), atomic layer chemical vapor deposition (ALD), or the like. In the present embodiment, the first oxide layer 16a is disposed between the nitride layer 32a and the epitaxial layer 12, so as to solve the problem of excessive stress generated by the direct contact between the nitride layer 32a and the epitaxial layer 12.
In the embodiment shown in fig. 8-10, the nitride layer 32a has a thickness of, for example, about 2500 a to about 3500 a before the step of forming the trench 18 (not shown). Within the thickness range of the nitride layer 32a, after the trench 18 is formed by performing an etching process using the nitride layer 32a as an etching mask, a portion of the nitride layer 32a and the entire first oxide layer 16a may be remained. That is, the thickness of the nitride layer 32a is within the above range, which is sufficient to prevent the devices under the nitride layer 32a from being damaged. In some embodiments, the nitride layer 32a remaining after the formation of the trench 18 is, for example, about 400 angstroms to about 900 angstroms (as shown in the nitride layer 32a of fig. 8).
With continued reference to fig. 8-10, after the trenches 18 and the conductive features 28 are formed, the mask structure 14 is then removed. The removal of the mask structure 14 includes removing a portion of the mask structure 14 and leaving a dielectric layer closest to the epitaxial layer 12, and removing the remaining mask structure 14 after removing the portion of the mask structure 14. Specifically, the removal of the mask structure 14 includes removing the nitride layer 32a and leaving the first oxide layer 16a, and then removing the first oxide layer 16 a.
In some embodiments, since the etching selectivity of the nitride layer 32a is greater than that of the first oxide layer 16a, the entire first oxide layer 16a may remain after the nitride layer 32a is removed. Then, after the nitride layer 32a is removed, the first oxide layer 16a is subsequently removed.
It is noted that in the embodiment where the thickness of the first oxide layer 16a is, for example, about 300 a to 700 a, the first oxide layer 16a can be completely removed by using a short-time (e.g., about 10 seconds to about 30 seconds) etching process, so as to achieve complete removal of the first oxide layer 16a without damaging the devices around the first oxide layer 16a, more specifically, the first oxide layer 16a can be completely removed by using a short-time etching process for about 10 seconds to about 30 seconds, so as to prevent over-etching from damaging the diffusion barrier layer 20, thereby ensuring that the diffusion barrier layer 20 can remain intact to effectively prevent the dopants of the conductive feature 28 from diffusing to the surroundings, and further preventing the electrical properties of the surrounding devices from being affected.
In one embodiment, the nitride layer 32a may be etched with hot phosphoric acid for about 50 seconds to about 100 seconds to remove all of the nitride layer 32a, and then the first oxide layer 16a may be etched with hydrofluoric acid for about 50 seconds to about 100 seconds to remove all of the first oxide layer 16 a.
Fig. 11-13 are diagrams of different stages of a step of removing the mask structure 14 according to further embodiments of the invention. The embodiment shown in fig. 11-13 is similar to the embodiment of fig. 1-7, the main difference being the composition and removal steps of the mask structure 14, and thus only fig. 11-13 are shown for illustrative purposes.
Referring to fig. 11, in still other embodiments, the mask structure 14 includes a first oxide layer 16b, a nitride layer 32b formed on the first oxide layer 16b, and a second oxide layer 34 formed on the nitride layer 32 b. The thickness of the first oxide layer 16b is, for example, about 300 to 700 angstroms. The nitride layer 32b may have a thickness of, for example, about 900 angstroms to about 1300 angstroms. The thickness of the second oxide layer 34 is, for example, about 2000 angstroms to about 4000 angstroms. The material of the first oxide layer 16b may be or include silicon dioxide or other suitable oxide. The nitride layer 32b may be or include silicon nitride or other suitable nitride. The second oxide layer 34 may be or include silicon dioxide or other suitable oxide. In the present embodiment, the first oxide layer 16b is disposed between the nitride layer 32b and the epitaxial layer 12, so as to solve the problem of excessive stress generated by the direct contact between the nitride layer 32b and the epitaxial layer 12.
In the embodiment shown in fig. 11-13, the thickness of the second oxide layer 34 is, for example, about 2500 a to about 3300 a before the step of forming the trench 18 (not shown). After the second oxide layer 34 is used as an etching mask to form the trench 18 within the thickness range of the second oxide layer 34, a portion of the second oxide layer 34, the entire nitride layer 32b, and the entire first oxide layer 16b may be remained. That is, the thickness of the second oxide layer 34 is within the above range, which is enough to prevent the elements under the second oxide layer 34 from being damaged. In some embodiments, the thickness of the second oxide layer 34 left after forming the trench 18 is, for example, about 400 angstroms to about 900 angstroms (as shown in fig. 11 for the second oxide layer 34).
With continued reference to fig. 11-13, after the trenches 18 and the conductive features 28 are formed, the mask structure 14 is removed. The removal of the mask structure 14 includes removing a portion of the mask structure 14 and leaving a dielectric layer closest to the epitaxial layer 12, and removing the remaining mask structure 14 after removing the portion of the mask structure 14. Specifically, the removal of the mask structure 14 may include removing the nitride layer 32b and the second oxide layer 34 while leaving the first oxide layer 16b, and then removing the first oxide layer 16 b.
In some embodiments, the height of the top surface of the protrusion 30 is between the top and bottom surfaces of the nitride layer 32b, so that the second oxide layer 34 on the nitride layer 32b is removed when the nitride layer 32b is removed by wet etching. In addition, in some embodiments, the etching selectivity of the nitride layer 32b is greater than that of the first oxide layer 16b, so that the entire first oxide layer 16b remains after the nitride layer 32b is removed.
Then, after removing the second oxide layer 34 and the nitride layer 32b, the first oxide layer 16b is removed. It is noted that in the embodiment where the thickness of the first oxide layer 16b is, for example, about 300 a to 700 a, the first oxide layer 16b can be completely removed by using a short-time (e.g., about 10 seconds to about 30 seconds) etching process, so as to achieve a more precise and complete removal of the first oxide layer 16b without damaging the devices surrounding the first oxide layer 16b, and more specifically, the first oxide layer 16b can be completely removed by using a short-time etching process for about 10 seconds to about 30 seconds, so as to prevent the diffusion barrier layer 20 from being damaged by over-etching, thereby ensuring that the diffusion barrier layer 20 can be kept intact to effectively prevent the dopants of the conductive feature 28 from diffusing to the surroundings, and further preventing the electrical properties of the surrounding devices from being affected.
In one embodiment, the nitride layer 32b and the second oxide layer 34 may be etched first using hot phosphoric acid for about 50 seconds to about 100 seconds to remove all of the nitride layer 32b and the second oxide layer 34, and then the first oxide layer 16b may be etched using hydrofluoric acid for about 50 seconds to about 100 seconds to remove all of the first oxide layer 16 b.
In other embodiments, the second oxide layer 34 and the nitride layer 32b may be removed sequentially, followed by removal of the first oxide layer 16 b. For example, hydrofluoric acid is used to remove the second oxide layer 34, hot phosphoric acid is used to remove the nitride layer 32b, and hydrofluoric acid is used to remove the first oxide layer 16 b.
Referring to fig. 14, a contact doped region 36 may be formed in the epitaxial layer 12 adjacent to the substrate 10 and in contact with the conductive feature 28 to enable current to pass between the conductive feature 28 and the contact doped region 36. The contact doped region 36 may be P-type. In one embodiment, a first well 38 may be formed in the epitaxial layer 12, surrounding a portion of the conductive feature 28 near the upper surface of the epitaxial layer 12. The first well region 38 may be P-type. In some embodiments, second well regions 42 may be formed in the epitaxial layer 12 on both sides of the first well region 38. The second well 42 may be N-type.
Referring to fig. 15, two gate structures 46 may be formed on the epitaxial layer 12, and the gate structures 46 are located between the first well region 38 and the adjacent second well region 42. In some embodiments, gate structure 46 may include a gate dielectric layer 48, a gate electrode 50 disposed on gate dielectric layer 48, and a gate silicide layer 52 disposed on gate electrode 50. The gate dielectric layer 48 may be silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant (high-k) dielectric material, any other suitable dielectric material, or a combination thereof. The material of the high-k dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium silicate, or zirconium aluminate. The gate electrode 50 may be a metal, a metal nitride, a conductive metal oxide, or a combination thereof. Such metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum, or hafnium. The gate suicide layer 52 may be or include nickel suicide, cobalt suicide, titanium suicide, or a combination thereof. In one embodiment, gate structure 46 may include only gate dielectric layer 48 and gate electrode 50.
In addition, a source region 40 may be formed in the first well 38, where the source region 40 surrounds a portion of the conductive feature 28 near the upper surface of the epitaxial layer 12. In the present embodiment, the diffusion barrier layer 20 contacts the source region 40 and separates the source region 40 from the conductive element 28, such that the diffusion barrier layer 20 can prevent the dopants of the conductive element 28 from diffusing into the source region 40, thereby preventing the electrical characteristics of the source region 40 from being disturbed. The source region 40 may be N-type. In some embodiments, a drain region 44 may be formed within the second well region 42. The drain region 44 may be heavily doped N-type.
In some embodiments, a spacer 54 may be formed on a sidewall of the gate structure 46, and an insulating layer 55 may be formed on an upper surface of the gate structure 46, on a surface of the spacer 54, and on an upper surface of the epitaxial layer 12, wherein the insulating layer 55 exposes the conductive feature 28, the source region 40, and the drain region 44.
In some embodiments, a conductive layer 56 may be formed on the epitaxial layer 12. Conductive layer 56 covers conductive feature 28, source region 40, gate structure 46, and a portion of second well 42 and exposes drain region 44. In some embodiments, an interlayer dielectric layer 58 and a contact plug 60 penetrating the interlayer dielectric layer 58 and connected to the drain region 44 may be formed on the epitaxial layer 12. The contact plug 60 comprises polysilicon, aluminum, gold, cobalt, copper, similar materials, or combinations thereof. Thereafter, a conductive member 62 may be formed on the interlayer dielectric layer 58, which is electrically connected to the contact plug 60. The conductive features 62 comprise copper, gold, tin, similar materials, or combinations thereof.
By one or more of the steps of the embodiments described above, the semiconductor structure 100 shown in fig. 15 can be obtained. It is noted that in the embodiment shown in fig. 15, the right portion (including source region 40) and the left portion (including source region 40) of the semiconductor structure 100, which are based on the source region 40, are each a Laterally Diffused Metal Oxide Semiconductor (LDMOS). In this embodiment, the source region 40 may serve as a common source for two ldmos devices, and the conductive element 28 is formed between the two ldmos devices, which passes through the common source of the ldmos devices, and the conductive element 28 is electrically connected to the source region 40 by the conductive layer 56. Thus, two ldmos transistors can pass current through the same source region 40 and the same conductive feature 28, thereby achieving space and manufacturing cost savings.
In summary, the semiconductor structure of the embodiment of the invention has the diffusion barrier layer disposed between the conductive component and the epitaxial layer, so that the diffusion barrier layer can block the dopant of the conductive component from diffusing to the surroundings when performing the subsequent manufacturing process (such as the high temperature thermal manufacturing process) to avoid affecting the electrical property of the surrounding devices, and the dimension of the diffused metal oxide semiconductor can be kept smaller without being limited, thereby further continuously reducing the source-drain resistance (R) valueDSON) To improve the performance of Laterally Diffused Metal Oxide (LDMOS) semiconductor.
In addition, when the height of the top surface of the conductive feature is lower than or equal to the height of the top surface of the epitaxial layer, the seam in the conductive feature may penetrate the top surface of the conductive feature, which may cause problems such as erosion during a subsequent cleaning step and short-circuiting of a subsequently formed line. Therefore, the conductive element of the semiconductor structure of the embodiment of the invention has the protruding part higher than the epitaxial layer, and the seam in the conductive element is prevented from penetrating through the top surface of the conductive element, so that the problem possibly caused by the subsequent manufacturing process is prevented.
The components of several embodiments are summarized above so that those skilled in the art can more easily understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present invention is defined by the claims of the present invention.
Claims (18)
1. A semiconductor structure, said semiconductor structure comprising:
a substrate;
an epitaxial layer disposed on the substrate;
a conductive element disposed in the epitaxial layer and having a protrusion higher than the epitaxial layer; and
a diffusion barrier layer disposed on the plurality of sidewalls of the conductive feature, wherein a bottom surface of the conductive feature is in direct contact with the epitaxial layer.
2. The semiconductor structure of claim 1 wherein said protrusion has a width greater than a width of said conductive feature in said epitaxial layer.
3. The semiconductor structure of claim 1, wherein the protrusion covers a top surface of the diffusion barrier layer.
4. The semiconductor structure of claim 1, wherein the diffusion barrier layer comprises one or more dielectric barrier layers.
5. The semiconductor structure of claim 4, wherein the diffusion barrier layer comprises a barrier oxide layer and a barrier nitride layer on the barrier oxide layer.
6. The semiconductor structure of any one of claims 1-5, further comprising:
a source region disposed in the epitaxial layer, the diffusion barrier layer contacting the source region and separating the source region and the conductive feature.
7. The semiconductor structure of any one of claims 1-5, wherein the conductive feature is disposed between two Laterally Diffused Metal Oxide Semiconductors (LDMOS), and the conductive feature passes through a common source of the LDMOS.
8. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming an epitaxial layer on the substrate;
forming a mask structure on the epitaxial layer, wherein the mask structure is provided with an opening which exposes a part of the epitaxial layer;
using the mask structure as an etching mask to remove the exposed epitaxial layer to form a trench;
forming a diffusion barrier layer on the plurality of side walls of the trench;
forming a conductive feature in the trench, the conductive feature having a protrusion above the epitaxial layer, wherein a bottom surface of the conductive feature is in direct contact with the epitaxial layer; and
removing the mask structure.
9. The method of fabricating a semiconductor structure according to claim 8, wherein a width of the protrusion is greater than a width of the conductive feature in the trench.
10. The method of claim 8, wherein the protrusion covers a top surface of the diffusion barrier layer.
11. The method of claim 8, wherein the mask structure comprises one or more dielectric layers.
12. The method of claim 11, wherein the mask structure comprises a first oxide layer and a nitride layer formed over the first oxide layer.
13. The method of claim 12, wherein said mask structure further comprises a second oxide layer formed over said nitride layer.
14. The method of claim 11, wherein the mask structure is a plurality of dielectric layers, and the removing of the mask structure comprises:
removing part of the mask structure and reserving a layer of the dielectric layer closest to the epitaxial layer; and
removing the remaining mask structure after removing a portion of the mask structure.
15. The method of claim 8, wherein the diffusion barrier layer comprises one or more dielectric barrier layers.
16. The method of fabricating a semiconductor structure according to claim 15, wherein the diffusion barrier layer comprises a barrier oxide layer and a barrier nitride layer formed over the barrier oxide layer.
17. The method of fabricating the semiconductor structure according to any one of claims 8 to 16, further comprising:
a source region is formed in the epitaxial layer, the diffusion barrier layer contacting the source region and separating the source region and the conductive feature.
18. The method as claimed in any of claims 8 to 16, wherein the conductive feature is formed between two ldmos devices and the conductive feature passes through a common source of the ldmos devices.
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