CN113363321B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN113363321B CN113363321B CN202010146921.4A CN202010146921A CN113363321B CN 113363321 B CN113363321 B CN 113363321B CN 202010146921 A CN202010146921 A CN 202010146921A CN 113363321 B CN113363321 B CN 113363321B
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- dielectric
- top surface
- gate structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 136
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 239000010410 layer Substances 0.000 claims abstract description 294
- 239000000463 material Substances 0.000 claims abstract description 132
- 239000011241 protective layer Substances 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims description 84
- 238000005530 etching Methods 0.000 claims description 62
- 238000002955 isolation Methods 0.000 claims description 54
- 230000001681 protective effect Effects 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- -1 silicon carbide nitride Chemical class 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 230000005669 field effect Effects 0.000 description 13
- 150000002500 ions Chemical class 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910001449 indium ion Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the surface of the substrate is provided with a source-drain doping layer; forming a channel column on the surface of part of the source-drain doped layer; forming an initial gate structure on the side wall surface and the top surface of the channel column; forming a first protective layer on the side surface of the initial gate structure; forming a dielectric structure on the substrate, wherein the dielectric structure covers the surface of the first protective layer, and the dielectric structure is made of a material different from that of the first protective layer; and forming a first conductive plug electrically connected with the source-drain doped layer in the dielectric structure. The semiconductor structure formed by the method has better performance.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a fin field effect transistor of a gate-all-around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin field effect transistor of the gate-around structure is further increased.
However, the performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a fin field effect transistor with a channel gate surrounding structure.
In order to solve the above technical problems, the present invention provides a semiconductor structure, including: the substrate is provided with a source-drain doping layer on the surface; the channel column is positioned on the surface of part of the source-drain doped layer; a gate structure located on a surface of the sidewall of the channel pillar, and a top surface of the gate structure is lower than a top surface of the channel pillar; the first protection layer is positioned on the surface of the side wall of the grid structure; a dielectric structure on the substrate, wherein the dielectric structure covers the surface of the first protective layer; and the first conductive plug is positioned in the dielectric structure and is electrically connected with the source-drain doping layer, and the dielectric structure is made of a material different from that of the first protective layer.
Optionally, a top surface of the first protective layer is higher than a top surface of the gate structure.
Optionally, the material of the first protective layer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
Optionally, the thickness of the first protective layer ranges from 3nm to 8 nm.
Optionally, the method further comprises: the second protective layer is positioned on the top surface of the grid structure, and the material of the second protective layer is different from the material of the dielectric structure; the second protective layer top surface is lower than the channel pillar top surface.
Optionally, the material of the second protective layer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
Optionally, the thickness of the second protective layer ranges from 5 nanometers to 30 nanometers.
Optionally, the method further comprises: and a second conductive plug electrically connected with the top of the channel column.
Optionally, the method further comprises: and the contact resistance layer is positioned at the bottom of the second conductive plug and is positioned between the bottom of the second conductive plug and the surface of the channel column.
Optionally, the method further comprises: the isolation layer is positioned on the surface of the source-drain doped layer, the gate structure is positioned on the surface of the isolation layer, and the gate structure also extends to the surface of the isolation layer at one side of the channel column; and a third conductive plug electrically connected with the gate structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a source-drain doping layer; forming a channel column on the surface of part of the source-drain doped layer; forming an initial gate structure on the side wall surface and the top surface of the channel column; forming a first protective layer on the side surface of the initial gate structure; forming a dielectric structure on the substrate, wherein the dielectric structure covers the surface of the first protective layer, and the dielectric structure is made of a material different from that of the first protective layer; and forming a first conductive plug electrically connected with the source-drain doped layer in the dielectric structure.
Optionally, the method further comprises: and before the initial gate structure is formed, forming an isolation layer on the surface of the source-drain doped layer, wherein the isolation layer covers part of the side wall surface of the channel column, and the top surface of the isolation layer is lower than the top surface of the channel column.
Optionally, the forming method of the first protection layer includes: forming a first protective material film on the surface of the isolation layer, the surface of the side wall of the initial gate structure and the surface of the top; and etching the first protective material film until the surface of the isolation layer and the top surface of the initial gate structure are exposed, so as to form the first protective layer.
Optionally, the method further comprises: etching the initial gate structure after forming the first protective layer and before forming the first conductive plug to form a gate structure, wherein the top surface of the gate structure is lower than the top surface of the channel column; the method for etching the initial gate structure comprises the following steps: forming a first dielectric layer covering the first protective layer on the surface of the isolation layer, wherein the first dielectric layer exposes the top surface of the initial gate structure; and etching the initial gate structure, forming an opening in the first dielectric layer, wherein the opening exposes the top surface and part of the side wall of the channel column and part of the side wall surface of the first protection layer, so that the initial gate structure forms a gate structure, and the top surface of the gate structure is lower than the top surface of the channel column.
Optionally, the method further comprises: after the grid structure is formed, before the first conductive plug is formed, a second protection layer is formed on the bottom surface of the opening, the second protection layer is located on the top surface of the grid structure, and the material of the second protection layer is different from that of the dielectric structure.
Optionally, the forming method of the second protection layer includes: forming a second protective material film in the opening and on the surface of the first dielectric layer, wherein the second protective material film is positioned on the top surface of the grid structure; and etching the second protective material film back to form a second protective layer on the bottom surface of the opening.
Optionally, the method further comprises: and forming a second conductive plug electrically connected with the top of the channel column in the dielectric structure.
Optionally, the method further comprises: after the opening is formed and before the second conductive plug is formed, a contact resistance layer is formed in the opening and is positioned on the top surface and the side wall surface of the channel column exposed by the opening.
Optionally, the gate structure further extends to a surface of the isolation layer on one side of the channel pillar; the method for forming the semiconductor structure further comprises the following steps: a third conductive plug is formed within the dielectric structure in electrical connection with the gate structure.
Optionally, the method further comprises: after forming the first protective layer, forming a second dielectric layer on the surface of the first dielectric layer before forming a first conductive plug, a second conductive plug and a third conductive plug, wherein the first dielectric layer and the second dielectric layer form the dielectric structure; and forming the first conductive plug, the second conductive plug and the third conductive plug in the first dielectric layer and the second dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
According to the method for forming the semiconductor structure, the first protective layer is formed on the surface of the side wall of the initial gate structure, and the material of the first protective layer is different from the material of the dielectric structure, so that the requirement that in the subsequent process of forming the first conductive plug in the dielectric structure, the dielectric structure and the first protective layer have etching selectivity is met, etching damage to the first protective layer is avoided, further etching damage to the gate structure positioned on the other side of the first protective layer is avoided, leakage current generated between the first conductive plug and the gate structure is reduced, and the performance of the formed semiconductor structure is good.
Further, the method for forming the semiconductor structure further comprises the following steps: and forming a second protective layer on the bottom surface of the opening, wherein the second protective layer is positioned on the top surface of the gate structure, and the material of the second protective layer is different from the material of the dielectric structure, so that the etching process adopted in the subsequent process of forming the first conductive plug in the dielectric structure has etching selectivity to the dielectric structure and the second protective layer, namely, the etching rate to the dielectric structure is higher than that to the second protective layer. Furthermore, in the process of etching the dielectric structure, etching damage to the second protective layer is not caused, and etching damage to the gate structure positioned at the bottom of the second protective layer is not caused, so that leakage current generated between the first conductive plug and the gate structure is reduced further, and the performance of the formed semiconductor structure is better.
Further, the method for forming the semiconductor structure further comprises the following steps: a contact resistance layer located on the exposed surface of the channel pillar; and the second conductive plug is positioned on the surface of the contact resistance layer. The contact resistance layer is beneficial to reducing the contact resistance between the second conductive plug and the top of the channel column, so that the performance of the formed semiconductor structure is better.
Drawings
FIG. 1 is a schematic diagram of a fin field effect transistor with a channel gate wrap around structure;
Fig. 2 to 13 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the fin field effect transistor with the conventional channel gate surrounding structure is to be improved.
Fig. 1 is a schematic diagram of a fin field effect transistor with a channel gate surrounding structure.
Referring to fig. 1, the method includes: a substrate 100; source-drain doped layer 101 on substrate 100; a channel pillar 102 located on the source drain doped layer 101; the isolation layer 103 is positioned on the surface of the source-drain doped layer 101 and on part of the side wall of the channel column 102, and the top surface of the isolation layer 103 is lower than the top surface of the channel column 102; a gate structure on a sidewall of channel pillar 102, the gate structure comprising: a gate dielectric layer 104, a work function layer 105 located on the gate dielectric layer 104, and a gate layer 107 located on the work function layer 105, wherein a part of the gate structure is further located on the surface of the isolation layer 103 at one side of the channel pillar 102; a dielectric layer 108 on the substrate 100, the gate structure being located within the dielectric layer 108; the first conductive structure 109 is electrically connected to the gate layer 107 on the surface of the isolation layer 103 on one side of the channel pillar 102, the second conductive structure 110 is electrically connected to the top of the channel pillar 102, and the third conductive structure 111 is electrically connected to the source/drain doped layer 101.
In the above structure, the channel pillar 102 is a channel of the semiconductor structure, and the gate structure is a surrounding gate structure, which has good gate control capability, can well inhibit short channel effect, and effectively reduces leakage current, so that the performance of the semiconductor structure is better.
However, the third conductive structure 111 is located on the surface of the source-drain doped layer 101, and the first conductive structure 109 is etched to form an opening (not shown) in the dielectric layer 108, where the opening exposes the surface of the source-drain doped layer 101; a conductive material is filled in the opening to form the third conductive structure 111. Since the third conductive structure 111 is located at one side of the gate structure, with the improvement of the integration level of the semiconductor structure, the distance between the third conductive structure 111 and the gate structure is required to be more and more shorter, so that over-etching or etching deviation is easily caused to the gate structure in the process of etching the dielectric layer 108 to form the opening, so that bridging between the formed third conductive structure 111 and the gate structure generates leakage current.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the surface of the substrate is provided with a source-drain doping layer; forming a channel column on the surface of part of the source-drain doped layer; forming an initial gate structure on the side wall surface and the top surface of the channel column; forming a first protective layer on the side surface of the initial gate structure; forming a dielectric structure on the substrate, wherein the dielectric structure covers the surface of the first protective layer; and forming a first conductive plug electrically connected with the source-drain doped layer in the dielectric structure, wherein the dielectric structure is made of a material different from that of the first protective layer. The method improves the performance of the fin field effect transistor with the channel gate surrounding structure.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 13 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, and the surface of the substrate 200 has a source-drain doped layer 210.
The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator. Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The forming process of the source/drain doped layer 210 includes an epitaxial growth process.
In this embodiment, the source-drain doped layer 210 has first doped ions therein. The type of the first doping ions is N type or P type; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or indium ions.
In this embodiment, the process of doping ions in the source/drain doped layer 210 is an in-situ doping process. In other embodiments, the process of doping ions in the source drain doped layer is an ion implantation process.
When the semiconductor structure is a P-type device, the materials of the source-drain doped layer 210 include: silicon, germanium or silicon germanium; the first doping ions are P-type ions, including boron ions or indium ions; when the semiconductor structure is an N-type device, the materials of the source-drain doped layer 210 include: silicon, gallium arsenide, or indium gallium arsenide; the first doping ions are N-type ions, including phosphorus ions or arsenic ions.
In this embodiment, the semiconductor structure is a P-type device, the material of the source-drain doped layer 210 is silicon, and the doped ions are boron ions.
Referring to fig. 3, a channel pillar 220 is formed on a portion of the surface of the source/drain doped layer 210.
The channel pillar 220 is used to form a channel with a subsequently formed gate structure.
The method for forming the channel pillar 220 includes: forming a channel material layer (not shown) on the substrate 200; forming a patterned mask layer (not shown) on the surface of the channel material layer, wherein the patterned mask layer exposes a part of the surface of the channel material layer; and etching the channel material layer by taking the patterned mask layer as a mask until the surface of the source-drain doped layer 210 is exposed, and forming the channel column 220 on the source-drain doped layer 210.
In this embodiment, the material of the channel pillar 220 comprises silicon. In other embodiments, the channel pillar material comprises semiconductor materials such as germanium, silicon germanium, gallium arsenide, and the like.
In this embodiment, the process of etching the trench material layer includes a dry etching process, which can form the trench pillars 220 with good sidewall morphology.
In this embodiment, the top surface of the channel pillar 220 further has a cover layer (not labeled), which can protect the top surface of the channel pillar 220 from the process during the process of etching the channel material film to form the channel pillar 220, thereby improving the performance of the channel pillar 220.
Referring to fig. 4, after the channel pillar 220 is formed, an isolation layer 230 is formed on the surface of the source/drain doped layer 210 to cover a portion of the sidewall surface of the channel pillar 220, and the top surface of the isolation layer 230 is lower than the top surface of the channel pillar.
The isolation layer 230 is used to electrically isolate the gate structure and the source-drain doped layer 210 that are formed later.
The method for forming the isolation layer 230 includes: forming a spacer material layer (not shown) on the substrate 200; the isolation material layer is etched back to form the isolation layer 230.
The material of the isolation layer 230 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride; the process of forming the isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the isolation layer 230 is silicon oxide. The process for forming the isolation material layer is a chemical vapor deposition process, and the chemical vapor deposition process can form the isolation material layer with compact structure and thicker thickness.
Referring to fig. 5, an initial gate structure 240 is formed on the sidewall and top surfaces of the channel pillar 220.
The initial gate structure 240 is used for subsequent gate structure formation.
Specifically, an initial gate structure 240 is formed on the surface of the isolation layer 230 to cover the sidewall surfaces and the top surfaces of the channel pillars 220.
The method for forming the initial gate structure 240 includes: forming an initial gate dielectric film (not shown) on the surface of the isolation layer 220 and on the top surface and the sidewall surface of the channel pillar 220; forming an initial work function film (not shown in the figure) on the surface of the initial gate dielectric layer; forming an initial gate electrode film (not shown) on the initial work function film surface; forming a patterned layer on the surface of the initial gate electrode film; and etching the patterned layer to expose the surface of the isolation layer 230 by using the patterned layer as a mask, so that the initial gate electrode film forms an initial gate electrode layer 243, the initial work function film forms an initial work function layer 242, the initial gate dielectric film forms an initial gate dielectric layer 241, and the initial gate electrode layer 243, the initial work function layer 242 and the initial gate dielectric layer 241 form the initial gate structure 240.
The material of the initial gate dielectric layer 241 includes a high-K (greater than 3.9) dielectric material including hafnium oxide or aluminum oxide.
The process for forming the initial gate dielectric film comprises the following steps: an atomic layer deposition process or a chemical vapor deposition process. In this embodiment, the process of forming the initial gate dielectric film includes an atomic layer deposition process, and the atomic layer deposition process can form the initial gate dielectric film with a compact structure and a thinner thickness.
The initial work function layer 242 is used for subsequent formation of a work function layer to adjust the threshold voltage of the formed semiconductor structure to meet process requirements.
The material of the initial work function layer 242 includes a P-type work function material or an N-type work function material; the P-type work function material comprises titanium nitride or tantalum nitride; the N-type work function material comprises titanium aluminum.
The initial gate electrode layer 243 includes: a metal comprising copper, tungsten or aluminum. The process of forming the initial gate electrode film includes a physical vapor deposition process or an electroplating process.
In this embodiment, before forming the initial gate dielectric film, the method further includes: the cap layer on the top surface of the channel pillar 220 is removed.
In other embodiments, before forming the initial gate dielectric film, the method further includes: and forming an interface layer on the surface of the channel column, wherein the interface layer can improve the interface defect between the initial gate dielectric layer and the channel column and improve the reliability of the formed semiconductor structure.
Next, a first protection layer is formed on the side surface of the initial gate structure 240, and the process of forming the first protection layer is shown in fig. 6 to 7.
Referring to fig. 6, a first protective material film 250 is formed on the surface of the isolation layer 230, and on the sidewall surfaces and the top surface of the initial gate structure 240.
The first protective material film 250 is used for forming a first protective layer later.
The materials of the first protective material film 250 and the subsequently formed first dielectric layer and the second dielectric layer are different, so as to ensure that the materials of the formed first protective layer and the first dielectric layer and the second dielectric layer are different.
The first dielectric layer and the second dielectric layer form a dielectric structure.
The materials of the first protective material film 250 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the first protective material film 250 is silicon nitride.
In this embodiment, the material of the first protective material film 250 and the material of the isolation layer 230 are also different, so that in the process of forming the first protective layer by subsequently etching the first protective material film 250, a larger etching selection ratio is provided between the first protective material film 250 and the isolation layer 230, so that etching loss to the isolation layer 230 is reduced, and the isolation layer 230 is ensured to have a certain thickness, so that the isolation layer 230 can have a better isolation effect, and generation of leakage current is avoided.
The forming process of the first protective material film 230 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 7, the first protective material film 250 is etched until the surface of the isolation layer 230 and the top surface of the initial gate structure 240 are exposed, thereby forming the first protective layer 251.
The thickness of the first protective layer 251 is 3 nm-8 nm.
The significance of selecting the thickness range is: if the thickness of the first protective layer 251 is less than 3 nm and the thickness of the first protective layer 251 is too thin, the over etching cannot be effectively prevented from happening in the subsequent process of forming the first conductive plug in the dielectric structure, that is, the etching damage to the gate structure positioned on the other side of the first protective layer 251 cannot be effectively avoided, bridging between the subsequently formed first conductive plug and the gate structure is easily caused, and leakage current is generated, so that the performance of the formed semiconductor structure is poor; if the thickness is greater than 8 nm, the first protection layer 251 needs to be formed into the first protection layer 251 with a relatively good thickness under the condition that the subsequent barrier effect can be satisfied, so that the process time and the process cost are increased, and the first protection layer 251 is formed by etching the first protection material film 250, which is dependent on a relatively long process time, and is unfavorable for saving the production cost.
The process of etching the first protective material film 250 includes: one or a combination of both of a dry etching process and a wet etching process.
In this embodiment, the process of etching the first protective material film 250 is an anisotropic dry etching process.
The first protection layer 251 is formed on the surface of the side wall of the initial gate structure 240, and the material of the first protection layer 251 is different from the material of the dielectric structure formed later, so that the condition that in the process of forming the first conductive plug in the dielectric structure later is satisfied, the dielectric structure and the first protection layer 251 have etching selectivity, so that etching damage to the first protection layer 251 is avoided, etching damage to the gate structure positioned on the other side of the first protection layer 251 is avoided, leakage current generated between the first conductive plug and the gate structure is reduced, and the performance of the formed semiconductor structure is better.
After forming the first protective layer 251, forming a dielectric structure on the substrate 200, wherein the dielectric structure covers the surface of the first protective layer 251; a first conductive plug electrically connected to the source-drain doped layer 210 is formed in the dielectric structure, and the dielectric structure is made of a material different from that of the first protective layer 251.
In this embodiment, after the first protection layer 251 is formed, the initial gate structure 240 is etched to form a gate structure, and the top surface of the gate structure is lower than the top surface of the channel pillar 220, and the initial gate structure is etched to form a gate structure, see fig. 8 to 9.
Referring to fig. 8, a first dielectric layer 260 is formed on the surface of the isolation layer 230 to cover the first protection layer 251, and the first dielectric layer 260 exposes the top surface of the initial gate structure 240.
The first dielectric layer 260 is used for providing support for forming the first conductive plug, the second conductive plug and the third conductive plug subsequently; on the other hand, the first dielectric layer 260 covers the sidewalls of the first protection layer 251 on the sidewall surface of the initial gate structure 240, so that the second protection layer formed later is only located on the top surface of the gate structure.
In this embodiment, the top surface of the first dielectric layer 260 is flush with the top surface of the initial gate structure 240.
The material of the first dielectric layer 260 is different from the material of the first protective layer 251.
The materials of the first dielectric layer 260 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the first dielectric layer 260 is silicon oxide.
The forming method of the first dielectric layer 260 includes: forming a first dielectric material layer (not shown) on the substrate 200, the first dielectric material layer covering the top surfaces of the channel pillars 220; the first dielectric material layer is planarized to form the first dielectric layer 260.
Referring to fig. 9, after the first dielectric layer 260 is formed, the initial gate structure 240 is etched, an opening 261 is formed in the first dielectric layer 260, and the opening 261 exposes a top surface and a portion of a sidewall surface of the channel pillar 220 and a portion of a sidewall surface of the first protection layer 251, so that the initial gate structure 240 forms a gate structure 270, and a top surface of the gate structure 270 is lower than a top surface of the channel pillar 220.
In this embodiment, the gate structure 270 further extends to the surface of the isolation layer 230 on one side of the channel pillar 220.
The process of etching the initial gate structure 240 includes: a dry etching process or a wet etching process.
In this embodiment, the process of etching the initial gate structure 260 is: and (5) a dry etching process.
Specifically, the initial gate structure 240 is etched, the initial gate dielectric layer 241 is formed into a gate dielectric layer 271, the initial work function layer 242 is formed into a work function layer 272, the initial gate electrode layer 243 is formed into a gate electrode layer 273, the gate dielectric layer 271 is located on the surface of the sidewall of the channel pillar 220 and the surface of the isolation layer 230, the work function layer 272 is located on the surface of the gate dielectric layer 271, the gate electrode layer 273 is located on the surface of the work function layer 272, and the gate dielectric layer 271, the work function layer 272 and the gate electrode layer 273 form the gate structure 270.
The gate structure 270 on the surface portion of the isolation layer 230 is used to subsequently form an electrical connection with the first conductive plug layer.
In other embodiments, the gate structure further comprises: and the interface layer is positioned on the surface of the side wall of the channel column, is positioned between the channel column and the gate dielectric layer and is used for improving interface defects, so that the reliability of the formed semiconductor structure is improved.
After the gate structure 270 is formed, a second protection layer is formed on the bottom surface of the opening 261 before the first conductive plug is formed subsequently, the second protection layer is located on the top surface of the gate structure 270, and the material of the second protection layer is different from the material of the dielectric structure. The process of forming the second protection layer is shown in fig. 10 to 11.
Referring to fig. 10, a second protective material film 280 is formed in the opening 261 and on the surface of the first dielectric layer 260, and the second protective material film 280 is located on the top surface of the gate structure 270.
The second protective material film 280 is used for forming a first protective layer later.
The second protective material film 280 is different from the first dielectric layer 260 and the second dielectric layer formed later, so as to ensure that the materials of the second protective layer formed and the first dielectric layer 260 and the second dielectric layer are different.
The first dielectric layer 260 and a subsequently formed second dielectric layer form a dielectric structure.
The material of the second protective material film 280 includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the second protective material film 280 and the first protective layer 251 are made of the same material, and are both silicon nitride.
The process of forming the second protective material film 280 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The thickness of the second protective material film 280 ranges from 5nm to 30 nm.
The significance of selecting the thickness range is: if the thickness is less than 5 nm, the thickness of the second protective material film 280 is thinner, so that the thickness of the second protective layer formed correspondingly is thinner, and the second protective layer with too thin thickness cannot effectively block over etching occurring in the subsequent process of forming the first conductive plug in the dielectric structure, that is, cannot effectively avoid etching damage to the gate structure 270 positioned at the bottom of the second protective layer, and bridging between the subsequently formed first conductive plug and the gate structure is easily caused, so that leakage current is generated, and the performance of the formed semiconductor structure is poor; if the thickness is greater than 30 nm, when the second protective layer can meet the requirement of having a better barrier effect, the second protective material film 280 with too thick thickness is formed, the process time and the process cost need to be increased, and the second protective layer is formed by etching the second protective material film 280, which correspondingly requires longer process time, so that the production cost is not beneficial to saving.
Referring to fig. 11, the second protective material film 280 is etched, and a second protective layer 281 is formed on the bottom surface of the opening 261.
The thickness of the second protective layer 281 is 5 nm to 30 nm.
The significance of selecting the thickness range is: if the thickness is less than 5nm, the second protective layer 281 is thinner and the second protective layer 281 is too thin, so that over etching cannot be effectively prevented from occurring in the subsequent process of forming the first conductive plug in the dielectric structure, that is, etching damage to the gate structure 270 at the bottom of the second protective layer 281 cannot be effectively avoided, bridging between the subsequently formed first conductive plug and the gate structure is easily caused, and leakage current is generated, so that performance of the formed semiconductor structure is poor; if the thickness is greater than 30 nm, when the second protective layer can meet the requirement of having a better barrier effect, the second protective material film 280 with a thicker thickness needs to be formed, the process time and the process cost are correspondingly increased, and the second protective material film 280 is etched to form the second protective layer 281, which correspondingly requires a longer process time, so that the production cost is not favorably saved.
The process of etching the second protective material film 280 includes: one or a combination of both of a dry etching process and a wet etching process.
In this embodiment, the process of etching the second protective material film 280 is a dry etching process. The dry etching process can better control the etching rate, thereby being beneficial to controlling the etching amount of etching the second protective material film 280 and controlling the thickness of the formed second protective layer 281.
It should be noted that the second protection layer 281 is located on the bottom surface of the opening 261, that is, the second protection layer 281 covers the top surface of the gate structure 270.
By forming the second protection layer 281 on the bottom surface of the opening 261, the second protection layer 281 is located on the top surface of the gate structure 270, and the material of the second protection layer 281 is different from the material of the dielectric structure, so that the etching process adopted in the subsequent process of forming the first conductive plug in the dielectric structure has etching selectivity to the dielectric structure and the second protection layer 281, that is, the etching rate to the dielectric structure is greater than the etching rate to the second protection layer. Furthermore, in the process of etching the dielectric structure, etching damage to the second protection layer 281 and etching damage to the gate structure 270 located at the bottom of the second protection layer 281 are not caused, which is beneficial to further reducing leakage current generated between the first conductive plug and the gate structure, so that the performance of the formed semiconductor structure is better.
Referring to fig. 12, after the second passivation layer 281 is formed, a contact resistance layer 262 is formed in the opening 261, and the contact resistance layer 262 is located on the top surface and the sidewall surface of the trench pillar 220 exposed by the opening 261.
The method for forming the contact resistance layer 262 includes: depositing a metal layer (not shown) on the bottom surface and the side wall surface of the opening 261; performing an annealing process to enable the metal layer to react with the surface of the channel column 220 at the bottom of the opening 261, so as to form the contact resistance layer 262; after the annealing process, the remaining metal layer is removed.
The materials of the contact resistance layer 262 include: titanium silicon compound.
By forming a contact resistance layer 262 on the exposed surface of the channel pillar 220, and then electrically connecting the top of the channel pillar 220 with a second conductive plug through the contact resistance layer 262. The contact resistance layer 262 is advantageous in reducing the contact resistance between the second conductive plug and the top of the channel pillar 220, resulting in a better performance of the formed semiconductor structure.
Referring to fig. 13, a second dielectric layer 290 is formed on the surface of the first dielectric layer 260, where the first dielectric layer 260 and the second dielectric layer 290 form the dielectric structure (not shown in the drawing)
The first dielectric layer 260 and the second dielectric layer 290 form a dielectric structure that provides support for forming a first conductive plug, a second conductive plug, and a third conductive plug. .
The materials of the second dielectric layer 290 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the second dielectric layer 290 is silicon oxide.
The process of forming the second dielectric layer 290 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The material of the first dielectric layer 260 is different from the material of the first protective layer 251, the material of the second dielectric layer 290 is different from the material of the first protective layer 251, and the first dielectric layer 260 and the second dielectric layer 290 form a dielectric structure, so that the material of the dielectric structure is different from the material of the first protective layer 251, and the first protective layer and the dielectric structure have an etching selection ratio in the process of forming a first conductive plug in the dielectric structure later, so that the first protective layer 251 can protect the gate structure 270 positioned on the side wall surface of the first protective layer, the gate structure 270 is not bridged by over etching, and the generation of leakage current is avoided.
Further, the material of the first dielectric layer 260 is different from the material of the second protective layer 281, the material of the second dielectric layer 290 is different from the material of the second protective layer 281, and the first dielectric layer 260 and the second dielectric layer 290 form a dielectric structure, so that the material of the dielectric structure is different from the material of the second protective layer 281, and the second protective layer 281 and the dielectric structure have an etching selectivity ratio in the process of forming the first conductive plug in the dielectric structure later, so that the second protective layer 281 can protect the gate structure 270 at the bottom of the second protective layer 281, and the gate structure 270 is not bridged due to over etching, thereby avoiding the generation of leakage current.
With continued reference to fig. 13, a first conductive plug 291 is formed in the dielectric structure and electrically connected to the source/drain doped layer 210.
With continued reference to fig. 13, a second conductive plug 292 is formed in the dielectric structure in electrical connection with the top of the channel pillar 220.
Since the contact resistance layer 262 is provided on the top surface and the sidewall surface of the channel pillar 220, the contact resistance between the second conductive plug 292 and the channel pillar 220 is advantageously reduced, thereby improving the performance of the semiconductor structure.
With continued reference to fig. 13, a third conductive plug 293 is formed within the dielectric structure in electrical connection with the gate structure 270.
Specifically, since the gate structure 270 extends to the surface of the isolation layer 230 on the side of the channel pillar 220, the third conductive plug 293 is located on the surface of the gate structure 270 on the surface of the isolation layer 230, thereby achieving electrical connection.
Correspondingly, the embodiment of the invention further provides a semiconductor structure formed by the method, please continue to refer to fig. 13, which includes: the substrate 200, the surface of the substrate 200 has a source-drain doped layer 210; channel pillars 220 located on a portion of the surface of the source-drain doped layer 210; a gate structure 270 located on a sidewall surface of the channel pillar 220, and a top surface of the gate structure 270 is lower than a top surface of the channel pillar 220; a first protection layer 251 located on a surface of a sidewall of the gate structure 270; a dielectric structure on the substrate 200, wherein the dielectric structure covers the surface of the first protection layer 251; a first conductive plug 291 is located in the dielectric structure and electrically connected to the source-drain doped layer 210, and the dielectric structure is made of a different material than the first protective layer 251.
The following detailed description refers to the accompanying drawings.
In this embodiment, the top surface of the first protection layer 251 is higher than the top surface of the gate structure 270.
The material of the first protective layer 251 includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the first protection layer 251 is silicon nitride.
The thickness of the first protective layer 251 ranges from 3 nm to 8 nm.
The semiconductor structure further includes: a second protection layer 281 located on the top surface of the gate structure 270, wherein the material of the second protection layer 281 is different from the material of the dielectric structure; the top surface of the second protection layer 281 is lower than the top surface of the channel pillar 220.
The materials of the second protective layer 281 include: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
In this embodiment, the material of the first protection layer 251 is silicon nitride.
The thickness of the second protective layer 281 ranges from 5 nm to 30 nm.
The semiconductor structure further includes: a second conductive plug 292 electrically connected to the top of the pillars of the channel 220.
In this embodiment, the semiconductor structure further includes: and a contact resistance layer 262 positioned at the bottom of the second conductive plug 292, the contact resistance layer 262 being positioned between the bottom of the second conductive plug 292 and the surface of the channel pillar 220.
Specifically, the contact resistance layer 262 is located above the top surface and sidewall surface of the channel pillar 220 of the second protective layer 281 portion.
The semiconductor structure further includes: the isolation layer 230 is located on the surface of the source-drain doped layer 210, the gate structure 270 is located on the surface of the isolation layer 230, and the gate structure 270 also extends to the surface of the isolation layer 230 on one side of the channel pillar 220; and a third conductive plug 293 electrically connected to the gate structure 270.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
the substrate is provided with a source-drain doping layer on the surface;
the channel column is positioned on the surface of part of the source-drain doped layer;
A gate structure located on a surface of the sidewall of the channel pillar, and a top surface of the gate structure is lower than a top surface of the channel pillar;
the first protection layer is positioned on the surface of the side wall of the grid structure;
The medium structure is positioned on the substrate, the material of the medium structure is silicon oxide, and the medium structure covers the surface of the first protective layer;
The first conductive plug is positioned in the dielectric structure and electrically connected with the source-drain doping layer, and the dielectric structure and the first protective layer are made of different materials, so that in the process of forming the first conductive plug in the dielectric structure, the first protective layer and the dielectric structure have etching selection ratio to protect the grid structure;
The second protection layer is positioned on the top surface of the grid structure, and the material of the second protection layer is silicon nitride; the top surface of the second protective layer is lower than the top surface of the channel column, and the thickness of the second protective layer ranges from 5 nanometers to 30 nanometers.
2. The semiconductor structure of claim 1, wherein a top surface of the first protective layer is higher than a top surface of the gate structure.
3. The semiconductor structure of claim 1, wherein the material of the first protective layer comprises: silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide oxide, or silicon oxynitride.
4. The semiconductor structure of claim 1, wherein a thickness of the first protective layer ranges from 3 nm to 8 nm.
5. The semiconductor structure of claim 1, further comprising: and a second conductive plug electrically connected with the top of the channel column.
6. The semiconductor structure of claim 5, further comprising: and the contact resistance layer is positioned at the bottom of the second conductive plug and is positioned between the bottom of the second conductive plug and the surface of the channel column.
7. The semiconductor structure of claim 1, further comprising: the isolation layer is positioned on the surface of the source-drain doped layer, the gate structure is positioned on the surface of the isolation layer, and the gate structure also extends to the surface of the isolation layer at one side of the channel column; and a third conductive plug electrically connected with the gate structure.
8. A method of forming a semiconductor structure, comprising:
Providing a substrate, wherein the surface of the substrate is provided with a source-drain doping layer;
forming a channel column on the surface of part of the source-drain doped layer;
forming an initial gate structure on the side wall surface and the top surface of the channel column;
Forming a first protective layer on the side surface of the initial gate structure;
Forming a dielectric structure on the substrate, wherein the dielectric structure is made of silicon oxide, the dielectric structure covers the surface of the first protective layer, and the dielectric structure is made of a material different from that of the first protective layer;
forming a first conductive plug electrically connected with the source-drain doped layer in the dielectric structure, wherein in the process of forming the first conductive plug in the dielectric structure, the first protective layer and the dielectric structure have etching selection ratio so as to protect the grid structure;
Forming a second protective layer on the top surface of the grid structure, wherein the second protective layer is made of silicon nitride; the top surface of the second protective layer is lower than the top surface of the channel column, and the thickness of the second protective layer ranges from 5 nanometers to 30 nanometers.
9. The method of forming a semiconductor structure of claim 8, further comprising: and before the initial gate structure is formed, forming an isolation layer on the surface of the source-drain doped layer, wherein the isolation layer covers part of the side wall surface of the channel column, and the top surface of the isolation layer is lower than the top surface of the channel column.
10. The method of forming a semiconductor structure of claim 9, wherein the method of forming a first protective layer comprises: forming a first protective material film on the surface of the isolation layer, the surface of the side wall of the initial gate structure and the surface of the top; and etching the first protective material film until the surface of the isolation layer and the top surface of the initial gate structure are exposed, so as to form the first protective layer.
11. The method of forming a semiconductor structure of claim 9, further comprising: etching the initial gate structure after forming the first protective layer and before forming the first conductive plug to form a gate structure, wherein the top surface of the gate structure is lower than the top surface of the channel column; the method for etching the initial gate structure comprises the following steps: forming a first dielectric layer covering the first protective layer on the surface of the isolation layer, wherein the first dielectric layer exposes the top surface of the initial gate structure; and etching the initial gate structure, forming an opening in the first dielectric layer, wherein the opening exposes the top surface and part of the side wall of the channel column and part of the side wall surface of the first protection layer, so that the initial gate structure forms a gate structure, and the top surface of the gate structure is lower than the top surface of the channel column.
12. The method of forming a semiconductor structure of claim 11, further comprising: after the grid structure is formed, before the first conductive plug is formed, a second protection layer is formed on the bottom surface of the opening, the second protection layer is located on the top surface of the grid structure, and the material of the second protection layer is different from that of the dielectric structure.
13. The method of forming a semiconductor structure of claim 12, wherein the method of forming a second protective layer comprises: forming a second protective material film in the opening and on the surface of the first dielectric layer, wherein the second protective material film is positioned on the top surface of the grid structure; and etching the second protective material film back to form a second protective layer on the bottom surface of the opening.
14. The method of forming a semiconductor structure of claim 12, further comprising: and forming a second conductive plug electrically connected with the top of the channel column in the dielectric structure.
15. The method of forming a semiconductor structure of claim 14, further comprising: after the opening is formed and before the second conductive plug is formed, a contact resistance layer is formed in the opening and is positioned on the top surface and the side wall surface of the channel column exposed by the opening.
16. The method of forming a semiconductor structure of claim 15, wherein the gate structure further extends to a spacer surface on a side of the channel pillar; the method for forming the semiconductor structure further comprises the following steps: a third conductive plug is formed within the dielectric structure in electrical connection with the gate structure.
17. The method of forming a semiconductor structure of claim 15, further comprising: after forming the first protective layer, forming a second dielectric layer on the surface of the first dielectric layer before forming a first conductive plug, a second conductive plug and a third conductive plug, wherein the first dielectric layer and the second dielectric layer form the dielectric structure; and forming the first conductive plug, the second conductive plug and the third conductive plug in the first dielectric layer and the second dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010146921.4A CN113363321B (en) | 2020-03-05 | 2020-03-05 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010146921.4A CN113363321B (en) | 2020-03-05 | 2020-03-05 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113363321A CN113363321A (en) | 2021-09-07 |
| CN113363321B true CN113363321B (en) | 2024-05-17 |
Family
ID=77523679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010146921.4A Active CN113363321B (en) | 2020-03-05 | 2020-03-05 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113363321B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116435275A (en) * | 2023-06-09 | 2023-07-14 | 粤芯半导体技术股份有限公司 | Semiconductor structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087706A (en) * | 1998-04-07 | 2000-07-11 | Advanced Micro Devices, Inc. | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
| US9530863B1 (en) * | 2016-04-13 | 2016-12-27 | Globalfoundries Inc. | Methods of forming vertical transistor devices with self-aligned replacement gate structures |
| US9966456B1 (en) * | 2016-11-08 | 2018-05-08 | Globalfoundries Inc. | Methods of forming gate electrodes on a vertical transistor device |
| CN108735816A (en) * | 2017-04-19 | 2018-11-02 | 格芯公司 | The air gap of the bottom source/drain region of neighbouring vertical transistor devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10388766B2 (en) * | 2017-10-23 | 2019-08-20 | International Business Machines Corporation | Vertical transport FET (VFET) with dual top spacer |
-
2020
- 2020-03-05 CN CN202010146921.4A patent/CN113363321B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087706A (en) * | 1998-04-07 | 2000-07-11 | Advanced Micro Devices, Inc. | Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
| US9530863B1 (en) * | 2016-04-13 | 2016-12-27 | Globalfoundries Inc. | Methods of forming vertical transistor devices with self-aligned replacement gate structures |
| US9966456B1 (en) * | 2016-11-08 | 2018-05-08 | Globalfoundries Inc. | Methods of forming gate electrodes on a vertical transistor device |
| CN108735816A (en) * | 2017-04-19 | 2018-11-02 | 格芯公司 | The air gap of the bottom source/drain region of neighbouring vertical transistor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113363321A (en) | 2021-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10693000B2 (en) | Semiconductor device having field-effect structures with different gate materials | |
| CN104253046B (en) | Fin formula field effect transistor and forming method thereof | |
| CN113363321B (en) | Semiconductor structure and forming method thereof | |
| CN111863933B (en) | Semiconductor structure and forming method thereof | |
| CN112151605B (en) | Semiconductor structure and forming method thereof | |
| TWI763567B (en) | Semiconductor device and method of forming the same | |
| CN113903666B (en) | Semiconductor structure and forming method thereof | |
| CN113363256B (en) | Semiconductor structure and forming method thereof | |
| CN112420831B (en) | Semiconductor structure and forming method thereof | |
| CN113314605B (en) | Semiconductor structure and forming method thereof | |
| CN113363145B (en) | Method for forming semiconductor structure | |
| CN113363154B (en) | Method for forming semiconductor structure | |
| CN113629142B (en) | Semiconductor structure and method for forming semiconductor structure | |
| CN112151381A (en) | Semiconductor structure and forming method thereof | |
| CN112992679B (en) | Semiconductor structure and forming method thereof | |
| CN112928025B (en) | Semiconductor structure and forming method thereof | |
| CN112951912B (en) | Semiconductor structure and forming method thereof | |
| CN113903805B (en) | Semiconductor structure and forming method thereof | |
| CN114068394B (en) | Method for forming semiconductor structure | |
| CN110875255B (en) | Semiconductor device and method of forming the same | |
| CN113314595B (en) | Semiconductor structure and forming method thereof | |
| CN113097137B (en) | Semiconductor structure and forming method thereof | |
| CN117637745A (en) | Semiconductor structure and forming method thereof | |
| CN116978948A (en) | Semiconductor structure and forming method thereof | |
| CN116133370A (en) | Semiconductor device and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |