CN116133370A - Semiconductor device and method for forming the same - Google Patents

Abstract

The embodiment of the invention discloses a semiconductor device and a forming method thereof, comprising the following steps: the semiconductor device comprises a substrate, a pair of source/drain regions, a metal-containing layer and a gate structure. The substrate has a trench. The source/drain regions are disposed in the substrate at both sides of the trench. A metal-containing layer is disposed below the trench, the metal-containing layer and the substrate on opposite sidewalls of the trench together forming a channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure includes: the gate dielectric layer is arranged on the opposite side wall of the groove, the buffer layer is arranged on the metal-containing layer, and the gate conducting layer is arranged on the buffer layer and is filled into the groove. The embodiment of the invention can increase the driving current to improve the performance of the semiconductor device.

Description

Semiconductor device and method for forming the same

Technical Field

Embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.

Background

Dynamic Random Access Memory (DRAM) is composed of a plurality of memory cells, each of which is substantially composed of a transistor and a capacitor, and the memory cells are generally electrically connected to each other by a word line and a bit line. In order to improve the performance and integration of the dram, the dram with embedded word lines (word lines) has been developed to achieve light, thin, short, small and better performance of the electronic products.

However, continuously increasing the integration level of semiconductor devices may cause difficulty in improving or making difficult the maintenance, or even the degradation, of the performance of dynamic random access memories. While existing dynamic random access memories have been generally desirable, they are not satisfactory in all respects.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device including: the semiconductor device comprises a substrate, a pair of source/drain regions, a metal-containing layer, a gate structure, a gate dielectric layer, a buffer layer and a gate conductive layer. The substrate has a trench. The source/drain regions are disposed in the substrate at both sides of the trench. A metal-containing layer is disposed below the trench, the metal-containing layer and the substrate on opposite sidewalls of the trench together forming a channel region of the semiconductor device. The gate structure is disposed in the trench. The gate structure includes: the gate dielectric layer is arranged on the opposite side wall of the groove, the buffer layer is arranged on the metal-containing layer, and the gate conducting layer is arranged on the buffer layer and is filled into the groove.

The embodiment of the invention provides a method for forming a semiconductor device, which comprises the following steps: forming a doped region on a substrate; etching the substrate to form a trench extending through the doped region and into the substrate; forming a gate dielectric layer on the sidewalls of the trench; forming a metal-containing layer under the trench; forming a buffer layer on the metal-containing layer; and forming a gate conductive layer on the buffer layer and filling the trench.

Drawings

FIGS. 1A, 1B, and 2 are cross-sectional views of semiconductor devices according to some embodiments of the present invention;

fig. 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 4-13 are cross-sectional views illustrating a process of forming a semiconductor device, according to some embodiments of the invention;

fig. 14-15 are cross-sectional views illustrating a process of forming a semiconductor device according to other embodiments of the present invention.

Reference numerals:

10, 20: a semiconductor device;

100: a substrate;

102: source/drain regions;

103: a groove;

104: a first trench;

118: a second trench;

105: a gate structure;

106: a gate dielectric layer;

108: a metal layer;

110: a metal-containing layer;

112: a buffer layer;

114: a barrier layer;

116: a gate conductive layer;

120: an isolation layer;

122: a first connector;

124: a second connector;

126: a bit line;

128: a capacitor;

130: an isolation structure;

DR1: a first direction;

DR2: a second direction;

l1, L2, L3, L4, L5, L6, L7: length.

Detailed Description

The following disclosure provides many examples of implementing different elements of the subject matter. Specific examples of components and configurations thereof are described below to simplify the description and are not intended to limit embodiments of the present invention. For example, where the description refers to a first element being formed over a second element, embodiments in which the first and second elements are in direct or indirect contact are contemplated, such as where additional elements are formed between the first and second elements. With respect to the terms "connected," "interconnected," and the like, two structures may be referred to as being in direct or indirect contact.

The terms "about" and "approximately" herein generally mean within + -20%, preferably + -10%, and more preferably + -5% or + -1% of a given value. Where no specific description of "about" or "approximately" is provided, a given numerical value may nevertheless imply a meaning of "about" or "approximately".

The current in the semiconductor device (e.g., on-current (I) _ON ) Or drive current (drive current)) may decrease with the miniaturization process of the semiconductor device. Lifting deviceFor example, in order to overcome the leakage phenomenon caused by the miniaturization of semiconductor devices, the threshold voltage (threshold voltage) may be increased with process margin and device design tolerances. However, increasing the threshold voltage may decrease the on-current or the drive current of the semiconductor device, thereby affecting the performance of the semiconductor device. For dynamic random access memories, lower drive currents may adversely affect the write recovery time (write recovery time, tWR) and/or the retention time (retention time), resulting in reduced performance of the dynamic random access memory.

Embodiments of the present invention provide a semiconductor device and a method of forming the same, in which a metal-containing layer is used as a part of a channel region of the semiconductor device, and a driving current can be increased to improve performance of the semiconductor device.

Fig. 1A illustrates a cross-sectional view of a semiconductor device 10 including a buried gate transistor. The semiconductor device 10 includes: a substrate 100, a pair of source/drain regions 102, a metal-containing layer 110, and a gate structure 105. As shown in fig. 1A, the substrate 100 has a trench 103. The substrate 100 may include: elemental semiconductor including silicon or germanium; a compound semiconductor including gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); alloy semiconductors including silicon germanium (SiGe) alloys, gallium arsenide phosphide (GaAsP) alloys, aluminum indium arsenide (AlInAs) alloys, aluminum gallium arsenide (AlGaAs) alloys, indium gallium arsenide (GaInAs) alloys, indium gallium phosphide (GaInP) alloys, and/or indium gallium arsenide phosphide (GaInAsP) alloys, or combinations thereof. The substrate 100 may also be a semiconductor-on-insulator (semiconductor on insulator, SOI). According to some embodiments of the present invention, the substrate 100 may be an undoped silicon substrate or a doped silicon substrate, wherein the doped silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.

Referring to fig. 1A, source/drain regions 102 are disposed in a substrate 100 on both sides of the top of a trench 103. In some embodiments of the present invention, the source/drain regions 102 may be N-doped, such as doped with phosphorus, arsenic, or antimony, and the substrate 100 may be P-doped, such as doped with boron or indium. In other embodiments, the source/drain regions 102 may be P-doped and the substrate 100 may be N-doped.

A metal-containing layer 110 is disposed below the trench 103 and surrounds the bottom of the trench 103. In some embodiments of the present invention, the metal-containing layer 110 and the substrate 100 on the opposite side walls of the trench 103 together form the channel region of the semiconductor device 10, the substrate 100 on the opposite side walls of the trench 103 being on top of the metal-containing layer 110. In other words, the metal-containing layer 110 is part of the channel region of the semiconductor device 10. The metal-containing layer 110 may include a metal silicide layer, which may include: cobalt disilicide layer, nickel silicide layer, titanium silicide layer, other metal silicide layer, or a combination of the foregoing. In some embodiments, the metal-containing layer 110 extends laterally beyond the sidewalls of the trench 103. In some embodiments, the thickness of the metal-containing layer 110 is greater than or equal to 5nm, for example, the thickness of the metal-containing layer 110 ranges from about 5nm to about 9nm, such as may be about 5nm, about 7nm, about 8nm, or about 9nm.

As shown in fig. 1A, a gate structure 105 is disposed in the trench 103. The gate structure 105 may be comprised of a gate dielectric layer 106, a buffer layer 112, and a gate conductive layer 116. A gate dielectric layer 106 is disposed on opposite sidewalls of the trench 103. In some embodiments, the bottom of the gate dielectric layer 106 is connected to the top of the metal-containing layer 110. The materials of the gate dielectric layer 106 may include: silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thickness of the gate dielectric layer 106 is less than the thickness of the metal-containing layer 110. For example, the gate dielectric layer 106 may have a thickness of about 4nm to about 6nm. In some embodiments, the metal-containing layer 110 extends laterally beyond the gate dielectric layer 106.

The buffer layer 112 is disposed on the metal-containing layer 110. In some embodiments, the buffer layer 112 is conformally disposed along the sidewalls of the gate dielectric layer 106 and the upper surface of the metal-containing layer 110, forming the buffer layer 112 with a U-shaped cross-section. The materials of the buffer layer 112 may include: silicon oxide, silicon nitride, silicon oxynitride, or high-k (dielectric constant greater than 3.9) dielectric materials. For example, the high-k dielectric material may include: hfO2, laO, alO, zrO, tiO, ta2O5, Y2O3, srTiO3, baTiO3, baZrO, hfZrO, hfLaO, hfTaO, hfSiO, hfSiON, hfTiO, laSiO, alSiO, al2O3, or a combination of the foregoing. In some embodiments, the buffer layer 112 is a single layer structure of silicon oxide. In other embodiments, the buffer layer 112 is a multi-layer structure including silicon oxide and a high-k dielectric material.

The gate conductive layer 116 is disposed on the buffer layer 112 and fills the trench 103. In some embodiments, the top surfaces of buffer layer 112 and gate conductive layer 116 are flush with each other. The gate conductive layer 116 may comprise a metal layer, a metal nitride layer, or a combination of the foregoing. The materials of the metal layer may include: aluminum, copper, tungsten, titanium, tantalum, metal alloys, other suitable materials, or combinations of the foregoing. The material of the metal nitride layer may include: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable materials, or combinations of the foregoing. In some embodiments, the gate conductive layer 116 is a multi-layer structure including a metal nitride layer (e.g., titanium nitride) and a metal layer (e.g., tungsten) disposed on the metal nitride layer. In other embodiments, the gate conductive layer 116 is a single layer structure of a single metal nitride layer. In some embodiments, the metal-containing layer 110 is U-shaped and surrounds a portion of the gate conductive layer 116, as shown in FIG. 1A. In some embodiments, a barrier layer 114 may be disposed between the buffer layer 112 and the gate conductive layer 116. For example, the materials of the barrier layer 114 may include: siN, siCN, siOC, or SiOCN.

Still referring to fig. 1A, in some embodiments, semiconductor device 10 may include an isolation layer 120. Isolation layer 120 is disposed on buffer layer 112 and gate conductive layer 116, and between source/drain regions 102. In some embodiments, the isolation layer 120 fills the top of the trench 103 and may be flush with the surface of the substrate 100. The material of spacer layer 120 may be the same or similar to the material of gate dielectric layer 106. For example, the isolation layer 120 may comprise silicon nitride.

According to some embodiments of the present invention, the channel region of the semiconductor device 10 is formed by the metal-containing layer 110 and the substrate 100 on the opposite side wall of the trench 103, and the metal-containing layer 110 in the channel region can reduce the resistance of the channel region, thereby improving the mobility of electrons to increase the on-current (or driving current) and further improve the performance of the device. In an embodiment of the present invention, the metal-containing layer 110 is part of the channel region of the semiconductor device 10, the metal-containing layer 110 and the source/drain regions 102 are separated by the substrate 100, i.e., the metal-containing layer 110 does not directly contact the source/drain regions 102. Thus, the metal-containing layer 110 does not cause shorting of the source/drain regions 102.

Referring to fig. 1A, solid dots are schematically depicted to represent electrons in an on state where they flow from one of the source/drain regions 102 through the channel region (the substrate 100 on the opposite side wall of the metal-containing layer 110 and the trench 103) to the other source/drain region 102. The metal-containing layer 110 may enhance the mobility of electrons as they flow through the channel region. As will be described below, the length of the metal-containing layer 110 may be adjusted by the process of forming the metal-containing layer 110. In some embodiments, referring to fig. 1A, the length of the metal-containing layer 110 is the sum of the lengths L1 and L3 in the first direction DR1 and the length L2 in the second direction DR2 (i.e., the length of the metal-containing layer 110 is l1+l2+l3). In some embodiments, the first direction DR1 is perpendicular to the second direction DR2. According to some embodiments, length L1 and length L3 may each be about 5nm to about 10nm. According to some embodiments, the length L2 may be about 20nm to about 30nm.

Referring to fig. 1B, electrons (solid dots) and holes (open circles) in the off state (off state) are schematically depicted, and free electrons (if present) in the metal-containing layer 110 in the off state may recombine with holes in the off state. Therefore, the use of a metal-containing layer as part of the channel region in a semiconductor device does not result in leakage or shorting.

Referring to fig. 2, according to some embodiments of the present invention, the semiconductor device 10 may belong to an application of a dynamic random access memory, wherein the gate structure 105 of the semiconductor device 10 serves as a buried word line of the dynamic random access memory, and the dynamic random access memory further comprises: first connection 122, second connection 124, isolation structure 130, bit line 126, and capacitor 128. It should be noted that for ease of understanding, the components therein may not be shown to scale. The first connection element 122 and the second connection element 124 are respectively disposed on the source/drain region 102. The materials of the first and second connectors 122, 124 may include: aluminum, copper, tungsten, other suitable materials, or a combination of the foregoing. The isolation structure 130 is disposed between the first connection 122 and the second connection 124. In some embodiments, the materials of the isolation structure 130 may include: silicon oxide, silicon nitride, or silicon oxynitride. The bit line 126 is disposed on the first connection 122. In some embodiments, the bit line 126 may be the same or similar in composition to the gate structure 105 as a buried word line. The capacitor 128 is disposed on the second connection 124. In some embodiments, the capacitor 128 is electrically connected to one of the source/drain regions 102 via the second connection 124, and the bit line 126 is electrically connected to the other source/drain region 102 via the first connection 122. In some embodiments, the metal-containing layer 110 is U-shaped and surrounds the bottom of the gate structure 105 as a buried word line.

As described above, a lower drive current may adversely affect the write recovery time (tWR) and/or the retention time (retention time) to reduce the performance of the dynamic random access memory. For example, in the on state, a lower driving current requires a longer writing time to charge the capacitor with a desired charge amount, resulting in a longer writing recovery time (i.e., slower writing speed) and thus poorer performance of the dram. On the other hand, at the same write time, a lower drive current can provide less charge and therefore less charge is left in the capacitor in the off state, resulting in a shorter retention time and reduced performance of the DRAM.

In the embodiment shown in fig. 2, the channel region of the dram is formed by the metal-containing layer 110 and the substrate 100 on the opposite side walls of the trench 103, and the metal-containing layer 110 can enhance the mobility of electrons to increase the driving current. Therefore, the write recovery time can be reduced to improve the performance of the DRAM. In addition, in some embodiments, since the driving current is increased, a larger amount of charge can be charged into the capacitor at the same writing time, and the retention time can be increased to improve the performance of the DRAM.

The metal-containing layer 110 may have other shapes or different lengths. Fig. 3 is a cross-sectional view of a semiconductor device 20 having a shorter metal-containing layer 110, in accordance with other embodiments of the present invention. For example, the length L4 of the metal-containing layer 110 may be about 20nm to about 30nm. The metal-containing layer 110 of the semiconductor device 20 is disposed only under the trench 103 and does not extend up to the sidewalls of the trench 103, and thus its length L4 may be less than the length (l1+l2+l3) of the metal-containing layer 110 of the semiconductor device 10 of fig. 1A described above. In such embodiments, the shorter metal-containing layer 110 may further provide flexibility in process and device design, and as will be described below, may simplify the process and reduce process costs. In some embodiments, the metal-containing layer 110 of the semiconductor device 20 extends laterally beyond the sidewalls of the trench 103 and/or the sidewalls of the gate dielectric layer 106.

Fig. 4-13 are cross-sectional views illustrating a process of forming a semiconductor device 10, according to some embodiments of the invention. Referring to fig. 4, the substrate 100 is blanket doped to form a doped region 102 on the substrate 100. Doping may be performed using ion implantation, implanting dopants into the substrate 100. In some embodiments, the dopant may include an N-type dopant, such as phosphorus, arsenic, antimony, or other N-type dopant. In other embodiments, the dopant may include a P-type dopant, such as boron, indium, or other P-type dopants.

Next, as shown in fig. 5, a patterning process is performed to form a first trench 104 extending through the doped region 102 into the substrate 100. In some embodiments, the patterning process may include: a photoresist layer (not shown) is formed on the doped region 102, the photoresist layer is exposed to a pattern, a post-exposure bake process is performed, the photoresist layer is developed to form a patterned mask layer, the patterned mask layer is then used to etch the doped region 102 and the substrate 100 to form the first trench 104, and the patterned mask layer is then removed. The etching process may include: dry etching (e.g., reactive Ion Etching (RIE) or plasma etching), wet etching, and/or other suitable processes. After the patterning process, the doped regions 102 on both sides of the first trench 104 may serve as source/drain regions for subsequently formed semiconductor devices.

Referring to fig. 6, a gate dielectric layer 106 is formed on sidewalls of the first trench 104. In some embodiments, the materials of the gate dielectric layer 106 may include: silicon oxide, silicon nitride, silicon oxynitride, or other dielectric material, and may be formed by any suitable method, such as: chemical vapor deposition, plasma enhanced chemical vapor deposition, in situ vapor generation (in situ steam generation, ISSG), or the like. According to some embodiments of the present invention, the gate dielectric layer 106 is formed by an in-situ vapor deposition (ISSG) method to form a silicon oxide layer on the sidewalls of the first trench 104 and on the substrate 100, and then removing the unnecessary silicon oxide layer (e.g., the silicon oxide layer on the doped region 102 or the substrate 100) by an appropriate etching process, thereby forming the gate dielectric layer 106 on the sidewalls of the first trench 104.

Fig. 7-10 illustrate a process of forming a metal-containing layer 110 under the first trench 104. Although some embodiments are described in the order of the drawings, the steps in these embodiments may be performed in other logical orders, or steps in some embodiments may be omitted. Referring first to fig. 7, the substrate 100 is etched along the first trench 104, extending the first trench 104 further downward, thereby forming an extension region 101 as shown by the dashed box of fig. 7. The process of extending the first trenches 104 may be the same or similar to the patterning process described above with respect to fig. 5.

Referring to fig. 8, a metal layer 108 is formed on the sidewalls of the gate dielectric layer 106 and the bottom and sidewalls of the extended first trench 104. The materials of the metal layer 108 may include: cobalt, nickel, titanium, or other metals, and may be formed by physical vapor deposition (e.g., sputtering), atomic layer deposition, or other processes. Referring next to fig. 9, a heat treatment process is performed to silicide the metal layer 108 with the first trench 104 and the substrate 100 under the gate dielectric layer 106 to form a metal-containing layer 110 (which may also be referred to as a metal silicide layer after the silicidation reaction). The heat treatment process may include an annealing process, such as: rapid thermal annealing (Rapid Thermal Annealing, RTA). In some embodiments, the thickness of the metal silicide layer may depend on the manner in which the annealing process is performed (e.g., one-stage or two-stage annealing) and/or parameters (e.g., annealing temperature). In some embodiments, the respective annealing temperatures are selected based on the material of the selected metal layer 108. For example, the thickness of the metal silicide layer may be adjusted to extend laterally beyond the sidewalls of the gate dielectric layer 106. In some embodiments, the material composition of the metal silicide layer depends on the material of the metal layer 108. The metal silicide layer includes: cobalt disilicide layer, nickel silicide layer, titanium silicide layer, or a combination of the foregoing. In some embodiments, referring to fig. 7 and 9, the metal-containing layer 110 is formed under and around the extension region 101, and thus, by adjusting the extension depth of the first trench 104 through the process of extending the first trench 104, the length L6 of the metal-containing layer 110 along the bottom of the extended first trench 104 and/or the lengths L5 and L7 along the sidewalls of the extended first trench 104 may be controlled. According to some embodiments, length L5 and length L7 may each be about 5nm to about 10nm. According to some embodiments, the length L6 may be about 20nm to about 30nm. As described above, the metal layer 110 may be used as a portion of the channel region of the semiconductor device 10 to increase the driving current. Therefore, the length of the metal-containing layer 110 can be adjusted by the above-mentioned process to achieve the desired driving current according to the design requirements of the device. Next, the unreacted metal layer 108 is removed, as shown in fig. 10. Unreacted metal layer 108 may be removed by an etching process. Although the description above refers to forming the metal-containing layer 110 by a metal silicidation process, the disclosure is not limited thereto. For example, in other embodiments, other ways of forming the metal-containing layer 110 may be used, such as: physical vapor deposition, metal organic chemical vapor deposition, or other suitable process.

Referring to fig. 11, a buffer layer 112 is conformally formed on the metal-containing layer 110. In some embodiments, a buffer layer 112 is also formed on sidewalls of the gate dielectric layer 106. The materials of the buffer layer 112 may include: silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Buffer layer 112 may be formed using chemical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, spin coating, one or more other suitable processes, or a combination of the preceding. The buffer layer 112 may have a single-layer structure or a multi-layer structure formed of different materials.

Referring to fig. 12, a gate conductive layer 116 is formed on the buffer layer 112 and fills the first trench 104. The gate conductive layer 116 may comprise a metal layer, a metal nitride layer, or a combination of the foregoing. The gate conductive layer 116 may be formed by physical vapor deposition, atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, other suitable processes, or a combination of the foregoing. In some embodiments, the gate conductive layer 116 may be a multi-layer structure including a metal nitride layer formed on the sidewall and bottom surfaces of the buffer layer 112 and a metal layer formed on the metal nitride layer and filling the first trench 104. In such embodiments, the metal nitride layer may have a barrier effect. In other embodiments, such as semiconductor devices having smaller trench widths for further miniaturization, a single layer of gate conductive layer 116, such as a single layer of metal nitride, may be employed due to the smaller trench widths.

In some embodiments, an optional barrier layer 114 is formed along the sidewalls and/or bottom surface of the buffer layer 112 prior to forming the gate conductive layer 116 over the buffer layer 112. The materials of the barrier layer 114 may include: siN, siCN, siOC, or SiOCN, and may be formed by chemical vapor deposition or plasma enhanced chemical vapor deposition.

Referring to fig. 13, the buffer layer 112, the barrier layer 114 (if formed), and the gate conductive layer 116 are recessed to form a second trench 118 exposing the gate dielectric layer 106. In some embodiments, the recess is an etch-back process, which may include a dry etch (e.g., reactive ion etch) or other etch process. In some embodiments, after the undercut, the top surfaces of buffer layer 112, barrier layer 114 (if formed), and gate conductive layer 116 are flush with each other. The isolation layer 120 is then filled into the second trench 118 to form the semiconductor device 10 shown in fig. 1A. In some embodiments, isolation layer 120 may be formed by depositing a layer of isolation material into second trench 118 by chemical vapor deposition or plasma enhanced chemical vapor deposition, and then removing the excess isolation material layer using a planarization process (e.g., chemical mechanical polishing or etch back).

After forming the semiconductor device 10 shown in fig. 1A, subsequent processes may be performed to form a dynamic random access memory as shown in fig. 2, in accordance with some embodiments of the present invention. Subsequent processes include (but are not limited to): forming a first connection 122 and a second connection 124 on the source/drain region 102, forming an isolation structure 130 between the first connection 122 and the second connection 124, forming a bit line 126 on the first connection 122, and forming a capacitor 128 on the second connection 124.

Fig. 14 and 15 are cross-sectional views illustrating a process of forming a semiconductor device 20 according to other embodiments of the present invention. After forming the first trench 104 as shown in fig. 6, the process of extending the trench shown in fig. 7 may be omitted, and a metal layer 108 may be formed on the sidewalls of the gate dielectric layer 106 and the bottom of the first trench 104, as shown in fig. 14. Then, a heat treatment process is performed to perform a silicidation reaction on the metal layer 108 and the substrate 100 under the first trench 104 and the gate dielectric layer 106, so as to form a metal silicide layer as shown in fig. 15. Then, a process similar to the process described above with respect to fig. 10-13 and a process of filling the isolation layer 120 are performed to form the semiconductor device 20 shown in fig. 3. In such embodiments, as described above, the drive current may be increased to improve device performance, and process cost and time may be reduced due to the omission of the process of extending the trench.

The semiconductor device and the forming method thereof provided by the embodiment of the invention comprise the step of forming the metal-containing layer as a part of a channel region of the semiconductor device, so that the driving current can be increased to improve the performance of the semiconductor device. For example, the write recovery time (tWR) may be reduced. In some embodiments, retention time (retention time) may also be increased. In addition, the method for forming the semiconductor device provided by the embodiment of the invention can adjust the length of the metal-containing layer, can achieve the required driving current according to the requirement and can increase the process margin.

The foregoing outlines features of several embodiments so that those skilled in the art to which the invention pertains may better understand the various aspects of the invention. Those skilled in the art to which the invention pertains will appreciate that they may readily use the conception and the specific structure utilized as a basis for the designing or modifying other processes and structures for carrying out the same purposes and/or advantages of the embodiments described herein. Those skilled in the art to which the invention pertains will also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims (10)

1. A semiconductor device, comprising:

a substrate having a trench;

a pair of source/drain regions disposed in the substrate on both sides of the trench;

a metal-containing layer disposed under the trench, the metal-containing layer and the substrate on opposite sidewalls of the trench together forming a channel region of the semiconductor device; and

a gate structure disposed in the trench, the gate structure comprising:

a gate dielectric layer disposed on opposite sidewalls of the trench;

a buffer layer disposed on the metal-containing layer; and

And a gate conductive layer disposed on the buffer layer and filling the trench.

2. The semiconductor device of claim 1, wherein the metal-containing layer extends laterally beyond sidewalls of the trench.

3. The semiconductor device of claim 1, wherein the metal-containing layer is U-shaped and surrounds a portion of the gate conductive layer.

4. The semiconductor device of claim 1, wherein the metal-containing layer comprises a metal silicide layer.

5. The semiconductor device of claim 4, wherein the metal silicide layer comprises: cobalt disilicide layer, nickel silicide layer, titanium silicide layer, or a combination of the foregoing.

6. The semiconductor device according to claim 1, further comprising:

a first connecting piece and a second connecting piece which are respectively arranged on the pair of source electrode/drain electrode areas;

the isolation structure is arranged between the first connecting piece and the second connecting piece;

a bit line disposed on the first connection member; and

and the capacitor is arranged on the second connecting piece.

7. A method of forming a semiconductor device, comprising:

forming a doped region on a substrate;

etching the substrate to form a first trench extending into the substrate through the doped region;

forming a gate dielectric layer on the sidewall of the first trench;

forming a metal-containing layer under the first trench;

forming a buffer layer on the metal-containing layer; and

a gate conductive layer is formed on the buffer layer and fills the first trench.

8. The method of forming a semiconductor device of claim 7, further comprising, prior to forming the metal-containing layer under the first trench:

the substrate is etched along the first trench to form an extension region, and the metal-containing layer is formed under and around the extension region.

9. The method of forming a semiconductor device of claim 7, wherein forming the metal-containing layer under the first trench comprises:

forming a metal layer on the sidewall of the gate dielectric layer and the bottom of the first trench;

performing a heat treatment process to enable the metal layer, the first groove and the substrate below the grid dielectric layer to perform a silicidation reaction so as to form a metal silicide layer; and

unreacted metal layer is removed.

10. The method of claim 9, wherein said metal silicide layer extends laterally beyond sidewalls of said gate dielectric layer.

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