CN115036370A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115036370A CN115036370A CN202110245879.6A CN202110245879A CN115036370A CN 115036370 A CN115036370 A CN 115036370A CN 202110245879 A CN202110245879 A CN 202110245879A CN 115036370 A CN115036370 A CN 115036370A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 50
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate comprising a first region and a second region; the first fin structure is positioned on the first region and the second fin structure is positioned on the second region, the first fin structure comprises a plurality of first channel layers, a first interval is formed between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers, and a second interval is formed between every two adjacent second channel layers; the first grid electrode structure is positioned on the first fin part structure of the first region and in the first interval, and the second grid electrode structure is positioned on the second fin part structure of the second region and in the first interval; the opening is positioned between the first gate structure and the second gate structure, and the top surface of the opening is higher than or flush with the top surfaces of the first gate structure and the second gate structure; and the isolation structure is positioned in the opening and seals the opening into a closed cavity. The parasitic capacitance of the semiconductor structure is reduced, and the performance is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
Fin field effect transistor (FinFET) architectures are the dominant force in the semiconductor industry today. However, with the continuous scaling of devices, when the channel length is small to a certain value, the FinFET structure cannot provide sufficient electrostatic control and sufficient driving current, so that a Nanosheet (nano-sheet) structure, that is, a Gate-Around-Gate (GAA) technology is introduced, and compared with the FinFET, the ring-Gate characteristic of the Nanosheet provides excellent channel control capability. At the same time, the excellent distribution of the channels in three dimensions allows the effective drive current per unit area to be optimized.
With the demand for smaller Track heights (Track heights), further reductions in Cell Height (Cell Height) will require smaller spacing between NMOS and PMOS devices within a standard Cell. However, for finfet and nanosheets, the process limits the spacing between these NMOS and PMOS devices. In order to expand the scalability of these devices, an innovative architecture is proposed, called the forkbolt nanosheet (forskhet) device. The forked nanoplates can be considered as natural extensions of the nanoplates. In contrast to the nanoplates, the channels of the forked nanoplates are controlled by a forked gate structure, which is achieved by introducing "dielectric walls" between the NMOS and PMOS devices prior to gate patterning. The NMOS gate trench and the PMOS gate trench are physically and electrically isolated by the wall, so that the distance between the NMOS and the PMOS is greatly reduced, and the forked nanosheets have better area and property scalability.
However, the performance of the present fork-shaped nanoplatelets still remains to be improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a semiconductor structure and a forming method thereof, and the parasitic capacitance of the semiconductor structure is reduced by forming the air side wall, so that the performance of the semiconductor structure is improved.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first region and a second region; the first fin structure comprises a plurality of first channel layers which are mutually separated along the normal direction of the surface of the substrate, a first interval is arranged between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers which are mutually separated along the normal direction of the surface of the substrate, and a second interval is arranged between every two adjacent second channel layers; the first grid structure is positioned on the first region and in the first interval, and the second grid structure is positioned on the second fin structure and in the second interval; the first source drain doping layer is positioned in the first fin structure on two sides of the first grid structure, and the second source drain doping layer is positioned in the second fin structure on two sides of the second grid structure; an opening between the first gate structure and the second gate structure, and a top surface of the opening is higher than or flush with top surfaces of the first gate structure and the second gate structure; and the isolation structure is positioned in the opening and seals the opening into a closed cavity.
Optionally, the method further includes: a dielectric structure on the substrate, the dielectric structure covering the first gate structure and the second gate structure.
Optionally, the method further includes: the first plug and the second plug are positioned on the first region, the first plug and the second plug are positioned in the medium structure, the first plug is electrically connected with the top of the first grid structure, and the second plug is electrically connected with the first source drain doping layer; and the third plug and the fourth plug are positioned in the medium structure, the third plug is electrically connected with the top of the second grid structure, and the fourth plug is electrically connected with the second source-drain doping layer.
Optionally, the dielectric structure includes a first dielectric layer and a second dielectric layer, a top surface of the first dielectric layer is flush with top surfaces of the first gate structure and the second gate structure, the second dielectric layer is located on the first dielectric layer, a top surface of the second dielectric layer is flush with top surfaces of the first plug and the third plug, the opening is located in the first dielectric layer, and a top surface of the opening is flush with a top surface of the first dielectric layer.
Optionally, the material of the first dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride; the material of the second dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride; the material of the isolation structure comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride.
Optionally, the dielectric structure includes a third dielectric layer, a top surface of the third dielectric layer is flush with top surfaces of the first plug and the third plug, the opening is located in the third dielectric layer, the opening is also located between the first plug and the third plug, and a top surface of the opening is flush with top surfaces of the first plug and the third plug.
Optionally, the material of the third dielectric layer is the same as that of the isolation structure, and includes one or a combination of a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, and silicon oxide nitride.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate comprising a first region and a second region; forming a first fin structure on the first region and a second fin structure on the second region, wherein the first fin structure comprises a plurality of first channel layers which are mutually separated along the normal direction of the surface of the substrate, a first interval is arranged between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers which are mutually separated along the normal direction of the surface of the substrate, and a second interval is arranged between every two adjacent second channel layers; forming a first gate structure on the first region and a second gate structure on the second region, the first gate structure being located on the first fin structure and within the first space, the second gate structure being located on the second fin structure and within the second space; forming an opening between the first gate structure and the second gate structure, a top surface of the opening being higher than or flush with a top surface of the first gate structure and the second gate structure; and forming an isolation structure in the opening, wherein the isolation structure seals the opening to form a closed cavity.
Optionally, before forming the first fin structure and the second fin structure, the method further includes: forming a first initial fin structure on the first region, and forming a second initial fin structure on the second region, wherein the first initial fin structure comprises a first sacrificial layer and a first channel layer which are alternately stacked along the normal direction of the surface of the substrate, the second initial fin structure comprises a second sacrificial layer and a second channel layer which are alternately stacked along the normal direction of the surface of the substrate, and an initial opening is formed between the first initial fin structure and the second initial fin structure; and forming an initial isolation structure in the initial opening.
Optionally, after the forming the initial isolation structure and before the forming the first gate structure and the second gate structure, the method further includes: forming a dummy gate structure on the first region and the second region, wherein the dummy gate structure spans the first initial fin structure, the second initial fin structure and the initial isolation structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is positioned on the side wall of the pseudo gate structure; and removing the dummy gate structure, forming a first gate opening in the first dielectric layer of the first region, wherein the first gate opening exposes a part of the sidewall surface of the first initial fin structure, and forming a second gate opening in the first dielectric layer of the second region, wherein the second gate opening exposes a part of the sidewall surface of the second initial fin structure.
Optionally, the method for forming the first fin structure and the second fin structure includes: removing the first sacrificial layer exposed by the first gate opening, and forming a first interval between adjacent first channel layers to form the first fin structure; and removing the second sacrificial layer exposed by the second gate opening, and forming a second interval between the adjacent second channel layers to form the second fin structure.
Optionally, the method for forming the first gate structure and the second gate structure includes: forming a first gate structure within the first gate opening and the first space; and forming a second gate structure in the second gate opening and the second interval.
Optionally, after the forming the dummy gate structure, the method further includes: and forming a first source-drain doping layer in the first initial fin part structures on two sides of the pseudo gate structure, and forming a second source-drain doping layer in the second initial fin part structures on two sides of the pseudo gate structure.
Optionally, the forming method of the opening includes: and removing the initial isolation structure, and forming an opening between the first gate structure and the second gate structure, wherein the top surface of the opening is flush with the top surfaces of the first gate structure and the second gate structure.
Optionally, after the forming the isolation structure, the method further includes: forming a second dielectric layer on the top surfaces of the first gate structure and the second gate structure; removing part of the second dielectric layer until the top surfaces of the first gate structure and the second gate structure are exposed, forming a first contact hole in the first area, and forming a third contact hole in the second area; removing part of the second dielectric layer and the first dielectric layer until the top surfaces of the first source-drain doping layer and the second source-drain doping layer are exposed, forming a second contact hole in the first area, and forming a fourth contact hole in the second area; and forming a first plug in the first contact hole, forming a second plug in the second contact hole, forming a third plug in the third contact hole, and forming a fourth plug in the fourth contact hole.
Optionally, after forming the first gate structure and the second gate structure, and before forming the opening, the method further includes: forming a second dielectric layer on the top surfaces of the first gate structure and the second gate structure; removing part of the second dielectric layer until the top surfaces of the first gate structure and the second gate structure are exposed, forming a first contact hole in the first area, and forming a third contact hole in the second area; removing part of the second dielectric layer and the first dielectric layer until the top surfaces of the first source-drain doping layer and the second source-drain doping layer are exposed, forming a second contact hole in the first area, and forming a fourth contact hole in the second area; and forming a first plug in the first contact hole, forming a second plug in the second contact hole, forming a third plug in the third contact hole, and forming a fourth plug in the fourth contact hole.
Optionally, the method for forming the opening includes: removing the first dielectric layer and the second dielectric layer to expose the initial isolation structure; and removing the initial isolation structure, and forming openings between the first gate structure and the second gate structure and between the first plug and the third plug, wherein the top surfaces of the openings are flush with the top surfaces of the first plug and the third plug.
Optionally, after the opening is formed, the method further includes: and forming a third dielectric layer on the substrate, wherein the top surface of the third dielectric layer is flush with the top surfaces of the first plug and the third plug, and simultaneously forming an isolation structure in the opening, wherein the isolation structure seals the opening to form a closed cavity.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the semiconductor structure in the technical scheme, the isolation structure is arranged between the first grid structure and the second grid structure, the opening is sealed by the isolation structure to form the closed cavity, the isolation structure is used for isolating devices formed on the first area and the second area, and the closed cavity is formed to be used as the air side wall under the condition that the distance between the devices is shortened.
According to the forming method of the technical scheme, after the first grid structure and the second grid structure are formed, the opening is formed between the first grid structure and the second grid structure, the top surface of the opening is higher than or flush with the top surfaces of the first grid structure and the second grid structure, then the isolation structure is formed in the opening, the opening is sealed into the sealed cavity by the isolation structure, the isolation structure is used for isolating devices formed on the first area and the second area, and the sealed cavity is formed to be used as the air side wall under the condition that the distance between the devices is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
FIGS. 2-14 are schematic views illustrating a semiconductor formation process according to an embodiment of the present invention;
fig. 15 to 20 are schematic structural views illustrating a process of forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As mentioned in the background, the performance of the current forked nanoplatelets is yet to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1, comprising: a substrate 100, the substrate 100 comprising a first region I and a second region II; a first fin structure 111 located on the first region I and a second fin structure 112 located on the second region II; a first gate structure 121 located on the first region I, the first gate structure 121 being located on the first fin structure 111 and surrounding the first fin structure 111; a second gate structure 122 located on the second region II, the second gate structure 122 being located on the second fin structure 112 and surrounding the second fin structure 112; an isolation structure 130 is located between the first gate structure 121 and the second gate structure 122, and the first gate structure 121 and the second gate structure 122 expose a top surface of the isolation structure 130.
In the semiconductor structure, the first region I and the second region II may be used to form an NMOS device or a PMOS device, and the isolation structure 130 physically and electrically isolates the NMOS gate trench from the PMOS gate trench, however, as the distance between the first region I and the second region II decreases, a parasitic capacitance may exist between the first gate structure and the second gate structure, the isolation structure is usually made of silicon nitride, silicon oxide, or the like, and the dielectric constant of the material of silicon nitride, silicon oxide, or the like is large, so that the parasitic capacitance of the semiconductor device is large, thereby affecting the electrical performance of the semiconductor device.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein an isolation structure is formed between a first gate structure and a second gate structure, the isolation structure seals an opening to form a sealed cavity, the sealed cavity is used as an air side wall, and the dielectric constant of air is small, so that the distance between a first region I and a second region II can be reduced, the parasitic capacitance between the adjacent first gate structure and the second gate structure can be significantly reduced, and the performance of the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 14 are schematic structural views illustrating a semiconductor forming process according to an embodiment of the invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 comprising a first region I and a second region II.
The substrate 200 provides a process platform for the subsequent formation of a semiconductor structure, and the first region i and the second region ii are used for the subsequent formation of MOS devices.
In this embodiment, the first region I is used to form a PMOS device, and the second region II is used to form an NMOS device; in other embodiments, the first region I may also be used to form an NMOS device, and the second region II may also be used to form a PMOS device.
In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The group III-V element multicomponent semiconductor material includes InP, GaAs, GaP, InAs, InSb, InGaAs, InGaAsP, etc.
And then, forming a first fin structure on the first region I and forming a second fin structure on the second region II, wherein the first fin structure comprises a plurality of first channel layers which are mutually separated along the normal direction of the surface of the substrate, a first interval is arranged between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers which are mutually separated along the normal direction of the surface of the substrate, and a second interval is arranged between every two adjacent second channel layers.
And forming a first grid structure on the first region I and a second grid structure on the second region II, wherein the first grid structure is positioned on the first fin structure and in the first interval, and the second grid structure is positioned on the second fin structure and in the second interval.
Please refer to fig. 2 to 10 for a process of forming the first fin structure, the second fin structure, the first gate structure, and the second gate structure.
With continued reference to fig. 2, a first initial fin structure is formed on the first region I and a second initial fin structure is formed on the second region II with an initial opening 201 therebetween.
The first preliminary fin structure includes first sacrificial layers 202 and first channel layers 203 alternately stacked in a surface normal direction of the substrate 200, and the second preliminary fin structure includes second sacrificial layers 204 and second channel layers 205 alternately stacked in the surface normal direction of the substrate 200.
The method of forming the first and second initial fin structures includes: forming a stacked material structure (not shown) on the substrate 200, the stacked material structure including sacrificial material layers for subsequently forming the first sacrificial layer 202 and the second sacrificial layer 204 and channel material layers for subsequently forming the first channel layer 203 and the second channel layer 205, which are alternately stacked in a surface normal direction of the substrate 200; forming a mask layer (not shown) on the stacked material structure, wherein the mask layer exposes the surface of a part of the sacrificial material layer, and the mask layer defines the positions and the sizes of a first initial fin structure and a second initial fin structure to be formed; and etching the sacrificial material layer, the channel material layer and the substrate 200 with partial thickness by using the mask layer as a mask, forming a first initial fin structure on the first region I, forming a second initial fin structure on the second region II, and forming an initial opening 201 between the first initial fin structure and the second initial fin structure.
In this embodiment, the first and second initial fin structures further include a portion of the substrate 200 with a patterned bottom.
The material of the sacrificial material layer comprises silicon or silicon germanium; the material of the channel material layer comprises silicon or silicon germanium. The material of the sacrificial material layer is different from the material of the channel material layer, so that the removal process has less damage to the first channel layer 203 and the second channel layer 205 when the first sacrificial layer 202 and the second sacrificial layer 204 are subsequently removed. In this embodiment, the material of the sacrificial material layer includes silicon germanium; the material of the channel material layer comprises silicon.
With continued reference to fig. 2, an isolation layer 206 is formed on the substrate 200, where the isolation layer 206 is located on sidewalls of portions of the first and second initial fin structures, and a top surface of the isolation layer 206 is lower than top surfaces of the first and second initial fin structures.
In this embodiment, the isolation layer 206 covers the sidewall surfaces of the substrate 200 with patterned bottoms of the first and second initial fin structures.
The method for forming the isolation layer 206 includes: forming an initial isolation film (not shown) on the substrate 200; planarizing the initial isolation film until top surfaces of the first initial fin structure and the second initial fin structure are exposed; the initial isolation film is continued to be etched back to form the isolation layer 206.
The material of the isolation layer 206 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, silicon oxycarbonitride, and silicon oxycarbonitride. In this embodiment, the material of the isolation layer 206 includes silicon oxide.
Referring to fig. 3, an initial isolation structure 207 is formed within the initial opening 201.
The method for forming the initial isolation structure 207 comprises the following steps: forming an initial isolation material layer (not shown) in the initial opening 201, on the surface of the first initial fin structure and on the surface of the second initial fin structure; and removing the initial isolation material layer on the surface of the first initial fin structure and the surface of the second initial fin structure, and forming an initial isolation structure 207 in the initial opening 201, wherein the top surface of the initial isolation structure 207 is flush with the top surfaces of the first initial fin structure and the second initial fin structure.
The material of the initial isolation structure 207 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. In this embodiment, the material of the initial isolation structure 207 includes silicon nitride.
The process of forming the initial layer of isolation material includes: chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), thermal treatment processes; the process for removing the initial isolation material layer on the surface of the first initial fin structure and the surface of the second initial fin structure comprises the following steps: a wet etching process or an isotropic dry etching process.
In this embodiment, the process of forming the initial isolation material layer includes an atomic layer deposition process, which has a strong hole filling capability, and can form the initial isolation material layer with a compact structure and a thin thickness in the initial opening 201, so that the formed initial isolation structure 207 provides a good support effect in subsequent processes, and the collapse of the first initial fin structure and the second initial fin structure is avoided.
Referring to fig. 4 to 6, fig. 4 is a schematic top view structure of a semiconductor structure without a first source-drain doping layer and a second source-drain doping layer, fig. 5 is a schematic cross-sectional structure along a-a direction of fig. 4, fig. 6 is a schematic cross-sectional structure along a B-B direction of fig. 4, after an initial isolation structure 207 is formed, a dummy gate structure 208 is formed on a first region I and a second region II, and the dummy gate structure 208 spans the first initial fin structure, the second initial fin structure and the initial isolation structure 207.
The dummy gate structure 208 includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) on the dummy gate dielectric layer.
In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer material may also be silicon oxynitride.
In this embodiment, the dummy gate layer is made of polysilicon.
With continued reference to fig. 4 to 6, a first source-drain doping layer 209 is formed in the first initial fin structure on both sides of the dummy gate structure 208, and a second source-drain doping layer 210 is formed in the second initial fin structure on both sides of the dummy gate structure 208.
The method for forming the first source drain doping layer 209 and the second source drain doping layer 210 includes: etching the first initial fin structure and the second initial fin structure by using the dummy gate structure 208 as a mask, forming a first source drain opening (not shown) in the first initial fin structure at two sides of the dummy gate structure 208, and forming a second source drain opening (not shown) in the second initial fin structure at two sides of the dummy gate structure 208; and forming a first source-drain doping layer 209 in the first source-drain opening, and forming a second source-drain doping layer 210 in the second source-drain opening.
In this embodiment, the first source-drain doping layer 209 and the second source-drain doping layer 210 are formed by an epitaxial growth process.
The first source drain doping layer 209 has first source drain doping ions thereinThe second source/drain doped layer 210 has second source/drain doped ions therein. When the first region i is used for forming a P-type device, the material of the first source-drain doping layer includes: silicon, germanium, or silicon germanium; the first source-drain doped ions are P-type ions including boron ions and BF 2- Ions or indium ions; the second region II is used for an N-type device, and the material of the second source-drain doping layer comprises: silicon, gallium arsenide, or indium gallium arsenide; the second source-drain doped ions are N-type ions and comprise phosphorus ions or arsenic ions.
Referring to fig. 7 and 8, the view directions of fig. 7 and 5 are the same, and the view directions of fig. 8 and 6 are the same, a first dielectric layer 211 is formed on the substrate 200, and the first dielectric layer 211 is located on the sidewall surface of the dummy gate structure 208.
The forming method of the first dielectric layer 211 comprises the following steps: forming a first dielectric material layer (not shown) on the substrate 200 and on the sidewall and top surface of the dummy gate structure 208; and flattening the first dielectric material layer until the top surface of the pseudo gate structure 208 is exposed to form the first dielectric layer 211.
The material of the first dielectric layer 211 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and the like.
In this embodiment, the material of the first dielectric layer 211 includes silicon oxide; the process for forming the first dielectric material layer comprises a chemical vapor deposition process.
In this embodiment, the method further includes: planarizing the first dielectric layer 211 and the dummy gate structure 208 until the top surface of the initial isolation structure 207 is exposed, so that the top surfaces of the dummy gate structure 208, the first dielectric layer 211 and the initial isolation structure 207 are flush; subsequent removal of the initial isolation structure may be facilitated.
Referring to fig. 9 and 10, the view directions of fig. 9 and 7 are the same, and the view directions of fig. 10 and 8 are the same, the dummy gate structure 208 is removed, a first gate structure 215 is formed on the first region I, and a second gate structure 216 is formed on the second region II.
In this embodiment, before forming the first gate structure 215 and the second gate structure 216, the method further includes: removing the dummy gate structure 208, forming a first gate opening (not shown) in the first dielectric layer 211 of the first region I, where the first gate opening exposes a portion of the sidewall surface of the first initial fin structure, forming a second gate opening in the first dielectric layer 211 of the second region II, where the second gate opening exposes a portion of the sidewall surface of the second initial fin structure; removing the first sacrificial layer 202 exposed by the first gate opening, forming a first spacer 217 between adjacent first channel layers 203, forming a first fin structure, removing the second sacrificial layer 204 exposed by the second gate opening, forming a second spacer 218 between adjacent second channel layers 205, forming the second fin structure.
In this embodiment, the process of removing the first sacrificial layer 202 and the second sacrificial layer 204 includes a wet etching process, and the wet etching process has less damage to the first channel layer 203 and the second channel layer 205.
In this embodiment, the method for forming the first gate structure 215 and the second gate structure 216 includes: forming an initial gate structure (not shown) within the first gate opening, within the first spacer 217, within the second gate opening, and within the second spacer 218, the initial gate structure spanning the first fin structure, the second fin structure, and the initial isolation structure 207; planarizing the initial gate structure until the top surface of the initial isolation structure 207 is exposed, forming a first gate structure 215 on the first region I, the first gate structure 215 being located on the first fin structure and within the first spacers 217, forming a second gate structure 216 on the second region II, the second gate structure 216 being located on the second fin structure and within the second spacers 218.
The first gate structure 215 includes a first gate dielectric layer (not shown), a first work function layer (not shown) on the first gate dielectric layer, and a first gate layer (not shown) on the first work function layer; the second gate structure 216 includes a second gate dielectric layer (not shown), a second work function layer (not shown) on the second gate dielectric layer, and a second gate layer (not shown) on the second work function layer.
The material of the first gate dielectric layer and the material of the second gate dielectric layer comprise high-dielectric-constant materials, the dielectric constant of the high-dielectric-constant materials is larger than 3.9, and the high-dielectric-constant materials comprise aluminum oxide or hafnium oxide; the material of the first work function layer comprises one or more combinations of N-type work function materials and P-type work function materials, and the material of the second work function layer comprises one or more combinations of N-type work function materials and P-type work function materials; the material of the first gate layer and the material of the second gate layer comprise a metal comprising tungsten.
Referring to fig. 11 and 12, the view directions of fig. 11 and 9 are the same, and the view directions of fig. 12 and 10 are the same, the initial isolation structure 207 is removed, an opening 219 is formed between the first gate structure 215 and the second gate structure 216, and the top surface of the opening 219 is flush with the top surfaces of the first gate structure 215 and the second gate structure 216.
In this embodiment, the opening 219 provides a space for forming an isolation structure later.
In this embodiment, the process of removing the initial isolation structure 207 includes a dry etching process.
Referring to fig. 13 and 14, the views of fig. 13 and 11 are in the same direction, and the views of fig. 14 and 12 are in the same direction, an isolation structure 220 is formed in the opening 219, and the isolation structure 220 closes the opening 219 into a closed cavity.
In this embodiment, the material of the isolation structure 220 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. The process of forming the isolation structure 220 includes a chemical vapor deposition process.
Because the distance between the first region I and the second region II is gradually reduced, the opening 219 has a high aspect ratio, when the isolation structure 220 is formed by chemical vapor deposition, because the hole filling capability is poor, when the opening 219 is not completely filled by the isolation structure 220, the opening 219 will be sealed from the top first, and the opening 219 will be sealed into a sealed cavity, which is used as an air side wall, because the dielectric constant of air is small, the parasitic capacitance between the adjacent first gate structure 215 and the second gate structure 216 can be reduced, and the performance of the formed semiconductor structure is further improved.
With continued reference to fig. 13 and 14, after the isolation structure 220 is formed, a second dielectric layer 212 is formed on the first dielectric layer 211, and the second dielectric layer 212 covers the top surfaces of the first gate structure 215, the second gate structure 216, and the isolation structure 220.
The material of the second dielectric layer 212 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. The process for forming the second dielectric layer 212 includes a chemical vapor deposition process, a thermal treatment process or an atomic layer deposition process.
After the second dielectric layer 212 is formed, the method further includes: forming a first plug 221 in the second dielectric layer 212 of the first region I, wherein the first plug 221 is electrically connected to the top of the first gate structure 215, and forming a third plug 223 in the second dielectric layer 212 of the first region I, wherein the third plug 223 is electrically connected to the top of the second gate structure 216; forming a second plug 222 in the first dielectric layer 211 and the second dielectric layer 212 in the first region I, wherein the second plug 222 is electrically connected with the top of the first source-drain doping layer 209, forming a fourth plug 224 in the first dielectric layer 211 and the second dielectric layer 212 in the second region II, and the fourth plug 224 is electrically connected with the top of the second source-drain doping layer 210.
In this embodiment, the first plug 221, the second plug 222, the third plug 223, and the fourth plug 224 are formed at the same time, and the forming method includes: removing a portion of the second dielectric layer 212 until the top surfaces of the first gate structure 215 and the second gate structure 216 are exposed, forming a first contact hole (not shown) in the first region I, and forming a third contact hole (not shown) in the second region II; removing a part of the second dielectric layer 212 and the first dielectric layer 213 until the top surfaces of the first source-drain doping layer 209 and the second source-drain doping layer 210 are exposed, forming a second contact hole (not shown) in the first region I, and forming a fourth contact hole (not shown) in the second region II; a first plug 221 is formed in the first contact hole, a second plug 222 is formed in the second contact hole, a third plug 223 is formed in the third contact hole, and a fourth plug 224 is formed in the fourth contact hole.
Correspondingly, the embodiment of the invention also provides a semiconductor structure.
Referring to fig. 13 and 14, the semiconductor structure includes: a substrate 200, the substrate 200 comprising a first region I and a second region II; the structure comprises a first fin structure and a second fin structure, wherein the first fin structure is positioned on a first region I, the second fin structure is positioned on a second region II, the first fin structure comprises a plurality of first channel layers 203 which are mutually separated along the normal direction of the surface of a substrate 200, a first interval 217 is arranged between every two adjacent first channel layers 203, the second fin structure comprises a plurality of second channel layers 205 which are mutually separated along the normal direction of the surface of the substrate 200, and a second interval 218 is arranged between every two adjacent second channel layers 205; a first gate structure 215 on the first region I and a second gate structure 216 on the second region II, the first gate structure 215 being on the first fin structure and within the first spacers 217, the second gate structure 216 being on the second fin structure and within the second spacers 218; an opening 219 (refer to fig. 11 and 12) between the first gate structure 215 and the second gate structure 216, wherein a top of the opening 219 is flush with a top surface of the first gate structure 215 and the second gate structure 216; an isolation structure 220 located within the opening 219, the isolation structure 220 enclosing the opening 219 into a closed cavity.
The opening 219 is also located between the first fin structure and the second fin structure.
The isolation structure 220 is used for isolating devices formed on the first region I and the second region II, the sealed cavity is used as an air side wall, the dielectric constant of air is small, parasitic capacitance between the first gate structure 215 and the second gate structure 216 can be reduced, and the performance of the semiconductor structure can be still ensured under the condition that the semiconductor process is further reduced.
In this embodiment, the method further includes: and an isolation layer 206 located on a portion of the sidewall surfaces of the first fin structure and the second fin structure.
In this embodiment, the method further includes: a first source-drain doping layer 209 located in the first fin structure at two sides of the first gate structure 215; and the second source-drain doping layer 210 is located in the second fin structure on two sides of the second gate structure 216.
In this embodiment, the method further includes: a first dielectric layer 211 covering the sidewall surfaces of the first gate structure 215 and the second gate structure 216, wherein the top surface of the first dielectric layer 211 is flush with the top surfaces of the first gate structure 215 and the second gate structure 216; and a second dielectric layer 212, located on the first dielectric layer 211, further covering the top surfaces of the first gate structure 215, the second gate structure 216 and the isolation structure 220.
In this embodiment, the first dielectric layer 211 and the second dielectric layer 212 form a dielectric structure.
In this embodiment, the method further includes: a first plug 221, located in the second dielectric layer 212 of the first region I, and the first plug 221 is electrically connected to the top of the first gate structure 215; a third plug 223 located in the second dielectric layer 212 of the second region II, wherein the third plug 223 is electrically connected to the top of the second gate structure 216; a second plug 222, located in the second dielectric layer 212 and the first dielectric layer 211 in the first region I, and the second plug 222 is electrically connected to the top of the first source drain doping layer 209; and a fourth plug 224 located in the second dielectric layer 212 and the first dielectric layer 211 in the second region II, wherein the fourth plug 224 is electrically connected to the top of the second source drain doped layer 210.
Fig. 15 to 20 are schematic structural views illustrating a process of forming a semiconductor structure according to another embodiment of the present invention.
Referring to fig. 15 and 16, fig. 15 is a schematic structural view based on fig. 9, fig. 16 is a schematic structural view based on fig. 10, a view direction of fig. 15 is the same as that of fig. 9, and a view direction of fig. 16 is the same as that of fig. 10, a second dielectric layer 312 is formed on the first dielectric layer 211, and the second dielectric layer 312 covers top surfaces of the first gate structure 215, the second gate structure 216 and the initial isolation structure 207; forming a first plug 321 in the second dielectric layer 312 in the first region I, wherein the first plug 321 is electrically connected to the top of the first gate structure 215, and forming a third plug 323 in the second dielectric layer 312 in the first region I, wherein the third plug 323 is electrically connected to the top of the second gate structure 216; forming a second plug 322 in the first dielectric layer 211 and the second dielectric layer 312 in the first region I, where the second plug 322 is electrically connected to the top of the first source-drain doping layer 209, forming a fourth plug 324 in the first dielectric layer 211 and the second dielectric layer 312 in the second region II, and where the fourth plug 324 is electrically connected to the top of the second source-drain doping layer 210.
Referring to fig. 17 and 18, the view direction of fig. 17 is the same as that of fig. 15, the view direction of fig. 18 is the same as that of fig. 16, the first dielectric layer 211, the second dielectric layer 312 and the initial isolation structure 207 are removed, an opening 319 is formed, the top surface of the opening 319 is higher than the top surfaces of the first gate structure 215 and the second gate structure 216, and is not only located between the first gate structure 215 and the second gate structure 216, but also located between the first plug 321 and the third plug 323 and between the second plug 322 and the fourth plug 324.
In this embodiment, the top surface of the opening 319 is flush with the top surfaces of the first, second, third and fourth plugs 321, 322, 323 and 324.
In this embodiment, the process of removing the first dielectric layer 211, the second dielectric layer 312 and the initial isolation structure 207 includes a dry etching process.
Referring to fig. 19 and 20, the view of fig. 19 is oriented in the same direction as fig. 17, and the view of fig. 20 is oriented in the same direction as fig. 18, and an isolation structure 320 is formed in the opening 319, and the isolation structure 320 seals the opening 319 into a closed cavity.
In this embodiment, a third dielectric layer 313 is further formed on the substrate 200 at the same time as the isolation structure 320 is formed, and the third dielectric layer 313 covers the sidewalls and the top surfaces of the first gate structure 215 and the second gate structure 216.
In this embodiment, the isolation structure 320 and the third dielectric layer 313 are made of the same material.
The materials of the isolation structure 320 and the third dielectric layer 313 include a low-k dielectric material (low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), or a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride and silicon oxycarbide.
In this embodiment, the process of forming the isolation structure 320 and the third dielectric layer 313 includes a chemical vapor deposition process.
In this embodiment, when the third dielectric layer 313 is formed on the substrate 200, the opening 319 is simultaneously filled with the material of the third dielectric layer 313, and since the opening 319 has a high aspect ratio, the filling capability of the material forming the isolation structure 320 is limited, when the opening 319 is not completely filled, the top of the opening 319 is now sealed, and the opening 319 is sealed to form a sealed cavity, and the sealed cavity is used as an air sidewall.
In this embodiment, the first plug 321, the second plug 322, the third plug 323, and the fourth plug 324 are formed first, and then the initial isolation structure 207 is removed to form an opening, on one hand, the formed opening can be located between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324, so that the subsequently formed air sidewall can reduce the parasitic capacitance between the first gate structure 215 and the second gate structure 216, and can also reduce the parasitic capacitance between the first plug 321 and the third plug 323, and between the second plug 322 and the fourth plug 324, thereby further improving the performance of the semiconductor structure; on the other hand, the alignment problem in the process of forming the first plug 321, the second plug 322, the third plug 323 and the fourth plug 324 can be avoided, and short circuit is not easily caused in the process.
Correspondingly, the embodiment of the invention also provides a semiconductor structure.
Referring to fig. 19 and 20, the semiconductor structure includes: a substrate 200, the substrate 200 comprising a first region I and a second region II; the structure comprises a first fin structure and a second fin structure, wherein the first fin structure is positioned on a first region I, the second fin structure is positioned on a second region II, the first fin structure comprises a plurality of first channel layers 203 which are mutually separated along the normal direction of the surface of a substrate 200, a first interval 217 is arranged between every two adjacent first channel layers 203, the second fin structure comprises a plurality of second channel layers 205 which are mutually separated along the normal direction of the surface of the substrate 200, and a second interval 218 is arranged between every two adjacent second channel layers 205; a first gate structure 215 on the first region I and a second gate structure 216 on the second region II, the first gate structure 215 being on the first fin structure and within the first spacers 217, the second gate structure 216 being on the second fin structure and within the second spacers 218; an opening 319 (refer to fig. 17 and 18) between the first gate structure 215 and the second gate structure 216, wherein a top of the opening 219 is higher than top surfaces of the first gate structure 215 and the second gate structure 216; an isolation structure 320 located within the opening 319, and the isolation structure 320 encloses the opening 319 into a closed cavity.
In this embodiment, the method further includes: and an isolation layer 206 located on a portion of the sidewall surfaces of the first fin structure and the second fin structure.
In this embodiment, the method further includes: a first source drain doping layer 209 located in the first fin structure at both sides of the first gate structure 215; and the second source-drain doping layer 210 is located in the second fin structure on two sides of the second gate structure 216.
In this embodiment, the method further includes: and a third dielectric layer 313 covering the sidewall surfaces and the top surfaces of the first gate structure 215 and the second gate structure 216, wherein the top surface of the third dielectric layer 313 is flush with the top surfaces of the first plug 321, the second plug 322, the third plug 323 and the fourth plug 324.
In this embodiment, the third dielectric layer 312 constitutes a dielectric structure.
In this embodiment, the method further includes: a first plug 321 located in the third dielectric layer 313 in the first region I, wherein the first plug 321 is electrically connected to the top of the first gate structure 215; a third plug 323 located in the third dielectric layer 313 of the second region II, wherein the third plug 323 is electrically connected to the top of the second gate structure 216; a second plug 322, located in the third dielectric layer 313 in the first region I, and the second plug 322 is electrically connected to the top of the first source drain doping layer 209; and a fourth plug 324 located in the third dielectric layer 313 in the second region II, wherein the fourth plug 324 is electrically connected to the top of the second source-drain doped layer 210.
The openings 319 are also located between the first and third plugs 321, 323, and between the second and fourth plugs 322, 324.
The isolation structure 320 is used for isolating devices formed on the first region I and the second region II, the sealed cavity is used as an air sidewall, the dielectric constant of air is small, parasitic capacitance between the first gate structure 215 and the second gate structure 216 can be reduced, parasitic capacitance between the first plug 321 and the third plug 323 and parasitic capacitance between the second plug 322 and the fourth plug 324 can be reduced, and the performance of the formed semiconductor structure is further improved under the condition that the semiconductor process is further reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
a substrate comprising a first region and a second region;
the first fin structure comprises a plurality of first channel layers which are mutually separated along the normal direction of the surface of the substrate, a first interval is arranged between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers which are mutually separated along the normal direction of the surface of the substrate, and a second interval is arranged between every two adjacent second channel layers;
the first grid structure is positioned on the first region and in the first interval, and the second grid structure is positioned on the second fin structure and in the second interval;
the first source-drain doping layer is positioned in the first fin part structures on two sides of the first grid structure, and the second source-drain doping layer is positioned in the second fin part structures on two sides of the second grid structure;
an opening between the first gate structure and the second gate structure, and a top surface of the opening is higher than or flush with top surfaces of the first gate structure and the second gate structure; and the isolation structure is positioned in the opening and seals the opening into a closed cavity.
2. The semiconductor structure of claim 1, further comprising: a dielectric structure on the substrate, the dielectric structure covering the first gate structure and the second gate structure.
3. The semiconductor structure of claim 2, further comprising: the first plug and the second plug are positioned on the first region, the first plug and the second plug are positioned in the medium structure, the first plug is electrically connected with the top of the first grid structure, and the second plug is electrically connected with the first source drain doping layer; and the third plug and the fourth plug are positioned in the medium structure, the third plug is electrically connected with the top of the second grid structure, and the fourth plug is electrically connected with the second source-drain doping layer.
4. The semiconductor structure of claim 3, wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer, a top surface of the first dielectric layer is flush with a top surface of the first gate structure and the second gate structure, the second dielectric layer is on the first dielectric layer, a top surface of the second dielectric layer is flush with a top surface of the first plug and the third plug, the opening is in the first dielectric layer, and a top surface of the opening is flush with a top surface of the first dielectric layer.
5. The semiconductor structure of claim 4, wherein a material of the first dielectric layer comprises one or a combination of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbo nitride, and silicon carbo nitride oxide; the material of the second dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride; the material of the isolation structure comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon oxycarbonitride.
6. The semiconductor structure of claim 3, wherein the dielectric structure comprises a third dielectric layer having a top surface that is flush with top surfaces of the first and third plugs, wherein the opening is located within the third dielectric layer, wherein the opening is also located between the first and third plugs, and wherein the top surface of the opening is flush with the top surfaces of the first and third plugs.
7. The semiconductor structure of claim 6, wherein the material of the third dielectric layer is the same as the material of the isolation structure and comprises a combination of one or more of a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride.
8. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region and a second region;
forming a first fin structure on the first region and a second fin structure on the second region, wherein the first fin structure comprises a plurality of first channel layers which are mutually separated along the normal direction of the surface of the substrate, a first interval is arranged between every two adjacent first channel layers, the second fin structure comprises a plurality of second channel layers which are mutually separated along the normal direction of the surface of the substrate, and a second interval is arranged between every two adjacent second channel layers;
forming a first gate structure on the first region and a second gate structure on the second region, the first gate structure being on the first fin structure and in the first space, the second gate structure being on the second fin structure and in the second space;
forming an opening between the first gate structure and the second gate structure, a top surface of the opening being higher than or flush with a top surface of the first gate structure and the second gate structure;
and forming an isolation structure in the opening, wherein the isolation structure seals the opening to form a closed cavity.
9. The method of forming a semiconductor structure of claim 8, further comprising, prior to forming the first fin structure and the second fin structure: forming a first initial fin structure on the first region, and forming a second initial fin structure on the second region, wherein the first initial fin structure comprises a first sacrificial layer and a first channel layer which are alternately stacked along the normal direction of the surface of the substrate, the second initial fin structure comprises a second sacrificial layer and a second channel layer which are alternately stacked along the normal direction of the surface of the substrate, and an initial opening is formed between the first initial fin structure and the second initial fin structure; and forming an initial isolation structure in the initial opening.
10. The method of forming a semiconductor structure of claim 9, wherein after forming the initial isolation structure and before forming the first gate structure and the second gate structure, further comprising: forming a dummy gate structure on the first region and the second region, wherein the dummy gate structure spans the first initial fin structure, the second initial fin structure and the initial isolation structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is positioned on the side wall of the pseudo gate structure; and removing the dummy gate structure, forming a first gate opening in the first dielectric layer of the first region, wherein the first gate opening exposes a part of the sidewall surface of the first initial fin structure, and forming a second gate opening in the first dielectric layer of the second region, wherein the second gate opening exposes a part of the sidewall surface of the second initial fin structure.
11. The method of forming a semiconductor structure of claim 10, wherein the first fin structure and the second fin structure are formed by a method comprising: removing the first sacrificial layer exposed by the first gate opening, and forming a first interval between adjacent first channel layers to form the first fin structure; and removing the second sacrificial layer exposed by the second gate opening, and forming a second interval between the adjacent second channel layers to form the second fin structure.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the first gate structure and the second gate structure comprises: forming a first gate structure in the first gate opening and the first space; and forming a second gate structure in the second gate opening and the second interval.
13. The method of forming a semiconductor structure of claim 10, further comprising, after forming the dummy gate structure: and forming a first source drain doping layer in the first initial fin structure on two sides of the pseudo gate structure, and forming a second source drain doping layer in the second initial fin structure on two sides of the pseudo gate structure.
14. The method of forming a semiconductor structure of claim 13, wherein the method of forming the opening comprises: and removing the initial isolation structure, and forming an opening between the first gate structure and the second gate structure, wherein the top surface of the opening is flush with the top surfaces of the first gate structure and the second gate structure.
15. The method of forming a semiconductor structure of claim 14, further comprising, after forming the isolation structure: forming a second dielectric layer on the top surfaces of the first gate structure and the second gate structure; removing part of the second dielectric layer until the top surfaces of the first gate structure and the second gate structure are exposed, forming a first contact hole in the first area, and forming a third contact hole in the second area; removing part of the second dielectric layer and the first dielectric layer until the top surfaces of the first source-drain doping layer and the second source-drain doping layer are exposed, forming a second contact hole in the first area, and forming a fourth contact hole in the second area; and forming a first plug in the first contact hole, forming a second plug in the second contact hole, forming a third plug in the third contact hole, and forming a fourth plug in the fourth contact hole.
16. The method of forming a semiconductor structure of claim 13, wherein after forming the first gate structure and the second gate structure, and before forming the opening, further comprising: forming a second dielectric layer on the top surfaces of the first gate structure and the second gate structure; removing part of the second dielectric layer until the top surfaces of the first grid structure and the second grid structure are exposed, forming a first contact hole in the first area, and forming a third contact hole in the second area; removing part of the second dielectric layer and the first dielectric layer until the top surfaces of the first source-drain doping layer and the second source-drain doping layer are exposed, forming a second contact hole in the first area, and forming a fourth contact hole in the second area; and forming a first plug in the first contact hole, forming a second plug in the second contact hole, forming a third plug in the third contact hole, and forming a fourth plug in the fourth contact hole.
17. The method of forming a semiconductor structure of claim 16, wherein the method of forming the opening comprises: removing the first dielectric layer and the second dielectric layer to expose the initial isolation structure; and removing the initial isolation structure, and forming openings between the first gate structure and the second gate structure and between the first plug and the third plug, wherein the top surfaces of the openings are flush with the top surfaces of the first plug and the third plug.
18. The method of forming a semiconductor structure of claim 17, further comprising, after forming the opening: and forming a third dielectric layer on the substrate, wherein the top surface of the third dielectric layer is flush with the top surfaces of the first plug and the third plug, and meanwhile, an isolation structure is formed in the opening and seals the opening to form a closed cavity.
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