CN101339904A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
CN101339904A
CN101339904A CNA2008101096472A CN200810109647A CN101339904A CN 101339904 A CN101339904 A CN 101339904A CN A2008101096472 A CNA2008101096472 A CN A2008101096472A CN 200810109647 A CN200810109647 A CN 200810109647A CN 101339904 A CN101339904 A CN 101339904A
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film
silicide layer
heat treatment
semiconductor
metal
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CN101339904B (en
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冈田茂业
二濑卓也
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Renesas Electronics Corp
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Renesas Technology Corp
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Priority claimed from JP2007182031A external-priority patent/JP2009021331A/en
Priority claimed from JP2008106606A external-priority patent/JP2009260004A/en
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Publication of CN101339904A publication Critical patent/CN101339904A/en
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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention can promotes performance of semiconductor device for forming metal silicide layer using self-alignment silicide treatment process. The method comprises: forming n<+> type semiconductor area 9b and p<+> type semiconductor area 10b for grid insulated film 7, grid electrode 8a, 8b, source-drain, then forming metal film and isolation film on semiconductor substrate 1, performing first heat treatment to react metal film with grid electrode 8a, 8b, n <+> type semiconductor area 9b and p <+> semiconductor area 10b, then forming metal silicide layer 41 constituted by monosilicide MSi of metal M for forming metal film, then removing isolation film and unreacted metal film, performing second heat treatment, stabilizing metal silicide layer, then the processing for making temperature of semiconductor substrate 1 higher than that of the second heat treatment being not performed, making heat treatment temperature of second heat treatment lower than that when crystal lattic size of disilicide MSi<2> of metal element M is equal to crystal lattice size of semiconductor substrate 1.

Description

The manufacture method of semiconductor device
Technical field
The present invention relates to the manufacture method of semiconductor device, particularly effectively be applicable to the technology of making semiconductor element with metal silicide layer.
Background technology
Along with the highly integrated development of semiconductor device, field-effect transistor (MISFET: metal-insulator-semiconductor field effect transistor (Metal Insulator SemiconductorField Effect Transistor)) according to scaled standard (scaling rule) by miniaturization, but the resistance of grid or source drain increases, even there is the problem that the miniaturization field-effect transistor also can't high speed operation.So, studying a kind of self-aligned silicide (salicide) technology at present, promptly on the conducting film that constitutes grid and the surface of semiconductor regions that constitutes source drain by the low-resistance metal silicide layer of autoregistration (Self-alignment) formation for example nickel silicide layer or cobalt suicide layer etc., reduce the resistance of grid or source drain thus.
The spy opens the manufacture method that 2005-109504 communique (patent documentation 1) discloses a kind of semiconductor element, and this method comprised with the next stage: the stage that forms metal level on gate electrode and regions and source; Utilize the Ar plasma that above-mentioned metal level is carried out the surface-treated stage; The silicon substrate that has formed above-mentioned metal level is carried out annealing in process under the temperature of regulation, form the stage of silicide film.
The spy opens 2006-294861 communique (patent documentation 2) and discloses the method that forms the containing metal film on the surface that contains the Si part, this method comprises utilizes high-frequency plasma physical property ground to handle the Surface Physical surface treatment procedure that contains the Si part, utilize the reactant gas chemical treatment to implement the chemical surface treatment procedure on the surface that contains Si part of plasma treatment, implementing the film formation process that the chemical surface-treated contains formation containing metal film on the Si part.
The spy opens 2003-119564 communique (patent documentation 3) and discloses following technology: remove the natural oxide film that is present in the Si substrate surface in plasma CVD equipment chamber (chamber) after, the Si substrate of this not having be removed natural oxide film places atmosphere, but transferring to the same indoor etching and the film forming of carrying out continuously of optimum condition, form the film that contains refractory metal having removed on the Si substrate of natural oxide film.
Te Kaiping 7-38104 communique (patent documentation 4) discloses following technology: deposit Ni film and metallic compound film successively having formed as on whole of the Si substrate of the diffusion layer of source drain, next, make Ni and Si reaction by heat treatment, on surface, form nickel silicide as the diffusion layer of source drain, then, by removing unreacted Ni and metallic compound film, on nickel silicide, not form the mode of insulant stably with the nickel silicide film forming.
[patent documentation 1] spy opens the 2005-109504 communique
[patent documentation 2] spy opens the 2006-294861 communique
[patent documentation 3] spy opens the 2003-119564 communique
[patent documentation 4] spy opens flat 7-38104 communique
Summary of the invention
According to the inventor's research, following discovery has been arranged.
The aspect that causes carrying out low resistanceization from miniaturization considers, ideal when ratio is made up of cobalt silicide when utilizing self-aligned silicide to handle metal silicide layer that (salicide process) form to be made up of nickel silicide on the conducting film that constitutes grid and the surface that constitutes the semiconductor regions of source drain.By making metal silicide layer is nickel silicide rather than cobalt silicide, can make the resistance of metal silicide layer lower, and can further reduce the diffusion resistance of source drain or contact resistance etc.By making metal silicide layer is that nickel silicide rather than cobalt silicide can form thin metal silicide layer, and the junction depth of source drain is shoaled, so help the miniaturization of field-effect transistor.
When the metal silicide layer that adopts the self-aligned silicide treatment process to form is cobalt silicide, because CoSi 2The resistance of phase is lower than the CoSi phase, so, at the conducting film that constitutes grid and constitute on the surface of semiconductor regions of source drain and must form by CoSi 2The metal silicide layer of forming.And the metal silicide layer that adopts the self-aligned silicide treatment process to form is when being nickel silicide, because the resistance of NiSi phase is lower than NiSi 2So phase is at the conducting film that constitutes grid and constitute on the surface of semiconductor regions of source drain and must form the metal silicide layer of being made up of NiSi.
When forming cobalt silicide, Si (silicon) is diffusion kind, and Si moves in the Co film, forms cobalt silicide thus, and when forming nickel silicide, and Ni (nickel) is diffusion kind, and Ni (nickel) forms nickel silicide thus to the silicon area side shifting.
The inventor finds that after deliberation Ni during heat treatment (nickel) excess diffusion forms unwanted NiSi 2Part might make the resistance inequality of the metal silicide layer of each field-effect transistor.In order further to improve the performance of field-effect transistor, wish the resistance inequality of the metal silicide layer of each field-effect transistor of reduction, and prevent the characteristic variations of field-effect transistor.
The inventor also finds after deliberation, during heat treatment NiSi might take place 2Misgrowth from NiSi course groove.If NiSi 2From the misgrowth of NiSi course groove, then cause the leakage current between the source drain of field-effect transistor to increase, perhaps cause the diffusion resistance in source drain zone to increase, so, in order further to improve the performance of field-effect transistor, wish to prevent above-mentioned NiSi 2Misgrowth from NiSi course groove.
Usually, on the interarea of Semiconductor substrate, form p channel type field effect transistors and n channel type field effect transistors as the active element that constitutes integrated circuit.Form nickel silicide layer respectively on the surface of the source drain of the source drain of p channel type field effect transistors and n channel type field effect transistors, realize the low resistanceization of the source drain of field-effect transistor, the inventor etc. study this.
Found that forming nickel silicide layer on the source drain of p channel type field effect transistors causes junction leakage to increase and inequality easily.In order to reduce above-mentioned junction leakage, the thickness that reduces to be deposited on the Ni film on the Si substrate is effectively, if but reduce the thickness of Ni film, then adopt the thickness attenuation of the nickel silicide layer that the self-aligned silicide technology forms, cause obtaining the low resistance effect.Surface gate electrode at field-effect transistor also forms nickel silicide layer, thereby the resistance of gate electrode is also reduced.The gate electrode of field-effect transistor usually as wiring, in the time of can't forming wiring by low-resistance gate electrode, causes taking place problems such as circuit working delay in integrated circuit.
The object of the present invention is to provide the technology that can improve performance of semiconductor device.
Other purposes of the present invention are to provide the technology that can improve semiconductor device reliability, and described semiconductor device has the field-effect transistor that has formed metal silicide layer on the surface of source drain.
Record and accompanying drawing above-mentioned and other purposes and new feature of the present invention as can be known by present specification.
Representative solution among following brief description the present invention.
The representative embodiment of the manufacture method of semiconductor device is after forming semiconductor regions on the Semiconductor substrate, clean the surface of the semiconductor regions of (dry cleaning) clean semiconductor substrate interarea by dry type, on Semiconductor substrate, form metal film, carry out the 1st heat treatment, make the reaction of above-mentioned metal film and above-mentioned semiconductor regions, the metal silicide layer that formation is made up of single silicide MSi of the metallic element M that constitutes above-mentioned metal film, remove unreacted above-mentioned metal film, carry out the 2nd heat treatment then.And the above-mentioned the 2nd heat treated heat treatment temperature is higher than the above-mentioned the 1st heat treated heat treatment temperature and is lower than the disilicide MSi of above-mentioned metallic element M 2Lattice size and lattice the 1st temperature of the same size of above-mentioned Semiconductor substrate.
Other representative embodiment of the manufacture method of semiconductor device be at the gate insulating film that has formed the n channel type field effect transistors, gate electrode and source drain with gate insulating film, gate electrode and the source drain of semiconductor regions and p channel type field effect transistors with depositing metallic films and the 1st barrier film successively on the Semiconductor substrate of semiconductor regions.Then, the temperature range of the reactivity of the metal film the when reactivity of the metal film when the reaction of the semiconductor regions that makes the p channel type field effect transistors and metal film is lower than the semiconductor regions that makes the n channel type field effect transistors and metal film reaction is carried out the 1st heat treatment, on the surface of the gate electrode of n channel type field effect transistors or semiconductor regions, and the surface of the gate electrode of p channel type field effect transistors or semiconductor regions on form metal silicide layer.Then, remove the metallic element of the 1st barrier film and unreacted formation metal film, on the surface of the gate electrode of n channel type field effect transistors or semiconductor regions, and the surface of the gate electrode of p channel type field effect transistors or semiconductor regions on behind the kish silicide layer, heat-treat temperature and be higher than the 1st heat treated the 2nd heat treatment.
The effect that following brief description is obtained by the representative solution among the present invention.
Can improve the performance of semiconductor device according to representational embodiment.
Can also improve the reliability of semiconductor device with the field-effect transistor that on the surface of source drain, has formed metal silicide layer.
Description of drawings
[Fig. 1] is as the major part profile in the semiconductor device manufacturing process of one of embodiment of the present invention.
Major part profile in the semiconductor device manufacturing process after [Fig. 2] Fig. 1.
Major part profile in the semiconductor device manufacturing process after [Fig. 3] Fig. 2.
Major part profile in the semiconductor device manufacturing process after [Fig. 4] Fig. 3.
Major part profile in the semiconductor device manufacturing process after [Fig. 5] Fig. 4.
Major part profile in the semiconductor device manufacturing process after [Fig. 6] Fig. 5.
Major part profile in the semiconductor device manufacturing process after [Fig. 7] Fig. 6.
Major part profile in the semiconductor device manufacturing process after [Fig. 8] Fig. 7.
[Fig. 9] expression is as the manufacturing process flow diagram of the part of the semiconductor device manufacturing process of one of embodiment of the present invention.
The plane sketch of the film formation device of the silicide material of one of [Figure 10] embodiment of the present invention.
The film formation process figure of the silicide material of one of [Figure 11] embodiment of the present invention.
The diagrammatic sectional view of the dry type cleaning process room that the film formation device of the silicide material of one of [Figure 12] embodiment of the present invention has.
[Figure 13] (a) and (b) and (c) be respectively the diagrammatic sectional view of chamber that is used for illustrating the semiconductor wafer processing operation of the dry type cleaning process room that the film formation device in the silicide material of embodiment of the present invention 1 has.
Major part profile in the semiconductor device manufacturing process after [Figure 14] Fig. 8.
Major part profile in the semiconductor device manufacturing process after [Figure 15] Figure 14.
Major part profile in the semiconductor device manufacturing process after [Figure 16] Figure 15.
Major part profile in the semiconductor device manufacturing process after [Figure 17] Figure 16.
The process chart of the formation operation of the NiSi layer in the semiconductor device of [Figure 18] expression comparative example.
Major part profile in the semiconductor device manufacturing process of [Figure 19] comparative example.
Major part profile in the semiconductor device manufacturing process of the comparative example after [Figure 20] Figure 19.
Major part profile in the semiconductor device manufacturing process of the comparative example after [Figure 21] Figure 20.
Major part profile in the semiconductor device manufacturing process of [Figure 22] comparative example.
The dependent curve chart of heat treatment temperature of the sheet resistance of [Figure 23] expression nickel silicide layer.
[Figure 24] expression single crystalline Si and NiSi 2The temperature dependent curve chart of lattice size.
[Figure 25] expression single crystalline Si and Ni 1-xPt xSi 2The temperature dependent curve chart of lattice size.
When [Figure 26] expression is carried out the 2nd heat treatment and is formed nickel silicide layer and the curve chart of the distribution of leakage current when not carrying out the 2nd heat treatment formation nickel silicide layer.
The curve chart of the distribution of the sheet resistance of [Figure 27] expression nickel silicide layer.
The crystalline texture of [Figure 28] expression silicon is the key diagram of diamond lattic structure.
[Figure 29] represents NiSi 2Crystalline texture be the key diagram of fluorite structure.
[Figure 30] (a) represents NiSi 2Fluorite structure in the key diagram of crystalline texture of Ni, (b) expression NiSi 2Fluorite structure in the key diagram of crystalline texture of Si.
The manufacturing process flow diagram of the part of the semiconductor device manufacturing process of [Figure 31] expression embodiment of the present invention 2.
Major part profile in the semiconductor device manufacturing process of [Figure 32] embodiment of the present invention 2.
Major part profile in the semiconductor device manufacturing process after [Figure 33] Figure 32.
Major part profile in the semiconductor device manufacturing process after [Figure 34] Figure 33.
Major part profile in the semiconductor device manufacturing process after [Figure 35] Figure 34.
The manufacturing process flow diagram of the part of the semiconductor device manufacturing process of [Figure 36] expression embodiment of the present invention 3.
Major part profile in the semiconductor device manufacturing process of [Figure 37] embodiment of the present invention 3.
Major part profile in the semiconductor device manufacturing process after [Figure 38] Figure 37.
The dependent curve chart of heat treatment temperature of the sheet resistance of the nickel silicide layer of [Figure 39] expression embodiment of the present invention 3.
The n of [Figure 40] expression embodiment of the present invention 3 +The reactivity of type silicon area and Ni film and p +The dependent curve chart of the heat treatment temperature of the reactivity of type silicon area and Ni film.
The n of [Figure 41] expression embodiment of the present invention 3 +The reactivity of type silicon area and Ni film and p +The dependent curve chart of the heat treatment temperature of the difference of the reactivity of type silicon area and Ni film.
The major part profile that (forms the stage of metal film and barrier film) in the semiconductor device manufacturing process of [Figure 42] embodiment of the present invention 3.
The major part profile that (carried out for the 1st heat treated stage) in the semiconductor device manufacturing process of [Figure 43] embodiment of the present invention 3.
The major part profile that (has carried out the stage of removing operation of barrier film and unreacted metal film) in the semiconductor device manufacturing process of [Figure 44] embodiment of the present invention 3.
The major part profile that (carried out for the 2nd heat treated stage) in the semiconductor device manufacturing process of [Figure 45] embodiment of the present invention 3.
The curve chart of the distribution of the leakage current of the nickel silicide layer of [Figure 46] expression embodiment of the present invention 3.
Major part profile in the semiconductor device manufacturing process after [Figure 47] Figure 37.
The manufacturing process flow diagram of the part of the semiconductor device manufacturing process of [Figure 48] expression embodiment of the present invention 4.
Major part profile in the semiconductor device manufacturing process of [Figure 49] expression embodiment of the present invention 4.
Major part profile in the semiconductor device manufacturing process after [Figure 50] Figure 49.
Major part profile in the semiconductor device manufacturing process after [Figure 51] Figure 50.
Major part profile in the semiconductor device manufacturing process after [Figure 52] Figure 51.
The manufacturing process flow diagram of the part of the semiconductor device manufacturing process of [Figure 53] expression embodiment of the present invention 5.
Major part profile in the semiconductor device manufacturing process of [Figure 54] embodiment of the present invention 5.
Major part profile in the semiconductor device manufacturing process after [Figure 55] Figure 54.
Major part profile in the semiconductor device manufacturing process after [Figure 56] Figure 55.
The manufacturing process flow diagram of the part of the semiconductor device manufacturing process of [Figure 57] expression embodiment of the present invention 6.
Major part profile in the semiconductor device manufacturing process of [Figure 58] expression embodiment of the present invention 6.
Major part profile in the semiconductor device manufacturing process after [Figure 59] Figure 58.
Major part profile in the semiconductor device manufacturing process after [Figure 60] Figure 59.
Symbol description
1 Semiconductor substrate
2 dielectric films
3 dielectric films
4 element separated regions
The 4a ditch
The 4b dielectric film
The 4c dielectric film
5 p type traps
6 n type traps
7 gate insulating films
8 silicon fimls
8a, 8b gate electrode
9a n -The N-type semiconductor N zone
9b n +The N-type semiconductor N zone
10a p -The N-type semiconductor N zone
10b p +The N-type semiconductor N zone
11 sidewalls
12 metal films
The 12a non-reacted parts
13,13a barrier film
20 film formation devices
21a the 1st carrying room
21b the 2nd carrying room
22 gate valves
23 load lock
24 load lock
25, Room 26,27
The 27a wafer station
The 27b wafer lift pins
27c, 27CH spray head
27d remote plasma generating means
27e seals (sealing)
27f shade ring (shadow ring)
The 27g exhaust chamber
28, Room 29,30,31
32a, 32b conveyance mechanical hand
Wafer input and output chambers 33
34 hoops
35 inlets
36 conveyance mechanical hands
41,41a, 41b metal silicide layer
42,43 dielectric films
44 contact holes
45 embolisms
45a insulated conductor film
45b leading body film
51 stop dielectric film
52 dielectric films
53 wiring trenches
54 insulated conductor films
55 wirings
112 Ni films
113 titanium nitride films
141a Ni 2The Si layer
141b NiSi layer
141c NiSi 2The misgrowth zone
Qn、Qp?MISFET
The SW semiconductor wafer
Embodiment
In following embodiment, for convenience of explanation, being divided into a plurality of parts or embodiment in case of necessity describes, under the situation unless otherwise indicated, each part mentioned above or embodiment are not irrelevant, the example of the part or all of distortion that embodiment is another embodiment or to its carry out in detail, supplementary notes etc.In addition, in following embodiment, when relating to (the comprising number, numerical value, amount, scope etc.) such as numerical value of key element, unless otherwise indicated and when clearly being defined as special value on the principle etc., be not limited to special value, can for more than the special value or below.In following embodiment, unless otherwise indicated and on the principle clearly be must the time etc., its inscape (also comprising key element step etc.) may not be essential inscape.Equally, clear and definite when not being such etc. unless otherwise indicated and on the principle when relating to the shape, position relation etc. of inscape etc. in following embodiment, comprise in fact approximate or similar shape etc. with this shape etc.Above-mentioned numerical value and scope also are same.
Below describe embodiment of the present invention in detail based on accompanying drawing.Need to prove that at the whole accompanying drawings that are used for illustrating embodiment, the parts with same function are labeled as prosign, omit repeat specification.In addition, in following embodiment, unless necessary especially, do not repeat the explanation of same or same section in principle.
In the accompanying drawing that embodiment is used,, in sectional view, also omit hachure sometimes for the ease of observing accompanying drawing.In addition, for the ease of observing accompanying drawing, also mark hachure in plane graph sometimes.
In addition, the dry type cleaning technique is disclosed Japanese patent application 2006-3704 number (on January 11st, 2006 filed an application), Japanese patent application 2006-12355 number (on January 20th, 2006 filed an application), two rapids etc. Japanese patent applications 2006-107780 number (on April 10th, 2006 filed an application), two rapids etc. Japanese patent applications 2007-81147 number (on March 27th, 2007 filed an application) of one rapids grade.In addition, 2007-81147 such as the Japanese patent application of two rapids grades (on March 27th, 2007 filed an application) discloses the effect that is formed at the barrier film on the self-aligned silicide material membrane that is used as the film that Stress Control film (film of the stress of control Semiconductor substrate active region) and anti-block see through in the self-aligned silicide technology etc.
(embodiment 1)
The semiconductor device manufacturing process of the present embodiment is described with reference to the accompanying drawings.Fig. 1～Fig. 8 be as one embodiment of the present invention semiconductor device, for example have a major part profile in the manufacturing process of semiconductor device of CMISFET (complementary type metal-insulator-semiconductor field effect transistor (Complementary MetalInsulator Semiconductor Field Effect Transistor)).
At first, as shown in Figure 1, prepare to have the Semiconductor substrate (semiconductor wafer) 1 that constitutes by monocrystalline silicon etc. of the p type of the resistivity about 1～10 Ω cm for example.Then, this Semiconductor substrate 1 of thermal oxidation, after for example forming the dielectric film about thickness 11nm 2 in its surface, utilize CVD (chemical vapour deposition (CVD) (Chemical Vapor Deposition)) method etc. to deposit for example dielectric film about thickness 90nm 3 on the upper strata of this dielectric film.Dielectric film 2 is made of silica etc., and dielectric film 3 is made of silicon nitride film etc.Then, as shown in Figure 2, with photoresist pattern (not shown) is etching mask dry ecthing dielectric film 3, dielectric film 2 and Semiconductor substrate 1 successively, forms the degree of depth for example thus and be ditch about 300nm (element separate use ditch) 4a on element separate to form the Semiconductor substrate 1 of presumptive area.Ditch 4a is the ditch that is used for resolution element,, is used to form the ditch of element separated region 4 described later that is.
Next, as shown in Figure 3, remove dielectric film 3 by the wet etching that has used hot phosphoric acid etc. after, on the interarea of Semiconductor substrate 1, comprise ditch 4a inside (sidewall and bottom), form for example dielectric film 4b about thickness 10nm.Then, utilize formation (deposition) dielectric film 4c such as CVD method (being on the dielectric film 4b) on the interarea of Semiconductor substrate 1, with landfill ditch 4a inside.
Dielectric film 4b is made of silicon oxide film or oxygen silicon nitride membrane.When dielectric film 4b is oxygen silicon nitride membrane, has following effect: can prevent to form the caused volumetric expansion of sidewall generation oxidation that the later heat treatment of operation makes ditch 4a, and can reduce the compression that acts on the Semiconductor substrate 1 by dielectric film 4b.
Dielectric film 4c is by HDP-CVD (High Density Plasma CVD: high-density plasma CVD) silicon oxide film of method film forming or O 3-TEOS oxide-film etc.Need to prove O 3-TEOS oxide-film is to use O 3(ozone) and TEOS (Tetraethoxysilane: tetraethoxysilane is also referred to as tetraethyl orthosilicate (Tetra Ethyl OrthoSilicate)) are unstripped gas (source gas), by the silicon oxide film of hot CVD method formation.Dielectric film 4c is when utilizing the silicon oxide film of HDP-CVD method film forming, and dielectric film 4b has the effect that prevents to damage Semiconductor substrate 1 when deposition dielectric film 4c.
Next, as shown in Figure 4, (Chemical Mechanical Polishing: cmp) method is ground dielectric film 4c, removes the dielectric film 4c of ditch 4a outside to utilize CMP, residual dielectric film 4b, 4c in the inside of ditch 4a form element separated region (element separation) 4 thus.
Then, Semiconductor substrate 1 is heat-treated under for example about 1150 ℃, sintering is imbedded the dielectric film 4c of ditch 4a thus.Under the state before the sintering, utilize the silicon oxide film of HDP-CVD method film forming to compare O 3The densification of-TEOS oxide-film.Therefore, dielectric film 4c is O 3During-TEOS oxide-film, the contraction with dielectric film 4c that sintering causes can reduce the effect that acts on the compression on the Semiconductor substrate 1.And dielectric film 4c is when utilizing the silicon oxide film of HDP-CVD method film forming, with dielectric film 4c be O 3-TEOS compares during oxide-film, and the contraction of the dielectric film 4c during sintering is little, so the compression that element separated region 4 acts on Semiconductor substrate 1 becomes big.
Be formed as described above by imbedding the dielectric film 4b in the ditch 4a, the element separated region 4 that 4c constitutes.Element separated region 4 does not form by LOCOS (local oxidation of silicon (Local Oxidization of Silicon)) method in the present embodiment, but preferably utilizes STI (shallow trench isolation is from (Shallow Trench Isolation)) method to form.That is, the element separated region 4 of the present embodiment preferably constitutes with the insulator in the ditch 4a (referring to dielectric film 4b, 4c herein) by imbedding the element separation that is formed at Semiconductor substrate 1.N channel-type MISFETQn described later (promptly constitutes gate insulating film 7, gate electrode 8a and the source drain n of n channel-type MISFETQn -N-type semiconductor N zone 9a and n +N-type semiconductor N zone 9b) is formed at active region by element separated region 4 regulations (encirclement).P channel-type MISFETQp described later (promptly constitutes gate insulating film 7, gate electrode 8b and the source drain p of p channel-type MISFETQp -N-type semiconductor N zone 10a and p +N-type semiconductor N zone 10b) also is formed at active region by element separated region 4 regulations (encirclement).
Next, as shown in Figure 5, the degree of depth of extremely stipulating from the interarea of Semiconductor substrate 1 forms p type trap 5 and n type trap 6.P type trap 5 can be by injecting as ion and stop mask covering photoresist film (not shown) that p channel-type MISFET forms presumptive area, forms ion on the Semiconductor substrate 1 of presumptive area at n channel-type MISFET and inject the method etc. of boron p such as (B) type impurity for example and form.N type trap 6 can be by injecting as ion and stop mask covering other photoresist film (not shown)s that n channel-type MISFET forms presumptive area, forms ion on the Semiconductor substrate 1 of presumptive area at p channel-type MISFET and inject the method etc. of phosphorus (P) for example or arsenic n such as (As) type impurity and form.
Next, behind the surface of cleaning (washing) Semiconductor substrate 1 such as the wet etching by for example having used hydrofluoric acid (HF) aqueous solution, go up formation gate insulating film 7 on the surface of Semiconductor substrate 1 (being the surface of p type trap 5 and n type trap 6).Gate insulating film 7 for example is made of thin silicon oxide film etc., for example can be by formation such as thermal oxidation methods.
Next, form the silicon fiml 8 of polysilicon film and so on as gate electrode formation electrically conductive film at (that is, on the gate insulating film 7 of p type trap 5 and n type trap 6) on the Semiconductor substrate 1.N channel-type MISFET in the silicon fiml 8 forms presumptive area (becoming the zone of gate electrode 8a described later) can be by using the photoresist film (not shown) as mask, and ion injects formation low-resistance n N-type semiconductor N films (doped poly silicon film) such as the method for phosphorus (P) or arsenic n such as (As) type impurity.P channel-type MISFET in the silicon fiml 8 forms presumptive area (becoming the zone of gate electrode 8b described later) by using other photoresist film (not shown)s as mask, the methods of boron ion implantation p such as (B) type impurity etc. form low-resistance p N-type semiconductor N film (doped poly silicon film).Silicon fiml 8 can be an amorphous silicon film when film forming also, and the heat treatment of (ion injects the back) becomes polysilicon film after film forming.
Next, as shown in Figure 6, make silicon fiml 8 form pattern, form gate electrode 8a, 8b thus by using photoetching process and dry ecthing method.
The gate electrode 8a that becomes the gate electrode of n channel-type MISFET is made of the polysilicon that has imported n type impurity (n N-type semiconductor N film, doped poly silicon film), and gate insulating film 7 is formed on the p type trap 5 at interval.That is, gate electrode 8a is formed on the gate insulating film 7 of p type trap 5.The gate electrode 8b that becomes the gate electrode of p channel-type MISFET is made of the polysilicon that has imported p type impurity (p N-type semiconductor N film, doped poly silicon film), and gate insulating film 7 is formed on the n type trap 6 at interval.That is, gate electrode 8b is formed on the gate insulating film 7 of n type trap 6.The grid length of gate electrode 8a, 8b can change as required, for example is about 50nm.
Next, as shown in Figure 7, inject phosphorus (P) or arsenic (As) the n type impurity of etc.ing, formation (a pair of) n by two side areas ion at the gate electrode 8a of p type trap 5 -N-type semiconductor N zone 9a is by two side areas boron ion implantation (B) the p type impurity of etc.ing at the gate electrode 8b of n type trap 6, formation (a pair of) p -N-type semiconductor N zone 10a.n -N-type semiconductor N zone 9a and p -The degree of depth (junction depth) of N-type semiconductor N zone 10a for example can be for about 30nm.
Next, on the sidewall of gate electrode 8a, 8b, form the sidewall spacers (spacer) that constitutes by the laminate film of for example silica or silicon nitride or above-mentioned dielectric film etc. or sidewall (side wall) (side wall insulating film) 11 as dielectric film.For example can be by the laminate film of cvd silicon oxide film on Semiconductor substrate 1 or silicon nitride film or above-mentioned film, utilize the laminate film of this silicon oxide film of anisotropic etching such as RIE (reactive ion etching (Reactive Ion Etching)) method or silicon nitride film or above-mentioned film, form sidewall 11.
After forming sidewall 11, for example pass through the two side areas at the gate electrode 8a and the sidewall 11 of p type trap 5, ion injects phosphorus (P) or arsenic n type impurity such as (As), forms (a pair of) n +N-type semiconductor N zone 9b (source electrode, drain electrode).For example, with 5 * 10 15/ cm 2About inject phosphorus (P), with 4 * 10 15/ cm 2About inject arsenic (As) and form.In addition, for example pass through the two side areas at the gate electrode 8b and the sidewall 11 of n type trap 6, boron ion implantation p type impurity such as (B) forms (a pair of) p +N-type semiconductor N zone 10b (source electrode, drain electrode).For example with 4 * 10 15/ cm 2About inject boron (B) and form.Can form n earlier +N-type semiconductor N zone 9b perhaps also can form p earlier +N-type semiconductor N zone 10b.After ion injects, also can utilize the annealing in process of handling the impurity that is used to activate importing at for example spike annealing about 1050 ℃ (Spike Anneal).n +N-type semiconductor N zone 9b and p +The degree of depth (junction depth) of N-type semiconductor N zone 10b for example can be for about 80nm.
n +The impurity concentration of N-type semiconductor N zone 9b is higher than n -N-type semiconductor N zone 9a, p +The impurity concentration of N-type semiconductor N zone 10b is higher than p -N-type semiconductor N zone 10a.Make n N-type semiconductor N zone (impurity diffusion layer) that source electrode or drain electrode as n channel-type MISFET play a role by n thus +N-type semiconductor N zone (impurity diffusion layer) 9b and n -N-type semiconductor N zone 9a forms, and the p N-type semiconductor N zone (impurity diffusion layer) that plays a role as source electrode or the drain electrode of p channel-type MISFET is by p +N-type semiconductor N zone (impurity diffusion layer) 10b and p -N-type semiconductor N zone 10a forms.So the source drain zone of n channel-type MISFET and p channel-type MISFET has LDD (lightly doped drain (Lightly doped Drain)) structure.n -N-type semiconductor N zone 9a forms n with respect to gate electrode 8a autoregistration +N-type semiconductor N zone 9b forms with respect to 11 autoregistrations of the sidewall on the sidewall that is formed at gate electrode 8a.p -N-type semiconductor N zone 10a forms p with respect to gate electrode 8b autoregistration +N-type semiconductor N zone 10b forms with respect to 11 autoregistrations of the sidewall on the sidewall that is formed at gate electrode 8b.
Thus, on p type trap 5, form n channel-type MISFET (metal-insulator-semiconductor field effect transistor) Qn as field-effect transistor.On n type trap 6, form p channel-type MISFET (metal-insulator-semiconductor field effect transistor) Qp as field-effect transistor.Obtain the structure of Fig. 7 thus.N channel-type MISFETQn can be considered as the n channel type field effect transistors, and p channel-type MISFETQp can be considered as the p channel type field effect transistors.n +N-type semiconductor N zone 9b can be considered as source electrode or the drain electrode semiconductor regions, p of n channel-type MISFETQn +N-type semiconductor N zone 10b can be considered as source electrode or the drain electrode semiconductor regions of p channel-type MISFETQp.
Next, utilize self-aligned silicide (salicide:Self Aligned Silicide) technology in the gate electrode 8a of n channel-type MISFETQn and source drain zone (herein corresponding to n +N-type semiconductor N zone 9b) surface and the gate electrode 8b of p channel-type MISFETQp and source drain zone are (herein corresponding to p +N-type semiconductor N zone 10b) forms low-resistance metal silicide layer (corresponding to metal silicide layer 41 described later) on the surface.The formation operation of this metal silicide layer below is described.
Fig. 8 is the major part profile in Fig. 7 semiconductor device manufacturing process afterwards.Fig. 9 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment, be illustrated in the structure that obtains Fig. 7 after, utilize self-aligned silicide (salicide:Self AlignedSilicide) to handle at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Form the manufacturing process flow diagram of the operation of metal silicide layer (metal semiconductor conversion zone) on the surface of N-type semiconductor N zone 10b.Figure 10 is that (metal silicide layer 41 forms and uses material membrane silicide material, herein corresponding to metal film 12 and barrier film 13) the plane sketch of film formation device, Figure 11 is the film formation process figure (process chart) of silicide material, Figure 12 is the diagrammatic sectional view of the dry type cleaning process room that is equipped with in the film formation device of silicide material, and Figure 13 is the process chamber diagrammatic sectional view that is used for illustrating the semiconductor wafer processing operation in the dry type cleaning process room that the silicide material film formation device is equipped with.Figure 14～Figure 17 is the major part profile in Fig. 8 semiconductor device manufacturing process afterwards.Need to prove that Fig. 9 is the manufacturing process flow diagram corresponding to the operation of Fig. 8 and Figure 14, Figure 11 is the manufacturing process flow diagram corresponding to the operation of Fig. 8.
As mentioned above, obtain the structure of Fig. 7 after, as shown in Figure 8, make gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +After expose on the surface of N-type semiconductor N zone 10b, on the interarea (whole surface) of Semiconductor substrate 1, comprise gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +On the 10b of N-type semiconductor N zone, for example utilizing, sputtering method forms (deposition) metal film 12 (the step S1 of Fig. 9).That is, in step S1, on Semiconductor substrate 1, comprise n +N-type semiconductor N zone 9b and p +On the 10b of N-type semiconductor N zone, form metal film 12, with covering grid electrode 8a, 8b.
Then, on metal film 12, form (deposition) barrier film (the 1st barrier film, Stress Control film, oxidation-resistant film, block film (cap film)) 13 (step S2 of Fig. 9).
The preceding use HF gas of step S1 (metal film 12 deposition procedures), NF 3Gas, NH 3Gas or H 2At least a dry type clean (corresponding to operation P2 described later) of carrying out in the gas is removed gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The natural oxide film on the surface of N-type semiconductor N zone 10b then, does not place Semiconductor substrate 1 atmosphere (atmosphere that contains aerobic), but carries out step S1 and step S2, and is comparatively desirable.
Metal film 12 for example is made of nickel (Ni) film, and its thickness (deposition thickness) for example can be for about 9nm.Except that Ni (nickel) film, for example also can use Ni-Pt alloy film (alloy film of Ni and Pt), Ni-Pd alloy film (alloy film of Ni and Pd), Ni-Y alloy film (alloy film of Ni and Y), Ni-Yb alloy film (alloy film of Ni and Yb), Ni-Er alloy film (alloy film of Ni and Er) or Ni-lanthanide series alloy film (alloy film of Ni and lanthanide series) and so on nickel alloy film etc. as metal film 12.Barrier film 13 for example is made of titanium nitride (TiN) film or titanium (Ti) film, and its thickness (deposition thickness) for example can be for about 15nm.Barrier film 13 plays a role as the film that Stress Control film (film of the stress of control Semiconductor substrate active region) and anti-block see through, be set at be used on the metal film 12 control action on Semiconductor substrate 1 stress or prevent metal film 12 oxidations etc.One of the method that the is preferably formed example of metal film 12 and barrier film 13 below is described.
The film forming of metal film 12 and barrier film 13 is used the film formation device 20 of silicide material shown in Figure 10.
As shown in figure 10, film formation device 20 disposes the 1st carrying room 21a and two carrying rooms of the 2nd carrying room 21b, around the 1st carrying room 21a, assemble 23,24 and 3 chambers 25,26,27 of load lock (load-lock chamber) by gate valve (gate valve) 22 as shutter means, around the 2nd carrying room 21b,, be the multichamber type device by 2 chambers 28,29 of gate valve 22 assemblings as shutter means.In addition, chamber 30,31 is used in 2 conveyances of configuration between the 1st carrying room 21a and the 2nd carrying room 21b.The 1st carrying room 21a is by maintenance specified vacuum degree such as exhaust gears, and portion is provided for the conveyance mechanical hand 32a of the multi-joint arm structure of conveyance semiconductor wafer SW in the central.Equally, the 2nd carrying room 21b is by maintenance specified vacuum degree such as exhaust gears, and portion is provided for the conveyance mechanical hand 32b of the multi-joint arm structure of conveyance semiconductor wafer SW in the central.
The 1st carrying room 21a goes up the chamber the 25, the 26th of configuration, carries out the heat treated of the heat treated of relatively-high temperature and uses the chamber, chamber 27 is that dry type clean (disposal) is used the chamber, the chamber 28 that the 2nd carrying room 21b goes up configuration is that the film forming of utilizing sputtering method to form metal film 12 (for example nickel film) is used the chamber, and chamber 29 is to use the chamber with the film forming of sputtering method formation barrier film 13 (for example titanium nitride film).When utilizing plasma CVD method to form barrier film 13, chamber 29 becomes the film forming of utilizing plasma CVD method to form barrier film 13 (for example titanium film) and uses the chamber.
Be configured in the chamber the 30, the 31st between the 1st carrying room 21a and the 2nd carrying room 21b, the chamber is used in the handing-over that semiconductor wafer SW joins between the 1st carrying room 21a and the 2nd carrying room 21b, in addition, also is that the chamber is used in the cooling that is used to cool off semiconductor wafer SW.Need to prove that in film formation device 20, the chamber that only is configured on the 1st carrying room 21a is 3, the chamber that only is configured on the 2nd carrying room 21b is 2, but is not limited thereto, and also can replenish the chamber of same use or the chamber of other purposes.
At first, utilize the conveyances be arranged in the wafer input and output chamber 33 with mechanical hands 36 1 semiconductor wafer SW to be taken out (the operation P1 of Figure 11) from any one hoop (hoop) 34, conveyance is to any of load lock 23 or 24.Hoop 34 is airtight accommodating containers of conveyance in batches of semiconductor wafer SW, takes in semiconductor wafer SW with endorsement positions such as 25,12,6 usually.The container outer wall of hoop 34 is an airtight construction except that fine breather filter portion, and dust almost completely is excluded.So, even conveyance in 1000 grades atmosphere, the inner cleannes that also can keep 1 grade.With the docking of film formation device 20 (docking) is that door leaf with hoop 34 is installed on the inlet 35, imports 33 inside, wafer input and output chamber, thereby is keeping carrying out under the clean state.Then, after vacuumizing in the load lock 23, utilize conveyance with mechanical hand 32a with semiconductor wafer SW from the 1st carrying room 21a vacuum conveyance to dry type cleaning process room 27 (the operation P2 of Figure 11).Figure 12 represents the diagrammatic sectional view of chamber 27.As shown in figure 12, chamber 27 mainly is made of wafer station (wafer stage) 27a, wafer lift pins (wafer liftpin) 27b, spray head (shower head) 27c and remote plasma generating means 27d.Wafer station 27a and wafer lift pins 27b have independently elevating mechanism, can control the distance of spray head 27c and semiconductor wafer SW and the distance of semiconductor wafer SW and wafer station 27a arbitrarily.The spray head 27c that is arranged on the top of wafer station 27a keeps uniform temperature usually, and this temperature for example is 180 ℃.
When being input to semiconductor wafer SW in the chamber 27, shown in Figure 13 (a), wafer station 27a is descended, make wafer lift pins 27b rise bearing semiconductor wafer SW on wafer lift pins 27b.The distance of spray head 27c and semiconductor wafer SW for example is set at 16.5 ± 12.7mm, and the distance of semiconductor wafer SW and wafer station 27a for example is set at 25.4 ± 17.8mm.
Next, when the interarea of dry type clean semiconductor wafer SW, shown in Figure 13 (b), wafer station 27a is risen, make wafer lift pins 27b descend bearing semiconductor wafer SW on wafer station 27a.The distance of spray head 27c and semiconductor wafer SW for example is set at 17.8 ± 5.1mm.
During the dry type clean, in remote plasma generating means 27d, excite and added for example NF of reducing gas 3Gas and NH 3The Ar gas of gas generates plasma, and this plasma is imported in the chamber 27.The plasma that is imported in the chamber 27 supplies to by spray head 27c on the interarea of semiconductor wafer SW, and (polysilicon and the formation that constitute gate electrode 8a, 8b have formed n with being formed at silicon by plasma +N-type semiconductor N zone 9b and p +Reduction reaction shown in for example formula (1) that takes place between the natural oxide film on the surface monocrystalline silicon of the Semiconductor substrate 1 of N-type semiconductor N zone 10b) is removed natural oxide film.Process conditions during the dry type clean for example is 180 ℃ of spray head temperature, NF 3Gas flow 14sccm, NH 3Gas flow 70sccm, pressure 400Pa, plasma power 30W.
SiO 2+ 2NF 3+ 2NH 3→ (NH 4) 2SiF 6(s)+2N 2+ 2H 2O formula (1)
At this moment, the product ((NH that generates by reduction reaction 4) 2SiF 6) remain on the interarea of semiconductor wafer SW.Semiconductor wafer SW only is carried on the wafer station 27a, and above-mentioned product also remains in the part at the side and the back side of semiconductor wafer SW.The product of a part that remains in the side of semiconductor wafer SW and the back side causes polluting or rising dirt in that semiconductor wafer SW conveyance is peeled off during to other chambers etc.So, after the dry type clean (disposal),, remove the product on the interarea that remains in semiconductor wafer SW by in chamber 27, semiconductor wafer SW being implemented heat treatment, simultaneously, remove residual product on the part at the side of semiconductor wafer SW and the back side.
Next, when heat treatment semiconductor wafer SW, shown in Figure 13 (c), wafer station 27a is descended, wafer lift pins 27b is risen, make semiconductor wafer SW be set at 180 ℃ spray head 27c near temperature.The distance of spray head 27c and semiconductor wafer SW for example is set at 3.8 ± 2.6mm, and the distance of semiconductor wafer SW and wafer station 27a for example is set at more than the 5.9mm.
During heat treatment, utilize heating-up temperature (180 ℃) the heating semiconductor wafer SW of spray head 27c.Make the temperature of semiconductor wafer SW become 100～150 ℃, during above-mentioned dry type clean (disposal), be formed at the product ((NH on the interarea of semiconductor wafer SW 4) 2SiF 6) for example the reaction shown in the through type (2) distillation remove.In addition, by this heat treatment, the side and the back side of semiconductor wafer SW also are heated, and the product that remains in the part at the side and the back side also is removed.
(NH 4) 2SiF 6(s) → (NH 4) 2SiF 6(g) formula (2)
But, during above-mentioned dry type clean, depart from (NH a little even be formed at the composition of the product on the semiconductor wafer SW 4) 2SiF 6, in the heat treatment of 100～150 ℃ of temperature, also be difficult to the reaction of generating polynomial (2), cause removing product fully residual atomic few product on the interarea of semiconductor wafer SW.As mentioned above, if the product of residual pettiness on the interarea of semiconductor wafer SW then makes the resistance inequality of the metal silicide layer (for example nickel silicide layer) on the interarea that was formed at semiconductor wafer SW afterwards.So, in the operation afterwards, semiconductor wafer SW is implemented temperature be higher than 150 ℃ heat treatment, remove the pettiness product on the interarea that remains in semiconductor wafer SW.
Next, utilize conveyance semiconductor wafer SW to be used chamber 25 (or chamber 26) from dry type cleaning process room 27 by the 1st carrying room 21a vacuum conveyance to heat treated, be carried on the platform (stage) that is disposed in the chamber 25 (or chamber 26) and go up (the operation P3 of Figure 11) with mechanical hand 32a.Bearing semiconductor wafer SW on the platform of chamber 25 (or chamber 26) heats semiconductor wafer SW thus under the temperature of regulation, the product on the interarea that remains in semiconductor wafer SW not distilling under 100～150 ℃ the temperature is removed in distillation.About the temperature on the interarea of semiconductor wafer SW, 150～400 ℃ of deemed appropriate scopes (also depend on other conditions certainly, be not limited to this scope) for example.Scope as be fit to producing in batches is thought of as 165～350 ℃, and 180～220 ℃ of grades are that the scope of central value is considered to only with 200 ℃.
Next, utilize conveyance semiconductor wafer SW extremely to be cooled off handing-over with chamber 30 (or chamber 31) with chamber 25 (or chamber 26) by the 1st carrying room 21a vacuum conveyance from heat treated, be carried on the platform that is disposed in the chamber 30 (or chamber 31) (the operation P4 of Figure 11) with mechanical hand 32a.By bearing semiconductor wafer SW on the platform of chamber 30 (or chamber 31), cooling semiconductor wafer SW.
Next, utilize conveyance to use mechanical hand 32b that semiconductor wafer SW is used chamber 28 (the operation P5 of Figure 11) with chamber 30 (or chamber 31) by the 2nd carrying room 21b vacuum conveyance to metal film 12 film forming from the cooling handing-over.Make by exhaust gear and to reach specified vacuum degree, for example 1.33 * 10 in the chamber 28 -6After about Pa, SW is heated to set point of temperature with semiconductor wafer, imports Ar gas with the regulation flow in chamber 28, utilizes sputtering method depositing metallic films 12 (for example nickel film) on the interarea of semiconductor wafer SW.The deposition procedures of this metal film 12 is corresponding to above-mentioned steps S1 (the step S1 of Fig. 9).The thickness of metal film 12 is 9nm for example, and the sputtering condition during film forming for example is 40 ℃ of film-forming temperatures, Ar throughput 13sccm.
Next, utilize conveyance semiconductor wafer SW to be used chamber 29 (the operation P6 of Figure 11) with chamber 28 by the 2nd carrying room 21b vacuum conveyance to barrier film 13 film forming from metal film 12 film forming with mechanical hand 32b.By exhaust gear make reach the specified vacuum degree in the chamber 29 after, SW is heated to set point of temperature with semiconductor wafer, with the regulation flow in chamber 29, import Ar gas and N 2Gas utilizes sputtering method to deposit the barrier film 13 that is made of titanium nitride film etc. on the interarea of semiconductor wafer SW.The deposition procedures of this barrier film 13 is corresponding to above-mentioned steps S2 (the step S2 of Fig. 9).The thickness of barrier film 13 is 15nm for example, and the sputtering condition during film forming for example is 40 ℃ of film-forming temperatures, Ar throughput 28sccm, nitrogen flow 80sccm.
Next, utilize conveyance to use chamber 29 to use chamber 30 (or chamber 31) (the operation P7 of Figure 11) from barrier film 13 film forming semiconductor wafer SW by the 2nd carrying room 21b vacuum conveyance to cooling handing-over with mechanical hand 32b.
Next, utilize conveyance to use chamber 30 (or chamber 31) vacuum conveyance to any one load lock 23 or 24 from the cooling handing-over semiconductor wafer SW, utilize conveyance semiconductor wafer SW to be turned back to any one hoop 34 (the operation P8 of Figure 11) from load lock 23 or 24 by wafer input and output chamber 33 again with mechanical hand 36 with mechanical hand 32a.
Need to prove, in the above-mentioned dry type clean, among the remote plasma generating means 27d, excite and added for example NF of reducing gas 3Gas and NH 3The Ar gas of gas (as plasma exciatiaon gas, using Ar gas usually, also can be other rare gas or their mist) generates plasma, and this plasma is imported in the chamber 27, removes natural oxide film by reduction reaction.As other schemes, can not use plasma, and in chamber 27, import HF gas and NH 3Gas or NF 3Gas and NH 3Reducing gass such as gas are removed natural oxide film by reduction reaction.
In addition, be not limited to the remote plasma body device,, can use common plasma device as long as no problem on other characteristics.Remote plasma has the advantage of not damaging substrate.
When using plasma to handle, be not limited to the combination of above-mentioned gas, so long as generate nitrogen, hydrogen, the fluorine free radical (the compound free radical that comprises above-mentioned substance) separately or the gas of reaction kind, and not influencing this processing and get final product, can be the combination of other gases.That is, can suitably use nitrogen, hydrogen and fluoro free radical to generate the mixed-gas atmosphere of gas (comprising mist), plasma exciatiaon gas and other interpolation gas etc.
Reacting gass such as reducing gas are not limited to above-mentioned gas, can be the gas of reaction of formation kind, and this reaction is planted at a lower temperature and gasified with the oxide-film reaction of silicon face.
After so forming metal film 12 and barrier film 13, Semiconductor substrate 1 is implemented the 1st heat treatment (annealing in process) (the step S3 of Fig. 9).The 1st heat treatment of step S3 is preferably at inert gas (for example argon (Ar) gas or helium (He) gas) or nitrogen (N 2) in the atmosphere, under normal pressure, carry out.When metal film 12 was nickel (Ni) film, the 1st heat treatment of step S3 was preferably carried out under 400～500 ℃.For example, can be in inert gas or nitrogen atmosphere, use RTA (rapid thermal annealing (Rapid Thermal Anneal)) method, under the temperature about 410 ℃, Semiconductor substrate is carried out heat treatment more than 10 seconds, below 1 minute, carry out the 1st heat treatment of step S3 thus, be evenly distributed on the whole zone of the interarea of Semiconductor substrate 1, more preferably set low programming rate (about 3 ℃/second～10 ℃/second) in order to make the heat that is applied to metal film 12.
By the 1st heat treatment of step S3, as shown in figure 14, make the polysilicon film that constitutes gate electrode 8a, 8b and metal film 12, and formation n +N-type semiconductor N zone 9b and p +Monocrystalline silicon and the metal film 12 of N-type semiconductor N zone 10b optionally react, and forming the metal semiconductor conversion zone is metal silicide layer 41.In the present embodiment,, form the metal silicide layer of forming by single silicide (being MSi) of the metallic element M that constitutes metal film 12 41 by the 1st heat treatment of step S3.By making gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Each top (upper layer part) of N-type semiconductor N zone 10b and metal film 12 reactions form metal silicide layer 41, so metal silicide layer 41 is formed at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Each surface (upper layer part) of N-type semiconductor N zone 10b.
Promptly, the 1st heat treatment by step S3, the Si (silicon) of metallic element M that constitutes metal film 12 and the polysilicon that constitutes gate electrode 8a, 8b is reacted, and (M+Si → MSi), (upper layer part of gate electrode 8a, 8b) forms the metal silicide layer 41 that is made of MSi on the surface of gate electrode 8a, 8b.In addition, by the 1st heat treatment of step S3, make the metallic element M and the n that constitute metal film 12 +Si (silicon) reaction of N-type semiconductor N zone 9b (M+Si → MSi), at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) forms the metal silicide layer 41 that constitutes by MSi.By the 1st heat treatment of step S3, make the metallic element M and the p that constitute metal film 12 +Si (silicon) reaction of N-type semiconductor N zone 10b (M+Si → MSi), at p +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) forms the metal silicide layer of forming by MSi 41.
As mentioned above, in the 1st heat treatment of step S3, make (formation) gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b (silicon) optionally reacts with metal film 12, forms metal silicide layer 41, and in the 1st heat treated stage of carrying out step S3, metal silicide layer 41 becomes MSi (metal list silicide) phase, and does not become M 2Si (two metal silicides) phase or MSi 2(metal disilicide) phase.Herein, MSi (metal list silicide) is the single silicide that constitutes the metallic element M of metal film 12, MSi 2(metal disilicide) is the disilicide that constitutes the metallic element M of metal film 12.For example, metal film 12 is under the situation of nickel (Ni) film, and in the 1st heat treated stage of carrying out step S3, metal silicide layer 41 becomes NiSi (nickel monosilicide) phase, and does not become Ni 2Si (two nickel silicides) phase or NiSi 2(nickel disilicide) phase.
Need to prove that the present embodiment 1 reaches in the following embodiment 2～6, the metallic element that constitutes metal film 12 is M with the chemical formulation, is expressed as " メ Le (metal) " with katakana.For example, when metal film 12 was nickel (Ni) film, above-mentioned M (constituting the metallic element M of metal film 12) was Ni, and above-mentioned MSi (metal list silicide) is NiSi (nickel monosilicide), above-mentioned M 2Si (two metal silicides) is Ni 2Si (two nickel silicides), above-mentioned MSi 2(metal disilicide) is NiSi 2(nickel disilicide).Metal film 12 is that Ni is that 98 atom %, Pt are the Ni-Pt alloy film (Ni of 2 atom % 0.98Pt 0.02Alloy film) time, the above-mentioned M metallic element M of metal film 12 (constitute) is that (wherein, if consider the ratio of components of Ni and Pt, then above-mentioned M is Ni for Ni and Pt 0.98Pt 0.02), above-mentioned MSi is Ni 0.98Pt 0.02Si, above-mentioned M 2Si is (Ni 0.98Pt 0.02) 2Si, above-mentioned MSi 2Be Ni 0.98Pt 0.02Si 2Metal film 12 is that Ni is that 99 atom %, Pd are the Ni-Pd alloy film (Ni of 1 atom % 0.99Pt 0.01Alloy film) time, the above-mentioned M metallic element M of metal film 12 (constitute) is that (wherein, if consider the ratio of components of Ni and Pd, then above-mentioned M then is Ni for Ni and Pd 0.99Pd 0.01), above-mentioned MSi is Ni 0.99Pd 0.01Si, above-mentioned M 2Si is (Ni 0.99Pd 0.01) 2Si, above-mentioned MSi 2Be Ni 0.99Pd 0.01Si 2When being alloy films of other compositions, metal film 12 also can similarly consider.
Next, by carrying out wet clean process, remove barrier film 13 and unreacted metal film 12 (that is, not with gate electrode 8a, 8b, n +N-type semiconductor N zone 9b or p +The metal film 12 of N-type semiconductor N zone 10b reaction) (the step S4 of Fig. 9).At this moment, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Remaining metal silicide layer 41 on the surface of N-type semiconductor N zone 10b.The wet clean process of step S4 can be undertaken by the wet-cleaned of using sulfuric acid or the wet-cleaned of using sulfuric acid and aqueous hydrogen peroxide solution etc.
Next, Semiconductor substrate 1 is implemented the 2nd heat treatment (annealing in process) (the step S5 of Fig. 9).The 2nd heat treatment of step S5 preferably is being full of inert gas (for example argon (Ar) gas or helium (He) gas) or nitrogen (N 2) in the environment of atmosphere, under normal pressure, carry out.The 2nd heat treatment of step S5 is carried out under the heat treatment temperature of the 1st heat treated heat treatment temperature that is higher than above-mentioned steps S3.For example, can be in inert gas or nitrogen atmosphere, the 2nd heat treatment of step S5 is carried out in the heat treatment of using the RTA method that Semiconductor substrate 1 is implemented more than 10 seconds, below 1 minute thus.
By carrying out the 2nd heat treatment of this step S5, can stabilization metallic silicide layer 41.Promptly, form the metal silicide layer 41 of MSi phase by the 1st heat treatment of step S3, even this metal silicide layer 41 carries out the 2nd heat treatment of step S5, still be the MSi phase, but by carrying out the 2nd heat treatment of step S5, make the composition in the metal silicide layer 41 more even, metallic element M in the metal silicide layer 41 and the ratio of components of Si are in stoichiometric proportion, more near 1: 1, can stabilization metallic silicide layer 41.Need to prove that the resistivity of MSi phase is lower than M 2Si reaches MSi mutually 2Phase, after step S5 (manufacturing to semiconductor device finishes), metal silicide layer 41 is also kept low-resistance MSi phase, in the semiconductor device of making (even for example Semiconductor substrate 1 being formed under the state of semiconductor chip independently), metal silicide layer 41 becomes low-resistance MSi phase.
If the 2nd heat treated heat treatment temperature T of step S5 2Be lower than the 1st heat treated heat treatment temperature T of step S3 1Even, then carrying out the 2nd heat treatment of step S5, metal silicide layer 41 is also constant substantially, can not show the effect of stabilization metallic silicide layer 41, so, make the 2nd heat treated heat treatment temperature T of step S5 2The 1st heat treated heat treatment temperature T that is higher than step S3 1(T 2＞T 1).By the 1st heat treated heat treatment temperature T that is being higher than step S3 1Heat treatment temperature T 2(be T 2＞T 1) under carry out the 2nd heat treatment of step S5, can make the composition homogenizing in the metal silicide layer 41, the ratio of components that makes metallic element M in the metal silicide layer 41 and Si in stoichiometric proportion more near 1: 1, thereby stabilization metallic silicide layer 41.
But the inventor finds after deliberation if the 2nd heat treated heat treatment temperature T of step S5 2Too high, then the 2nd heat treatment of step S5 causes constituting the metallic element M excess diffusion of metal silicide layer 41, MSi 2(metal disilicide) easily from metal silicide layer 41 to groove misgrowth.In addition, also find to form unwanted MSi 2Part makes the resistance inequality of the metal silicide layer 41 of each field-effect transistor.
Therefore, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5 2The disilicide that is lower than the metallic element M that constitutes metal film 12 is MSi 2Lattice size (lattice constant) the consistent temperature T of the lattice size (lattice constant) of (metal disilicide) and Semiconductor substrate 1 3(the 1st temperature) (T 3＞T 2).Thus, when the 2nd heat treatment of carrying out step S5, can suppress or prevent MSi 2(metal disilicide) from metal silicide layer 41 to groove misgrowth, and, can suppress or prevent unwanted MSi 2The formation of part, thus the resistance inequality of each metal silicide layer 41 reduced.Afterwards this is elaborated.
Thus at gate electrode 8a and the source drain zone (n of n channel-type MISFETQn +N-type semiconductor N zone 9b) surface (upper layer part) and gate electrode 8b and the source drain zone (p of p channel-type MISFETQp +N-type semiconductor N zone 10b) surface (upper layer part) forms the metal silicide layer of being made up of MSi (metal list silicide) 41.In addition, the thickness of metal silicide layer 41 depends on the thickness of metal film 12, and when the thickness of metal film 12 for example was the 9nm left and right sides, the thickness of metal silicide layer 41 for example was about 19nm.
Next, as shown in figure 15, on the interarea of Semiconductor substrate 1, form dielectric film 42.That is, on Semiconductor substrate 1, comprise on the metal silicide layer 41, form dielectric film 42, with covering grid electrode 8a, 8b.Dielectric film 42 for example is made of silicon nitride film, can pass through the formation such as plasma CVD method of about 450 ℃ of film-forming temperatures (underlayer temperature).On dielectric film 42, form the dielectric film 43 of thickness then greater than dielectric film 42.Dielectric film 43 for example is made of silicon oxide film etc., can use TEOS (Tetra ethoxy silane: tetraethoxysilane, be also referred to as orthosilicic acid tetraethyl ester (Tetra Ethyl Ortho Silicate)), by the formation such as plasma CVD method of about 450 ℃ of film-forming temperatures.Form the interlayer dielectric that constitutes by dielectric film 42,43 thus.Then, the surface of dielectric film 43 is ground etc., make the top smooth of dielectric film 43 by the CMP method.Even because the substrate unevenness forms concaveconvex shape on the surface of dielectric film 42, also can obtain the interlayer dielectric of its flattening surface by the surface that utilizes the CMP method to grind dielectric film 43.
Next, as shown in figure 16, use the photoresist pattern (not shown) that is formed on the dielectric film 43 as etching mask, dry ecthing dielectric film 43,42 forms contact hole (through hole, hole) 44 thus on dielectric film 42,43.At this moment, at first comparing dry ecthing dielectric film 43 under the dielectric film 43 easy etched conditions with dielectric film 42, stop (Etching Stopper) film with dielectric film 42 as etching, after forming contact hole 44 on the dielectric film 43, remove the dielectric film 42 of the bottom of contact hole 44 comparing under the dielectric film 42 easy etched conditions dry ecthing with dielectric film 43.In the bottom of contact hole 44, expose a part, for example n of the interarea of Semiconductor substrate 1 +N-type semiconductor N zone 9b and p +The part of the part of the lip-deep metal silicide layer 41 of N-type semiconductor N zone 10b or the lip-deep metal silicide layer 41 of gate electrode 8a, 8b etc.
Next, in contact hole 44, form by tungsten (W) and wait the embolism (plug) (connecting usefulness conductor portion, flush type embolism, buried conductor portion) 45 that constitutes.In order to form embolism 45, for example, on dielectric film 43, comprise the inside (on bottom and the sidewall) of contact hole 44, by the plasma CVD method formation insulated conductor film 45a (for example titanium film, titanium nitride film or their laminate film) of about 450 ℃ of film-forming temperatures (underlayer temperature).Then, on insulated conductor film 45a, form the leading body film 45b that constitutes by tungsten film etc. by CVD method etc., with landfill contact hole 44, utilize CMP method or etching method etc. to remove unwanted leading body film 45b and insulated conductor film 45a on the dielectric film 43, can form embolism 45 thus.Be formed at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b or p +Embolism 45 on the 10b of N-type semiconductor N zone is at its bottom and gate electrode 8a, 8b, n +N-type semiconductor N zone 9b or p +The lip-deep metal silicide layer 41 of N-type semiconductor N zone 10b connects, thereby is electrically connected.
Next, as shown in figure 17, on the dielectric film 43 of having imbedded embolism 45, form prevention dielectric film 51 and wiring formation dielectric film 52 successively.Stoping dielectric film 51 is to add and stop etched film man-hour dielectric film 52 being carried out ditch, and uses the material that has etching selectivity with respect to dielectric film 52.Stoping dielectric film 51 for example can be the silicon nitride film that forms by plasma CVD method, and dielectric film 52 for example can be the silicon oxide film that forms by plasma CVD method.In addition, stoping the 1st layer of wiring of explanation below the formation on dielectric film 51 and the dielectric film 52.
Next, utilize (single damascene) method of singly inlaying to form the 1st layer of wiring.At first, with resist pattern (not shown) is that mask carries out dry ecthing, at dielectric film 52 and after stoping the regulation zone formation wiring trench 53 of dielectric film 51, (be on the dielectric film 52, comprising the bottom and the sidewall of wiring trench) formation insulated conductor film (barrier metal film) 54 on the interarea of Semiconductor substrate 1.Insulated conductor film 54 for example can use titanium nitride film, tantalum film or nitrogenize tantalum film etc.Next, utilize CVD method or sputtering method etc. on insulated conductor film 54, to form the Seed Layer (seed layer) of copper, further use electroplating method etc. on Seed Layer, to form plated copper film.Inside by plated copper film landfill wiring trench 53.Then, utilize the CMP method to remove plated copper film, Seed Layer and the barrier metal film 54 in wiring trench 53 zone in addition, form the 1st layer of wiring 55 of taking electric material with copper as the leading factor.Wiring 55 is by source electrode or the drain electrode n of embolism 45 with n channel-type MISFETQn and p channel-type MISFETQp +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b, electrical connections such as gate electrode 8a, 8b.Then, utilize dual damascene (dual damascene) method to form the 2nd layer of wiring, omit diagram and explanation thereof herein.
Next, illustrate in greater detail the effect of the present embodiment.Figure 18 is the process chart of formation operation of NiSi layer 141b in the semiconductor device of expression comparative example, corresponding to Fig. 9 of the present embodiment.Figure 19～Figure 21 is the major part profile in the semiconductor device manufacturing process of comparative example.Figure 22 is the major part profile in the semiconductor device manufacturing process of comparative example, and expression has formed the zone corresponding to the n channel-type MISFET in the operation stage of Figure 21.
In the semiconductor device of the comparative example of Figure 18～Figure 22, the NiSi layer 141b that is equivalent to the metal silicide layer 41 of the present embodiment formed by the operation that is different from the present embodiment, in addition, makes in the same manner with the semiconductor device of the present embodiment.
When making the semiconductor device of comparative example, obtain being equivalent to as shown in figure 19, on the interarea of Semiconductor substrate 1, comprising gate electrode 8a, 8b, n after the structure of above-mentioned Fig. 7 of the present embodiment +N-type semiconductor N zone 9b and p +On the 10b of N-type semiconductor N zone, deposition Ni film 112 (metal film 12 that is equivalent to the present embodiment) (the step S101 of Figure 18).Then, deposited titanium nitride film 113 (barrier film 13 that is equivalent to the present embodiment) (the step S102 of Figure 18) on Ni film 112.Then, as shown in figure 20, utilize the RTA method under about 320 ℃, to carry out left and right sides heat treatment in 30 seconds, make (formation) gate electrode 8a, 8b, n thus +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b (silicon) optionally reacts with Ni film 112, thereby at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Form Ni on the surface of N-type semiconductor N zone 10b 2Si (two nickel silicides) layer 141a (the step S103 of Figure 18).
Next, by carrying out wet clean process, remove titanium nitride film 113 and unreacted Ni film 112 (the step S104 of Figure 18) after, utilize the RTA method about 550 ℃, to carry out left and right sides heat treatment in 30 seconds (the step S105 of Figure 18).Make Ni 2Si layer 141a and gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The silicon (Si) of N-type semiconductor N zone 10b further reacts in the heat treatment of step S105 and (carries out Ni 2The reaction of Si+Si → 2NiSi), as shown in figure 21, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Form on the surface of N-type semiconductor N zone 10b by with Ni 2Si compares NiSi layer 141b stable and that constitute mutually for the NiSi of low-resistivity.That is, the heat treatment of the step S103 by the front forms Ni 2Si phase (Ni 2Si layer 141a), make it in the heat treatment of thereafter step S105, become NiSi phase (NiSi layer 141b).Then, the semiconductor device of comparative example also is identically formed dielectric film 42,43, contact hole 44, embolism 45, stops dielectric film 51, dielectric film 52 and connect up 55 with the present embodiment, omits its diagram and explanation here.Make the semiconductor device of comparative example thus.
When forming cobalt silicide, Si (silicon) plants for diffusion, and is mobile in the Co film by Si, form cobalt silicide, and when forming nickel silicide, Ni (nickel) plants for spreading, and to the silicon area side shifting, forms nickel silicide by Ni (nickel).
The inventor scrutinizes the semiconductor device of the comparative example of making as mentioned above, finds NiSi 2(nickel disilicide) easily from NiSi layer 141b to groove misgrowth.Among Figure 22 with NiSi 2Be expressed as NiSi easy excrescent region mode 2Misgrowth zone 141c.Above-mentioned NiSi 2The generation of misgrowth zone 141c obtains confirming by the inventor's experiment (the section observation of semiconductor device and the composition analysis of section etc.).And if discovery NiSi 2To groove misgrowth, then cause the leakage current between the source drain of MISFET to increase from NiSi layer 141b, perhaps cause the diffusion resistance in source drain zone to increase.
So in the present embodiment, as mentioned above, step S1 is on the interarea of Semiconductor substrate 1, comprises gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +On the 10b of N-type semiconductor N zone, depositing metallic films 12 carries out step S2 then, promptly on metal film 12, deposit barrier film 13, carry out the 1st heat treatment then,, form the metal silicide layer 41 of MSi (metal list silicide) phase by the 1st heat treatment as step S3.That is,, make (formation) gate electrode 8a, 8b, n by the 1st heat treatment of step S3 +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b (silicon) optionally react with metal film 12, formation metal silicide layer 41, and in the 1st heat treated stage of carrying out this step S3, metal silicide layer 41 is not M 2Si (two metal silicides) phase or MSi 2(metal disilicide) phase, but MSi (metal list silicide) phase.For example, when metal film 12 was nickel (Ni) film, in the 1st heat treated stage of carrying out step S3, metal silicide layer 41 was not Ni 2Si (two nickel silicides) phase or NiSi 2(nickel disilicide) phase, but NiSi (nickel monosilicide) phase.Therefore, in the present embodiment, under the heat treatment temperature of the heat treatment temperature of the step S103 that is higher than above-mentioned comparative example, carry out the 1st heat treatment of step S3.When metal film 12 was nickel (Ni) film, the 1st heat treated heat treatment temperature of step S3 preferably in 400～500 ℃ scope, for example can be made as 410 ℃.
On Semiconductor substrate, form p +Type silicon area and n +The type silicon area forms Ni film about 10nm and TiN (titanium nitride) film about 15nm thereon, makes Ni film and p by heat treatment then +Type silicon area and n +The reaction of type silicon area forms nickel silicide layer, removes unreacted Ni film and TiN film, and Figure 23 is the expression dependent curve of heat treatment temperature of the sheet resistance (sheetresistance) of the nickel silicide layer of formation at this moment.The transverse axis of the curve of Figure 23 is corresponding to make Ni film and p by heat treatment +Type silicon area and n +The heat treatment temperature of type silicon area reaction, the longitudinal axis of the curve of Figure 23 is corresponding to the sheet resistance value of the nickel silicide layer that forms by this heat treatment.The heat treatment that Figure 23 carried out is to utilize RTA to carry out about 30 seconds.In addition, in the curve of Figure 23, with white circle (p +Type silicon area+Ni film) expression makes Ni film and p by heat treatment +The sheet resistance value of the nickel silicide layer that the reaction of type silicon area forms is with black circle (n +Type silicon area+Ni film) expression makes Ni film and n by heat treatment +The sheet resistance value of the nickel silicide layer that the reaction of type silicon area forms.
Shown in the curve of Figure 23, for nickel silicide layer, the sheet resistance of NiSi (nickel monosilicide) phase time is lower than Ni 2Si (two nickel silicides) phase (Ni 2The Si phase time is about 30 Ω/, the NiSi phase time is about 10 Ω/).By the curve chart of Figure 23 as can be known, if heat treatment temperature is low, then the nickel silicide layer of Xing Chenging is high-resistance Ni 2The Si phase, if improve heat treatment temperature, then the nickel silicide layer of Xing Chenging becomes low-resistance NiSi phase.In addition, with make Ni film and n by heat treatment +The nickel silicide layer that the reaction of type silicon area forms (corresponding to deceiving the curve that circle is represented among Figure 23) is compared, and makes Ni film and p by heat treatment +The nickel silicide layer that type silicon area reaction forms (curve of representing corresponding to white circle among Figure 23) is from Ni 2The temperature that Si is phase-changed into the NiSi phase low (that is, can under lower heat treatment temperature, form the NiSi phase).Heat treatment temperature is more than 400 ℃ the time, p +Type silicon area and n +Arbitrary zone in the type silicon area all can form the nickel silicide layer of NiSi phase.
In the above-mentioned comparative example, for the heat treatment by step S103 forms Ni 2Si layer 141a, the heat treatment temperature of step S103 is lower than the temperature that forms the NiSi phase, for example is about 320 ℃.And in the present embodiment,, and do not form M for the 1st heat treatment by step S3 forms MSi phase metal silicide layer 41 2Si phase metal silicide layer 41, the 1st heat treatment of step S3 is carried out under the heat treatment temperature that can form the MSi phase (temperature that is higher than the minimum heat treatment temperature that can form the MSi phase).When for example metal film 12 was nickel (Ni) film, as shown in Figure 23, the 1st heat treatment of step S3 was preferably carried out under the temperature more than 400 ℃, for example carries out under about 410 ℃.Thus,, can make metal silicide layer 41 be MSi (metal list silicide) phase in the 1st heat treated stage of carrying out step S3, rather than M 2Si (two metal silicides) phase.
But, in the 1st heat treatment of step S3, along with moving of metallic element M, the reaction of M+Si → MSi takes place, because metallic element M is the state that moves easily, so, if heat treatment temperature is too high, even then there is barrier film 13, also might cause metallic element M excess diffusion (moving), part forms MSi 2(metal disilicide).In addition, if being higher than from MSi, the 1st heat treated heat treatment temperature of step S3 is phase-changed into MSi 2The temperature of phase then causes metal silicide layer 41 all to become MSi 2Phase.Therefore, when for example metal film 12 was nickel (Ni) film, the 1st heat treated heat treatment temperature of step S3 was preferably below 500 ℃, more preferably is below 450 ℃, can prevent to form when forming the metal silicide layer of being made up of MSi 41 MSi thus 2So when metal film 12 was nickel (Ni) film, the 1st heat treated heat treatment temperature of step S3 was preferably in 400～500 ℃ scope.
When carrying out the heat treatment of the reaction that causes with metallic element M diffusion (moving), MSi takes place in metallic element M Anomalous Diffusion easily 2Misgrowth from metal silicide course groove.In the present embodiment, in the 1st heat treatment of step S3, owing to follow the reaction of the M+Si → MSi that moves of metallic element M, metallic element M is the state that moves easily, so, the possible Anomalous Diffusion of metallic element M, and then MSi takes place 2To groove misgrowth, but barrier film 13 prevents the generation of above-mentioned situation from metal silicide layer 41.
That is, above-mentioned comparative example is under the state that nickel silicide layer is not covered by barrier film, carries out undergoing phase transition of nickel silicide layer and (makes Ni 2Si layer 141a becomes NiSi layer 141b) and so on heat treatment (heat treatment of above-mentioned steps S105), cause having oxygen (O) forming NiSi phase time surface.Therefore, the defective that oxygen causes increases, and by the defective that produces, Ni becomes and spreads easily, thereby impels NiSi in the heat treatment that is used to form NiSi layer 141b 2Misgrowth.
And in the present embodiment, when the 1st heat treatment by step S3 formed the metal silicide layer of being made up of MSi 41, barrier film 13 suppressed or the seeing through of anti-block (O), thereby can prevent to metal silicide layer 41 supply oxygen (O).Thus, when the 1st heat treatment by step S3 forms the metal silicide layer 41 that is made of MSi, can suppress or prevent to produce the defective that oxygen causes, and can suppress or prevent metallic element M to be spread by the defective that oxygen causes.So, can suppress or prevent MSi when the 1st heat treatment of step S3 2From metal silicide layer 41 to groove misgrowth.In order to improve above-mentioned effect, barrier film 13 is not preferably the film that sees through (being difficult to see through) oxygen (O), and promptly barrier film 13 is preferably the film of no oxygen permeability, as such barrier film 13, and preferred titanium nitride (TiN) film or titanium (Ti) film.
In the present embodiment, barrier film 13 is preferably the film that makes Semiconductor substrate 1 produce tensile stress.That is, be that barrier film 13 is arranged under the state on the metal film 12 at the film that will make Semiconductor substrate 1 produce tensile stress, carry out the 1st heat treatment of step S3, make metal film 12 and silicon area ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) reaction, the metal silicide layer 41 of formation MSi phase.
In the lattice size of Semiconductor substrate 1 near MSi 2Under the state of the lattice size of (metal disilicide), when carrying out the heat treatment of the reaction that causes with metallic element M diffusion (moving), between the lattice of metallic element M and Si (Si of formation Semiconductor substrate 1), replace easily, so, the easy Anomalous Diffusion of metallic element M in the heat treatment, MSi 2Easily from metal silicide layer 41 to groove misgrowth.
And in the present embodiment, by under the state that has formed the barrier film 13 that makes Semiconductor substrate 1 produce tensile stress, carry out the 1st heat treatment of step S3, compare with the situation that does not have barrier film 13 thus, can be under the effect of the tensile stress that barrier film 13 produces, increase the lattice size of Semiconductor substrate 1, can increase the lattice size and the MSi of Semiconductor substrate 1 2The lattice size of (metal disilicide) poor.Therefore, can suppress or prevent MSi when the 1st heat treatment of step S3 2From metal silicide layer 41 to groove misgrowth.
In addition, in the present embodiment, as mentioned above, after the 1st heat treatment of carrying out step S3 forms the metal silicide layer 41 of MSi phase, carry out wet clean process as step S4, remove barrier film 13, unreacted metal film 12 thus, carry out the 2nd heat treatment as step S5 then.In the present embodiment, the 1st heat treated stage of carrying out step S3, metal silicide layer 41 has become the MSi phase, even carry out the 2nd heat treatment of step S5, metal silicide layer 41 also still is the MSi phase, before and after the 2nd heat treatment of step S5, the phase of metal silicide layer 41 (MSi phase) is constant.Different with the heat treatment of the step S105 of comparative example, the 2nd heat treatment of the step S5 of the present embodiment is not in order to make metal silicide layer 41 undergoing phase transition (from M 2Si is phase-changed into the MSi phase) and the processing carried out, but the stabilizing annealing that carries out for stabilization metallic silicide layer 41.After the 2nd heat treatment of step S5, to the manufacturing of semiconductor device, finish (for example, to cutting semiconductor substrate 1 form independently semiconductor chip), do not make the temperature of Semiconductor substrate 1 be higher than the 2nd heat treated heat treatment temperature T of step S5 2Promptly, various heating processes after the 2nd heat treatment of step S5 (for example, the operation of the heating of following Semiconductor substrate 1 of film formation process of various dielectric films or electrically conductive film and so on) in, do not make the temperature of Semiconductor substrate 1 be higher than the 2nd heat treated heat treatment temperature T of step S5 2, after the 2nd heat treatment of step S5, do not make the temperature of Semiconductor substrate 1 be higher than the 2nd heat treated heat treatment temperature T 2Processing.In other words, make the 2nd heat treated heat treatment temperature T of step S5 in advance 2The heating-up temperature that is higher than the Semiconductor substrate 1 in step S5 all heating processes (operation of the heating of following Semiconductor substrate 1 of film formation process of for example various dielectric films or electrically conductive film and so on) afterwards.Thus, can prevent that the heating (film formation process of for example various dielectric films or electrically conductive film) in the step S5 operation afterwards from making the metallic element M that constitutes metal silicide layer 41 (MSi phase) be diffused into Semiconductor substrate 1 (gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) situation that causes the characteristic variations of MISFET in.
Under the 2nd heat treated situation of not carrying out step S5 different with the present embodiment, condition according to thereafter heating process (operation of the heating of following Semiconductor substrate 1 of film formation process of for example various dielectric films or electrically conductive film and so on), the characteristic of metal silicide layer 41 might change, so, must manage or redesign the operation of the heating of following Semiconductor substrate 1 cautiously.And in the present application, because by carrying out the heat treatment stabilization metallic silicide layer 41 of step S5, so can suppress or prevent the characteristic variations of the metal silicide layer 41 that the condition by the heating process (operation of the heating of following Semiconductor substrate 1 of film formation process of for example various dielectric films or electrically conductive film and so on) after the step S5 causes, and follow the management or the redesign of operation of the heating of Semiconductor substrate 1 easily.
Preferred the 2nd heat treated heat treatment temperature T that makes step S5 in advance 2Be higher than the heating-up temperature of the Semiconductor substrate 1 in step S5 all heating processes (operation of the heating of following Semiconductor substrate 1 of film formation process of for example various dielectric films or electrically conductive film and so on) afterwards, can after step S5, do not make the temperature of Semiconductor substrate 1 be higher than the 2nd heat treated heat treatment temperature T thus 2Processing.If like this, the characteristic of metal silicide layer 41 just can not be subjected to the influence of variation of the condition of the heating process (operation of the heating of following Semiconductor substrate 1 of film formation process of for example various dielectric films or electrically conductive film and so on) after the step S5.So, the operation of the heating of following Semiconductor substrate 1 after as easy as rolling off a log management or the redesign step S5.
As mentioned above, by carrying out the 2nd heat treatment of step S5, can obtain the stabilization effect of metal silicide layer 41 and prevent the effect etc. of characteristic variations.
In the 1st heat treatment of step S3, because the reaction of M+Si → MSi takes place, so metallic element M spreads (moving) in a large number to silicon area ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) in, by comparison, in the 2nd heat treatment of step S5, (M+Si → MSi) is so the metallic element M in the metal silicide layer 41 is difficult to diffusion (moving) to silicon area because above-mentioned reaction does not take place.In addition, the 1st heat treatment of step S3 is carried out under the state that has formed metal film 12, thus supply with metallic element M by metal film 12, but the 2nd heat treatment of step S5 carries out under the state of having removed metal film 12, so do not resupply metallic element M.Therefore, stability for the metal silicide layer 41 of the MSi phase that improves the 1st heat treated stage of having carried out step S3, the 2nd heat treatment by step S5 improve the MSi phase metal silicide layer 41 stability and improve the 1st heat treatment phase ratio of step S3, can prevent MSi effectively 2From final metal silicide layer 41 to groove misgrowth.
But, according to discovering of the inventor, in the 2nd heat treatment of step S5, according to heat treatment temperature T 2Difference, the metallic element M that constitutes metal silicide layer 41 also might excess diffusion, makes MSi 2(metal disilicide) from metal silicide layer 41 to groove misgrowth.In addition, also find, according to the 2nd heat treated heat treatment temperature T of step S5 according to the inventor's research 2Difference, might form unwanted MSi 2Part, thus make the resistance inequality of metal silicide layer 41 in each field-effect transistor.Describe the 2nd heat treated heat treatment temperature T of this step S5 below in detail 2
The 2nd heat treated heat treatment temperature T of step S5 2If be lower than the 1st heat treated heat treatment temperature T of step S3 1Even, then carrying out the 2nd heat treatment of step S5, metal silicide layer 41 is also constant substantially, can't obtain the stabilization effect of metal silicide layer 41, so, must make the 2nd heat treated heat treatment temperature T of step S5 2The 1st heat treated heat treatment temperature T that is higher than step S3 1(T 2＞T 1).By making the 2nd heat treated heat treatment temperature T of step S5 2The 1st heat treated heat treatment temperature T that is higher than step S3 1(T 2＞T 1), can make the composition in the metal silicide layer 41 more even by the 2nd heat treatment of step S5, metallic element M in the metal silicide layer 41 and the ratio of components of Si in stoichiometric proportion more near 1: 1, and then can stabilization metallic silicide layer 41.By stabilization metallic silicide layer 41, can suppress leakage current between the source drain of MISFET etc.
But, if the 2nd heat treated heat treatment temperature T of step S5 2Too high, then the 2nd heat treatment of step S5 makes and the metallic element M excess diffusion that constitutes metal silicide layer 41 causes MSi 2(metal disilicide) easily from metal silicide layer 41 to groove misgrowth.That is, if the 2nd heat treated heat treatment temperature T of step S5 2Too high, then cause taking place NiSi among above-mentioned Figure 22 2The represented MSi of misgrowth zone 141c 2The misgrowth of (metal disilicide).Confirmed the 2nd heat treated heat treatment temperature T of step S5 according to the inventor's experiment (the section observation of semiconductor device and the composition analysis of section etc.) 2Cause MSi 2(metal disilicide) from metal silicide layer 41 to groove misgrowth.This MSi 2(metal disilicide) causes the leakage current between the source drain of field-effect transistor to increase as mentioned above to the misgrowth of groove from metal silicide layer 41, perhaps cause the diffusion resistance in source drain zone to increase, so, in order to improve the Performance And Reliability of field-effect transistor, must prevent MSi 2(metal disilicide) is from the misgrowth of metal silicide layer 41 to groove.
The inventor has studied the 2nd heat treatment and the MSi of step S5 2(metal disilicide) obtains following the discovery from the excrescent relation of metal silicide layer 41 to groove.That is, make the 2nd heat treated heat treatment temperature T of step S5 2The disilicide that is lower than the metallic element M that constitutes metal film 12 is MSi 2Lattice size (lattice constant) the consistent temperature T of the lattice size (lattice constant) of (metal disilicide) and Semiconductor substrate 1 3(T 2＜T 3) utmost point prevented MSi effectively 2(metal disilicide) from metal silicide layer 41 to groove misgrowth.This is because in the heat treatment, if be in Semiconductor substrate 1 and MSi 2MSi then takes place in state that the lattice size (lattice constant) of (metal disilicide) is consistent easily 2(metal disilicide) is from the misgrowth of metal silicide layer 41 to groove.Need to prove that the lattice size is meant lattice constant (length of elementary cell) among the application.
That is, if the lattice size of Semiconductor substrate 1 away from MSi 2The lattice size of (metal disilicide), even then carry out the 2nd heat treatment of step S5, also be difficult between the lattice of metallic element M and Si replace, so, metallic element M is difficult to diffuse to semiconductor substrate region (monocrystalline silicon region) from the metal silicide layer 41 of MSi phase, and then is difficult to generate MSi 2(metal disilicide) part.On the contrary, if the lattice size of Semiconductor substrate 1 near MSi 2The lattice size of (metal disilicide), then replace easily between the lattice of metallic element M and Si, so under heat treated effect, metallic element M diffuses to semiconductor substrate region (monocrystalline silicon region) from the metal silicide layer 41 of MSi phase easily, and then generates MSi easily 2(metal disilicide) part.Therefore, when carrying out the 2nd heat treatment of step S5, only otherwise be in Semiconductor substrate 1 and MSi 2The state that the lattice size (lattice constant) of (metal disilicide) is consistent just can suppress or prevent MSi 2(metal disilicide) is from the misgrowth of metal silicide layer 41 to groove.
So, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than MSi 2The lattice size of (metal disilicide) and the lattice temperature T of the same size of Semiconductor substrate 1 3(T 2＜T 3), thus, when the 2nd heat treatment of carrying out step S5, can not be in Semiconductor substrate 1 and MSi 2The lattice state of the same size of (metal disilicide).Thus, by the 2nd heat treatment of step S5, can suppress or prevent MSi 2(metal disilicide) from the misgrowth of metal silicide layer 41 to groove, and can prevent to produce in the semiconductor device of making the MSi from metal silicide layer 41 to groove 2The misgrowth zone of (metal disilicide).
Next, to Semiconductor substrate 1 for monocrystalline silicon (Si) substrate, metal film 12 for nickel (Ni) film, metal silicide layer 41 the suitable example during for nickel silicide (NiSi) layer carry out more specific description.In such cases, above-mentioned metallic element M is Ni (nickel), and above-mentioned MSi becomes NiSi (nickel monosilicide), above-mentioned MSi 2Become NiSi 2(nickel disilicide).
Figure 24 is expression monocrystalline silicon (Si) and NiSi 2The temperature dependent curve chart of the lattice size of (nickel disilicide).The transverse axis of the curve of Figure 24 is corresponding to temperature, and the longitudinal axis of the curve of Figure 24 is corresponding to mismatch (mismatch) α of lattice size or lattice size described later.In the curve of Figure 24, represent that with solid line the lattice size of monocrystalline silicon (Si) is (corresponding to lattice constant, lattice described later size L SOr length L 1) temperature dependency, represent NiSi with chain-dotted line 2The lattice size of (nickel disilicide) is (corresponding to lattice constant, lattice described later size L MOr length L 2) temperature dependency.In addition, dot the lattice size and the NiSi of monocrystalline silicon (Si) 2The temperature dependency of the mismatch α of the lattice size of (nickel disilicide).
Monocrystalline silicon (Si) and NiSi 2(nickel disilicide) all expands with the rising of temperature, but both coefficient of linear expansion (thermal coefficient of expansion) difference.Shown in the curve of Figure 24, monocrystalline silicon (Si) lattice size at room temperature is greater than NiSi 2(nickel disilicide), but NiSi 2The coefficient of linear expansion of (nickel disilicide) is greater than monocrystalline silicon (Si), so, raise monocrystalline silicon (Si) and NiSi from room temperature with temperature 2The difference of the lattice size of (nickel disilicide) is dwindled gradually.And, in temperature T 4The time silicon metal (Si) and NiSi 2Lattice size (lattice constant) unanimity of (nickel disilicide).If temperature is higher than temperature T 4, NiSi then 2The lattice size of (nickel disilicide) is greater than monocrystalline silicon (Si).Monocrystalline silicon (Si) and NiSi 2The lattice temperature T of the same size of (nickel disilicide) 4Be about 590 ℃ of (T 4=590 ℃).
If the lattice size of Semiconductor substrate 1 is away from NiSi 2The lattice size of (nickel disilicide), even then carry out the 2nd heat treatment of step S5, between the lattice of Ni and Si, also be difficult to replace, so, Ni is difficult to diffuse to semiconductor substrate region (monocrystalline silicon region) from the nickel silicide layer of NiSi phase (metal silicide layer 41), and then is difficult to generate NiSi 2(nickel disilicide) part.But, if different with the present embodiment, the 2nd heat treated heat treatment temperature T of step S5 2Be temperature T 4More than (T 2〉=T 4), then when the 2nd heat treatment of step S5, when the temperature of Semiconductor substrate 1 reaches temperature T 4, generation constitutes the lattice size and the NiSi of the monocrystalline silicon (Si) of Semiconductor substrate 1 2The lattice state of the same size of (nickel disilicide).At this moment, replace easily between the lattice of Ni and Si, cause Ni to diffuse to monocrystalline silicon region (semiconductor substrate region), promote NiSi from nickel silicide layer (metal silicide layer 41) 2The misgrowth of (nickel disilicide).
Therefore, in the present embodiment, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for the Ni film, makes the 2nd heat treated heat treatment temperature T of step S5 2Be lower than temperature T 4(T 2＜T 4).Thus, when the 2nd heat treatment of step S5, to end, the lattice size of the monocrystalline silicon (Si) of formation Semiconductor substrate 1 is always greater than NiSi from beginning in the 2nd heat treatment 2The lattice size of (nickel disilicide) is difficult to constitute the lattice size and the NiSi of the monocrystalline silicon (Si) of Semiconductor substrate 1 2The lattice state of the same size of (nickel disilicide).So, can suppress or prevent NiSi in the 2nd heat treatment of step S5 2(nickel disilicide) from the nickel silicide layer (metal silicide layer 41) of NiSi phase to groove misgrowth.
As mentioned above, monocrystalline silicon (Si) and NiSi 2Lattice size (lattice constant) the consistent temperature T of (nickel disilicide) 4Be about 590 ℃ of (T 4=590 ℃), so, be monocrystalline silicon (Si) substrate and metal film 12 during in Semiconductor substrate 1 for nickel (Ni) film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than temperature T 4I.e. 590 ℃ of (T 2＜T 4=590 ℃).
Next, be described more specifically Semiconductor substrate 1 for monocrystalline silicon (Si) substrate, metal film 12 for the alloy film of nickel (Ni) and platinum (Pt), be that Ni-Pt alloy film, metal silicide layer 41 are nickel Platinum Silicide (Ni 1-xPt xSi) the suitable example in when layer.In such cases, above-mentioned metallic element M is Ni and Pt, and above-mentioned MSi is Ni 1-xPt xSi, above-mentioned MSi 2Be Ni 1-xPt xSi 2
Figure 25 is expression monocrystalline silicon (Si) and Ni 1-xPt xSi 2The temperature dependent curve of lattice size, corresponding to above-mentioned Figure 24.The transverse axis of the curve of Figure 25 is corresponding to temperature, and the longitudinal axis of the curve of Figure 25 is corresponding to the mismatch α of lattice size or lattice size described later.In the curve of Figure 25, represent that with solid line the lattice size of monocrystalline silicon (Si) is (corresponding to lattice constant, lattice described later size L SOr length L 1) temperature dependency, represent Ni with chain-dotted line 1-xPt xSi 2The lattice size (corresponding to lattice constant, lattice described later size L MOr length L 2) temperature dependency.In addition, dot the lattice size and the Ni of monocrystalline silicon (Si) 1-xPt xSi 2The temperature dependency of mismatch α of lattice size.But that the curve of Figure 25 is represented is Ni 1-xPt xSi 2The situation of middle x=0.02, i.e. Ni 1-xPt xSi 2Be Ni 0.98Pt 0.02Si 2Situation.As mentioned above, Ni 1- xPt xSi 2X when being x=0.02, be 2.0 atom % (ratio of Ni is 98 atom %), be that metal film 12 is Ni corresponding to the ratio of the Pt in the Ni-Pt alloy film that constitutes metal film 12 0.98Pt 0.02The situation of alloy film.
The temperature dependency of the lattice size of the monocrystalline silicon (Si) among the temperature dependency of the lattice size of the monocrystalline silicon shown in Figure 25 (Si) and above-mentioned Figure 24 is identical.On the other hand, Ni 1-xPt xSi 2Lattice size (the lattice size under the room temperature) can use Vegard theorem (Vegard rule) to obtain.NiSi 2The part (site with respect to Ni is 2% herein) in Ni site replaced by Pt, relatively Figure 24 and Figure 25 as can be known, Ni 0.98Pt 0.02Si 2Lattice size (the lattice size under the room temperature) greater than NiSi 2Lattice size (the lattice size under the room temperature).And, Pt containing ratio hour, for example Ni 1-xPt xSi 2When middle x is 0.02 (x=0.02) left and right sides, can be considered as Ni 1-xPt xSi 2(be Ni 0.98Pt 0.02Si 2) coefficient of linear expansion (thermal coefficient of expansion) and NiSi 2Coefficient of linear expansion (thermal coefficient of expansion) roughly the same.The Ni that so obtains 1-xPt xSi 2(Ni among Figure 25 0.98Pt 0.02Si 2) the temperature dependency of lattice size shown in the curve of Figure 25.
Shown in the curve of Figure 25, Ni 1-xPt xSi 2Lattice size at room temperature is greater than monocrystalline silicon (Si), Ni 1-xPt xSi 2Coefficient of linear expansion greater than monocrystalline silicon (Si), but rise monocrystalline silicon (Si) and Ni from room temperature with temperature 1-xPt xSi 2The lattice difference in size dwindle.And, in temperature T 5The time silicon metal (Si) and Ni 1-xPt xSi 2Lattice size consistent, if temperature is higher than temperature T 5, Ni then 1-xPt xSi 2The lattice size greater than monocrystalline silicon (Si).Ni 1-xPt xSi 2In x be 0.02 o'clock (be Ni 0.98Pt 0.02Si 2The time), monocrystalline silicon (Si) and Ni 1-xPt xSi 2Lattice temperature T of the same size 5Be about 495 ℃ of (T 5=495 ℃).
In the present embodiment, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for the Ni-Pt alloy film, makes the 2nd heat treated heat treatment temperature T of step S5 2Be lower than monocrystalline silicon (Si) and Ni 1-xPt xSi 2Lattice temperature T of the same size 5(T 2＜T 5).Thus, when the 2nd heat treatment of step S5, to end, the lattice size (lattice constant) of the monocrystalline silicon (Si) of formation Semiconductor substrate 1 is all the time greater than Ni from beginning in the 2nd heat treatment 1-xPt xSi 2The lattice size, do not constitute the lattice size and the Ni of the monocrystalline silicon (Si) of Semiconductor substrate 1 1-xPt xSi 2Lattice state of the same size.So, can suppress or prevent Ni in the 2nd heat treatment of step S5 1-xPt xSi 2From Ni 1-xPt xThe nickel silicide layer that contains Pt of Si phase (metal silicide layer 41) is to groove misgrowth.
As mentioned above, monocrystalline silicon (Si) and Ni 0.98Pt 0.02Si 2Lattice temperature T of the same size 5Be about 495 ℃ of (T 5=495 ℃).Therefore, be that monocrystalline silicon (Si) substrate and metal film 12 are Ni in Semiconductor substrate 1 0.98Pt 0.02(with the Ni containing ratio is that 98 atom %, Pt containing ratio are that the alloy film of 2.0 atom % is expressed as Ni to film 0.98Pt 0.02Film or Ni 0.98Pt 0.02Alloy film) time, makes the 2nd heat treated heat treatment temperature T of step S5 2Be lower than temperature T 5I.e. 495 ℃ of (T 2＜T 5=495 ℃).
In addition, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for the Ni-Pt alloy film, according to the Pt containing ratio in the metal film 12, and said temperature T 5Change.When the Pt containing ratio in the Ni-Pt alloy film (metal film 12) is 2.0 atom %, said temperature T 5Be about 495 ℃, the Pt containing ratio in the Ni-Pt alloy film (metal film 12) is during less than 2.0 atom %, said temperature T 5Be offset to and be higher than about 495 ℃ temperature, the Pt containing ratio in the Ni-Pt alloy film (metal film 12) is during greater than 2.0 atom %, said temperature T 5Be offset to and be lower than about 495 ℃ temperature.
In addition, said temperature T 4Or said temperature T 5Corresponding to said temperature T 3That is, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for nickel (Ni) film, the lattice size and the MSi of Semiconductor substrate 1 2The lattice temperature T of the same size of (metal disilicide) 3Be said temperature T 4(T 3=T 4).In addition, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for the Ni-Pt alloy film, the lattice size and the MSi of Semiconductor substrate 1 2The lattice temperature T of the same size of (metal disilicide) 3Be said temperature T 5(T 3=T 5).
Be the situation of Ni film and be that the situation of Ni-Pt alloy film is that example describes with metal film 12, but metal film 12 be Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film etc. situation too.That is, metal film 12 is Ni 1-xPt xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1- xPt xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1, metal film 12 is Ni 1-xPd xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1- xPd xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Metal film 12 is Ni 1-xYb xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1 -xYb xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Metal film 12 is Ni 1-xEr xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1- xEr xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Metal film 12 is Ni 1-xY xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1- xY xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Metal film 12 is Ni 1-xLn xAlloy film (Ln herein: in the time of lanthanide series), make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than Ni 1-xLn xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.
As mentioned above, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5 at least 2Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (that is, mismatch α is 0%) of Semiconductor substrate 1 3(T 2＜T 3).And, the 2nd heat treated heat treatment temperature T of step S5 2Under MSi 2Poor (absolute value) of the lattice size of the lattice of (metal disilicide) size and Semiconductor substrate 1 more preferably is more than 0.01% of lattice size of Semiconductor substrate 1 (being α 〉=0.01%), more than 0.02% of lattice size (being α 〉=0.02%) of further preferred semiconductor substrate 1.
MSi 2The lattice size L of (metal disilicide) M(corresponding to length L described later 2) and the lattice of Semiconductor substrate 1 size L S(corresponding to length L described later 1) difference with respect to the lattice of Semiconductor substrate 1 size L SRatio (ratio) represent that with percentage as mismatch α, this mismatch α represents with following formula.
α=[(L S-L M)/L S] * 100 (unit is %)
In the curve of above-mentioned Figure 24 and Figure 25, the temperature dependency of above-mentioned mismatch α is represented by dotted lines, under any situation in Figure 24 and Figure 25, and the L in the above-mentioned formula SAll corresponding to the lattice size of monocrystalline silicon (Si), under the situation of Figure 24, the L in the above-mentioned formula MCorresponding to NiSi 2The lattice size, under the situation of Figure 25, the L in the above-mentioned formula MCorresponding to Ni 0.98Pt 0.02Si 2The lattice size.
Under the situation of Figure 24, rise silicon metal (Si) and NiSi from room temperature with temperature 2The difference of lattice size dwindle gradually, so above-mentioned mismatch α diminishes, temperature T 4Silicon metal (Si) and NiSi when (about 590 ℃) 2Consistent (the L of lattice size S=L M), above-mentioned mismatch α is 0% (α=0%).On the other hand, under the situation of Figure 25, rise silicon metal (Si) and Ni from room temperature with temperature 0.98Pt 0.02Si 2The difference of lattice size dwindle gradually, above-mentioned mismatch α diminishes gradually, in temperature T 5(about 495 ℃) are silicon metal (Si) and Ni down 0.98Pt 0.02Si 2Consistent (the L of lattice size S=L M), above-mentioned mismatch α is 0% (α=0%).
In the 2nd heat treatment of step S5, not only do not form the lattice size and the MSi of Semiconductor substrate 1 2Lattice state of the same size, and keep the lattice size and the MSi of Semiconductor substrate 1 2The difference of lattice size be the state than big difference of a certain degree, can more positively suppress metallic element M thus and diffuse to semiconductor substrate region, and can more positively prevent MSi from the metal silicide layer 41 of MSi phase 2To groove misgrowth.Therefore, at the 2nd heat treated heat treatment temperature T of step S5 2Above-mentioned mismatch α is preferably greater than 0% (α＞0%) down, more preferably is (α 〉=0.01%) more than 0.01%, more preferably (α 〉=0.02%) more than 0.02%.So, if be that 0.01% temperature is made as temperature T with above-mentioned mismatch α 6, above-mentioned mismatch α is that 0.02% temperature is made as temperature T 7, the 2nd of step S5 the heat treated heat treatment temperature T then 2More preferably be that above-mentioned mismatch α is 0.01% temperature T 6Below (T 2≤ T 6), more preferably above-mentioned mismatch α is 0.02% temperature T 7Below (T 2≤ T 7).Thus, when the 2nd heat treatment of step S5, become the lattice size and the MSi of Semiconductor substrate 1 2The difference of lattice size be the state than big difference of a certain degree, so, can more positively suppress metallic element M and diffuse to semiconductor substrate region, and can more positively prevent MSi from the metal silicide layer 41 of MSi phase 2Misgrowth to groove.
Shown in the curve of Figure 24, Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for nickel (Ni) film, and when promptly metal silicide layer 41 be a nickel silicide (NiSi) layer, above-mentioned mismatch α was 0.01% temperature T 6Be about 575 ℃ of (T 6=575 ℃), above-mentioned mismatch α is 0.02% temperature T 7Be about 560 ℃ of (T 7=560 ℃).So Semiconductor substrate 1 is monocrystalline silicon (Si) substrate and a metal film 12 during for nickel (Ni) film, the 2nd heat treated heat treatment temperature T of step S5 2Be at least above-mentioned mismatch α and be 0% temperature T 4Below (about 590 ℃), more preferably be 0.01% temperature T for above-mentioned mismatch α 6Below, i.e. about (T below 575 ℃ 2≤ T 6=575 ℃).And, the 2nd heat treated heat treatment temperature T of step S5 2More preferably above-mentioned mismatch α is 0.02% temperature T 7Below, i.e. about (T below 560 ℃ 2≤ T 7=560 ℃).
Shown in the curve of Figure 25, Semiconductor substrate 1 is that monocrystalline silicon (Si) substrate and metal film 12 are Ni 0.98Pt 0.02During alloy film, metal silicide layer 41 is Ni 0.98Pt 0.02During the Si layer, above-mentioned mismatch α is 0.01% temperature T 6Be about 480 ℃ of (T 6=480 ℃), above-mentioned mismatch α is 0.02% temperature T 7Be about 470 ℃ of (T 7=470 ℃).So Semiconductor substrate 1 is that monocrystalline silicon (Si) substrate and metal film 12 are Ni 0.98Pt 0.02During alloy film, the 2nd heat treated heat treatment temperature T of step S5 2Be at least above-mentioned mismatch α and be 0% temperature T 5Below (about 495 ℃), more preferably be 0.01% temperature T for above-mentioned mismatch α 6Below, i.e. about (T below 480 ℃ 2≤ T 6=480 ℃).And, the 2nd heat treated heat treatment temperature T of step S5 2More preferably above-mentioned mismatch α is 0.02% temperature T 7Below, i.e. about (T below 470 ℃ 2≤ T 7=470 ℃).
Figure 26 is the curve chart of the distribution (inequality) of expression leakage current.Figure 26 represents that the step S1～S5 according to the present embodiment forms the situation (representing " the 2nd heat treatment is arranged " with white circle among Figure 26) and situation (representing " not having the 2nd heat treatment " with black circle among Figure 26) different with the present embodiment, that the 2nd heat treatment that omit step S5 forms nickel silicide layer (corresponding to metal silicide layer 41) of nickel silicide layer (corresponding to metal silicide layer 41).Need to prove that the curve of Figure 26 is at n +Form the Ni film on the type silicon area, thereby form the situation of nickel silicide layer, the 2nd heat treated heat treatment temperature T 2Be made as 550 ℃.(arbitrary unit: arbitrary unit), the longitudinal axis of the curve of Figure 26 is corresponding to probability distribution (cumulative frequency, Cumulative Frequency) corresponding to leakage current value for the transverse axis of the curve of Figure 26.
Different with the present embodiment, when omitting the 2nd heat treatment of step S5, nickel silicide layer (metal silicide layer 41) be unsettled NiSi (MSi) phase, shown in the curve of Figure 26, the possibility of leakage current increase uprises.With at p +Compare thereby form on the type silicon area when Ni film forms nickel silicide layer, at n +Thereby the increase of above-mentioned leakage current is remarkable when forming Ni film formation nickel silicide layer on the type silicon area, and by above-mentioned Figure 23 as can be known, this is because and p +The type silicon area is compared, n +The type silicon area forms the temperature height of NiSi phase, causes the NiSi layer instability that forms easily.
And as described in the present embodiment, when carrying out the 2nd heat treatment of step S5, composition in the nickel silicide layer (metal silicide layer 41) is more even, Ni (metallic element M) in the nickel silicide layer (metal silicide layer 41) and the ratio of components of Si are in stoichiometric proportion, more near 1: 1, so can stablize nickel silicide layer (metal silicide layer 41).By the 2nd heat treatment of step S5, make nickel silicide layer (metal silicide layer 41) stable, shown in the curve of Figure 26, can prevent the increase of leakage current thus.So, can prevent the characteristic variations of each MISFET, and can improve the performance of semiconductor device.
Figure 27 is the curve chart of expression according to the distribution (inequality) of the sheet resistance of the nickel silicide layer (corresponding to metal silicide layer 41) of step S1～S5 formation of the present embodiment.Need to prove that the curve of Figure 27 is at p +Form the Ni film on the type silicon area, thereby form the situation of nickel silicide layer.The transverse axis of the curve of Figure 27 is corresponding to sheet resistance value, and the longitudinal axis of the curve of Figure 27 is corresponding to probability distribution (cumulative frequency, Cumulative Frequency).The 2nd heat treated heat treatment temperature T of the curve representation step S5 of Figure 27 2Situation when being 550 ℃ (curve of representing with circle mark among Figure 27) and the situation (curve of representing with the square mark among Figure 27) when being 600 ℃.
As mentioned above, monocrystalline silicon (Si) and NiSi 2Lattice temperature T of the same size 4Be about 590 ℃ of (T 4=590 ℃).Therefore, the 2nd of the step S5 shown in the curve chart of Figure 27 the heat treated heat treatment temperature T 2The situation that is 550 ℃ is corresponding to the 2nd heat treated heat treatment temperature T that makes step S5 as described in the present embodiment 2Be lower than NiSi 2(MSi 2) lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 4(T 3) (T 2＜T 4Be T 2＜T 3) situation (make the 2nd heat treated heat treatment temperature T 2A little less than said temperature T 7Situation).And the 2nd heat treated heat treatment temperature T of the step S5 shown in the curve chart of Figure 27 2The situation that is 600 ℃ is corresponding to different the 2nd heat treated heat treatment temperature T that make step S5 with the present embodiment 2Be higher than NiSi 2(MSi 2) lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 4(T 3) (T 2＞T 4Be T 2＞T 3) situation.
By the curve of Figure 27 as can be known, with the 2nd heat treated heat treatment temperature T that makes step S5 2The situation that is 600 ℃ is compared, T 2When being 550 ℃, the sheet resistance value of nickel silicide layer uneven little.That is, with the 2nd heat treated heat treatment temperature T that makes step S5 2The situation that is 600 ℃ is compared, T 2The ratio that causes nickel silicide layer to become high resistance (high sheet resistance) when being 550 ℃ reduces.
Think that it be the reasons are as follows.That is, make the 2nd heat treated heat treatment temperature T of step S5 2When being 600 ℃, heat treatment temperature T 2Be higher than NiSi 2(MSi 2) lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 4(T 3), so, in the 2nd heat treatment of step S5, in nickel silicide layer (corresponding to metal silicide layer 41), produce high-resistance NiSi 2Part, the possibility that causes sheet resistance to uprise increases.And with the 2nd heat treated heat treatment temperature T of step S5 2When being made as 550 ℃, heat treatment temperature T 2Be lower than NiSi 2(MSi 2) lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 4(T 3), so, even carry out the 2nd heat treatment of step S5, also can suppress or prevent to generate in the nickel silicide layer (corresponding to metal silicide layer 41) high-resistance NiSi 2Part.
In the present embodiment, by making the 2nd heat treated heat treatment temperature T of step S5 2Be lower than MSi 2(NiSi 2) lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 3(T 4) (T 2＜T 3), can suppress or prevent in metal silicide layer 41, to generate MSi 2(NiSi partly 2Part).Therefore, the resistance that not only makes metal silicide layer 41 is the resistance value of low-resistance MSi phase, and can reduce the inequality of the resistance of each metal silicide layer 41.So, forming a plurality of MISFET on the Semiconductor substrate 1, when on each MISFET, forming metal silicide layer 41, can make the resistance of metal silicide layer 41 of each MISFET even, and can prevent the characteristic variations of MISFET.So, can improve the performance of semiconductor device.
As mentioned above, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (being that above-mentioned mismatch α is 0%) of Semiconductor substrate 1 3(T 2＜T 3), more preferably be that above-mentioned mismatch α is 0.01% temperature T 6Below (T 2≤ T 6), more preferably above-mentioned mismatch α is 0.02% temperature T 7Below (T 2≤ T 7).Can suppress or prevent as above-mentioned NiSi shown in Figure 22 thus 2The MSi of misgrowth zone 141c and so on 2Misgrowth, this experiment by the inventor (section of semiconductor device observe and the composition analysis of section etc.) has obtained affirmation.In addition, can suppress or prevent MSi 2The source drain of the MISFET that causes of misgrowth between the increase of leakage current or the increase of the diffusion resistance in source drain zone.In the present embodiment, by carrying out the 2nd heat treatment of step S5, can stabilization metallic silicide layer 41, so can prevent the characteristic variations (characteristic variations of each MISFET) of MISFET.Therefore, can improve the performance of semiconductor device.
In the present embodiment, under the state that has formed barrier film 13, carry out the 1st heat treatment of step S3, make reactions such as metal film 12 and area, form the metal silicide layer 41 of MSi phase, as mentioned above, barrier film 13 is preferably the film that can make Semiconductor substrate 1 produce tensile stress.Promptly, the membrane stress of barrier film 13 (stress of film self) performance compression is (when utilizing the titanium nitride film of sputtering method formation, for example be the compression about 2GPa (gigapascal (gigapascal))) effect, can make Semiconductor substrate 1 (form MISFET active region) produce tensile stress by the effect reaction.As the above-mentioned film (being barrier film 13 herein) that makes Semiconductor substrate 1 produce tensile stress, be preferably titanium nitride (TiN) film or titanium (Ti) film.
Barrier film 13 makes the direction or the big or small material that not only depends on film of the stress of Semiconductor substrate 1 generation, also depends on into embrane method.When barrier film 13 is titanium nitride (TiN) film, if utilize the plasma CVD method film forming, then barrier film 13 might become the film that makes Semiconductor substrate 1 produce compression, (the PVD method: physical vapour deposition (PVD) (Physical VaporDeposition) method) film forming, barrier film 13 can become the film that makes Semiconductor substrate 1 produce tensile stress by utilizing sputtering method.On the other hand, when barrier film 13 was titanium (Ti) film, if utilize sputtering film-forming, then barrier film 13 might become the film that makes Semiconductor substrate 1 produce compression, but by utilizing the plasma CVD method film forming, barrier film 13 can become the film that makes Semiconductor substrate 1 produce tensile stress.Therefore, when barrier film 13 is titanium nitride (TiN) film, preferably utilize sputtering method (PVD method) to form, when barrier film 13 is titanium (Ti) film, preferably utilize plasma CVD method to form.
Barrier film 13 makes the direction and the size of the stress of Semiconductor substrate 1 generation also depend on film-forming temperature.Barrier film 13 is when using titanium nitride (TiN) film of sputtering method (PVD method) formation, film-forming temperature is low more, and the tensile stress that barrier film 13 can make Semiconductor substrate 1 produce is big more, and is opposite, when film-forming temperature was too high, barrier film 13 might become the film that makes Semiconductor substrate 1 produce compression.Therefore, barrier film 13 is during for titanium nitride (TiN) film that uses sputtering method (PVD method) and form, and the film-forming temperature of barrier film 13 (underlayer temperature) is preferably below 300 ℃, the film that barrier film 13 is become make Semiconductor substrate 1 positively produce tensile stress.In addition, by cooling body is set on film formation device, can make film-forming temperature (underlayer temperature) for below the room temperature.
And barrier film 13 is when utilizing titanium (Ti) film of plasma CVD method formation, film-forming temperature is low more, and the tensile stress that barrier film 13 can make Semiconductor substrate 1 produce is big more, and is opposite, if film-forming temperature is too high, then barrier film 13 might become the film that makes Semiconductor substrate 1 produce compression.In addition, if film-forming temperature is too high, when then forming barrier film 13, metal film 12 and (formation) gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b (silicon) might overreaction.Therefore, barrier film 13 is that the film-forming temperature of barrier film 13 (underlayer temperature) is preferably below 450 ℃ when using titanium (Ti) film of plasma CVD method formation.Thus, barrier film 13 can become the film that makes Semiconductor substrate 1 positively produce tensile stress, simultaneously, can suppress or prevent metal film 12 and (formation) gate electrode 8a, 8b, n when forming barrier film 13 +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b (silicon) overreaction.
Tantalum nitride (TaN) film or tantalum (Ta) film all can become the film that makes Semiconductor substrate 1 produce tensile stress, so, can be used as barrier film 13.But when using tantalum nitride (TaN) film or tantalum (Ta) film, the wet clean process of step S4 must be used hydrofluoric acid (HF), might cause being etched to when wet-cleaned barrier film 13 and metal film 12 part in addition.Therefore,, compare with tantalum (Ta) film, more preferably use titanium nitride (TiN) film or titanium (Ti) film removed easily by the wet clean process of step S4 with tantalum nitride (TaN) film as barrier film 13.
Barrier film 13 is for being difficult to the film with metal film 12 reactions, though be preferably carry out step S3 the 1st heat treatment also not with the film of metal film 12 reactions.If by the 1st heat treatment of step S3, make barrier film 13 and metal film 12 reactions then might cause hindering the formation of metal silicide layer 41 that perhaps the composition of metal silicide layer 41 changes.In the present embodiment,, can prevent metal film 12 and barrier film 13 reactions in the 1st heat treatment of step S3, and can positively form metal silicide layer 41 by the 1st heat treatment of step S3 by making the film of barrier film 13 for being difficult to react with metal film 12.As the above-mentioned barrier film 13 that is difficult to metal film 12 reaction, preferred titanium nitride (TiN) film or titanium (Ti) film.
If the thickness of the metal silicide layer 41 that forms is blocked up, then might cause the increase of leakage current, and also unfavorable to the miniaturization of MISFET.Therefore, in the present embodiment, more preferably the thickness of metal film 12 is not blocked up.That is, in the present embodiment, the thickness of the metal film 12 that forms among the step S1 (deposition thickness, perpendicular to the thickness on the direction of Semiconductor substrate 1 interarea) is preferably below the 15nm.If metal film 12 is thin excessively, then the thickness of metal silicide layer 41 is thin excessively, and diffusion resistance increases.Therefore, the thickness of the metal film 12 that forms by step S1 (deposition thickness, perpendicular to the thickness on the direction of Semiconductor substrate 1 interarea) more preferably is 3～15nm, and more preferably 6～12nm for example can be 9nm.
At Semiconductor substrate 1 surface (gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +When the surface of N-type semiconductor N zone 10b) having the following formation of the state metal film 12 of natural oxide film, this natural oxide film has the metal film 12 of obstruction and silicon (gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The silicon of N-type semiconductor N zone 10b) effect of reaction.Therefore, on Semiconductor substrate 1 surface, exist when forming metal film 12 under the state of natural oxide film, must form thicker metal film 12, make the metallic element M of metal film 12 diffuse to silicon area (gate electrode 8a, 8b, n easily +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) in, but in the present embodiment, as mentioned above, can make metal film 12 not blocked up.So, in the present embodiment, preferably at Semiconductor substrate 1 surface (gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b) there is not the state of natural oxide film to form metal film 12 down on.Therefore, preferably carry out gate electrode 8a, 8b, the n that dry type is cleaned conductive substrate 1 interarea +N-type semiconductor N zone 9b and p +The operation (corresponding to the operation P2 of above-mentioned Figure 11) on the surface of N-type semiconductor N zone 10b, remove the natural oxide film on above-mentioned surface, then, Semiconductor substrate 1 is not placed atmosphere (atmosphere that contains aerobic), but carry out step S1 (deposition procedures of metal film 12) and step S2 (deposition procedures of barrier film 13).Can even metal film 12 is not thick, also can positively form the metal silicide layer of forming by MSi 41 not having to form metal film 12 under the state of natural oxide film thus.So, can prevent that the metal silicide layer 41 blocked up leakage currents that make from increasing.Also help the miniaturization of MISFET.
In the present embodiment, as mentioned above, between dry type clean operation (the operation P2 of above-mentioned Figure 11) and operation (the step S1 of Fig. 9 is the operation P2 of Figure 11), Semiconductor substrate 1 is implemented the product of generation when removing dry type clean (disposals) and the heat treatment (the operation P3 of Figure 11) carried out under 150～400 ℃ at depositing metallic films 12 on the interarea of Semiconductor substrate 1.Therefore, the autoregistration reaction (reaction of the M+Si → MSi that is caused by the 1st heat treatment of step S3) that is deposited on the metal film 12 on the interarea of Semiconductor substrate 1 is not hindered by above-mentioned product, but at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b evenly takes place, thereby can obtain the uneven little metal silicide layer 41 of resistance.
Because the heat treatment (the operation P3 of Figure 11) of the product that enforcement generates when removing the dry type clean between dry type clean operation (the operation P2 of above-mentioned Figure 11) and metal film 12 deposition procedures (the step S1 of Fig. 9, the operation P5 of Figure 11), so, the autoregistration reaction of metal film 12 is not hindered by above-mentioned product, even metal film 12 is not thick, also can positively form the metal silicide layer of forming by MSi 41.So, can prevent the blocked up situation that causes leakage current to increase of the thickness of metal silicide layer 41.Also help the miniaturization of MISFET.
In the present embodiment, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b, p +The surface of N-type semiconductor N zone 10b forms in the operation of metal silicide layer 41, removes by dry type clean (disposal) and remains in product on Semiconductor substrate 1 interarea by being higher than heat treatment under 150 ℃ the temperature.Therefore, (the n type polysilicon of formation gate electrode 8a, the p type polysilicon that constitutes gate electrode 8b, formation have formed n to silicon +N-type semiconductor N zone 9b, p +The monocrystalline silicon of the Semiconductor substrate 1 of N-type semiconductor N zone 10b) and the autoregistration of metal film 12 reaction be not generated thing and hinder, react equably, and then can obtain the little metal silicide layer 41 of resistance inequality.
In the present embodiment, to the manufacturing end (for example, by cutting etc. Semiconductor substrate 1 being formed the independently stage of semiconductor chip) of semiconductor device, metal silicide layer 41 all is MSi (metal list silicide) phase.This is because the semiconductor device of making is lower than MSi by making metal silicide layer 41 for resistivity 2Reach M mutually 2The MSi phase of Si phase makes metal silicide layer 41 be low resistance, and can reduce the diffusion resistance of contact resistance, source drain, thereby improves the performance of the semiconductor device that has formed MISFET.Therefore, as the 1st condition, be lower than MSi if the present embodiment is applicable to by resistivity 2(metal disilicide) reaches M mutually 2The metal silicide of MSi (metal list silicide) phase of Si (two metal silicides) phase and so on forms the situation of metal silicide layer 41, and then effect is obvious.
Because the present embodiment can or prevent MSi in inhibition 2The excrescent while, form MSi phase metal silicide layer 41, so as the 2nd condition, if be applicable to by there being MSi 2The silicide of (metal disilicide) phase forms the situation of metal silicide layer 41, and then effect is obvious.
The present embodiment can be in preventing heat treatment step the diffusion (moving) of metallic element M unnecessary (surplus), thereby suppress or prevent MSi 2The excrescent while, form the metal silicide layer 41 of MSi phase, so, as the 3rd condition,, be not the situation that Si (silicon) but metallic element M become diffusion kind if the present embodiment is applicable to when forming metal silicide layer, then effect is obvious.
If consider above-mentioned the 1st～the 3rd condition, when then metal film 12 is Ni film or Ni alloy film, particularly when Ni (nickel) film, Ni-Pt (nickel-platinum) alloy film, Ni-Pd (nickel-palladium) alloy film, Ni-Y (nickel-yttrium) alloy film, Ni-Yb (nickel-ytterbium) alloy film, Ni-Er (nickel-erbium) alloy film or Ni-lanthanide series alloy film, if be suitable for the present embodiment, then effect is obvious.If metal film 12 is Ni film, Ni-Pt alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film, when then forming metal silicide layer, not that Si (silicon) but metallic element M become diffusion kind, have MSi 2Phase, and the resistivity of MSi phase is lower than MSi 2Reach M mutually 2The Si phase.But, when metal film 12 was in Ni film, Ni-Pt alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or the Ni-lanthanide series alloy film any one, MSi all took place 2From the excrescent problem of metal silicide course groove, metal silicide layer owing to form MSi 2When part caused the uneven problem, particularly metal film 12 that increases of resistance to be Ni (nickel) film, the problems referred to above were the most remarkable.Therefore, if be suitable for the present embodiment when metal film 12 is Ni (nickel) film, then effect is the most obvious.This for following embodiment too.
MISFET compares with the p channel-type, forms as above-mentioned NiSi shown in Figure 22 at n channel-type MISFET easily 2(nickel disilicide) from NiSi layer 141b to the misgrowth of groove zone 141c.By above-mentioned Figure 23 as can be known, compare with n type silicon area, p type silicon area carries out the reaction of Ni and Si under lower temperature, compares with n type silicon area, and p type silicon area spreads Ni easily.Therefore, compare with n type trap 6, the p type trap 5 that spreads easily at Ni is easy to generate NiSi 2Misgrowth zone 141c.Therefore, MISFETQp compares with the p channel-type, in n channel-type MISFETQn, can prevent MSi when being suitable for the present embodiment 2More obvious from metal silicide layer 41 to the excrescent effect of groove.This for following embodiment too.
As explanation with reference to above-mentioned Figure 27 carried out, with by on n type silicon area, forming the Ni film and heat-treating, form nickel silicide layer and compare, by on p type silicon area, forming the Ni film and heat-treating, when forming nickel silicide layer, the sheet resistance of nickel silicide layer is uneven easily.Think that this also is that p type zone is diffusion Ni easily, promotes the reaction of Ni and Si easily owing to compare with n type zone, so form high-resistance NiSi in the nickel silicide layer of the NiSi phase that forms easily 2Part.Therefore, MISFETQn compares with the n channel-type, and in p channel-type MISFETQp, the effect of the resistance inequality that can reduce metal silicide layer 41 when being suitable for the present embodiment is more obvious.This for following embodiment too.
The present embodiment in source electrode or drain electrode with semiconductor regions (9b, 10b) the last situation that forms metal silicide layer 41 of last and gate electrode (8a, 8b) is illustrated, but as other schemes, also can be not form metal silicide layer 41 on gate electrode 8a, 8b, (be n at source electrode or drain electrode with semiconductor regions herein +N-type semiconductor N zone 9b, p +N-type semiconductor N zone 10b) goes up the scheme that forms metal silicide layer 41.This for following embodiment too.
In the present embodiment, as preferred plan, to (referring to n here with semiconductor regions in the source electrode or the drain electrode that are formed on the Semiconductor substrate 1 +N-type semiconductor N zone 9b, p +N-type semiconductor N zone 10b) going up the scheme that forms metal silicide layer 41 is illustrated, but as other schemes, can also be to use on the semiconductor regions in addition, utilize the method identical to form the scheme of metal silicide layer 41 with the present embodiment in the source electrode or the drain electrode that are formed on the Semiconductor substrate 1.In such cases, by using described metal silicide layer 41 forming methods of the present embodiment, can prevent from the metal silicide layer that forms, to form MSi 2Part, thereby the effect of the resistance inequality of the metal silicide layer that can be reduced.But, as described in the present embodiment, if (refer to n here with semiconductor regions in the source electrode or the drain electrode that are formed on the Semiconductor substrate 1 +N-type semiconductor N zone 9b, p +N-type semiconductor N zone 10b) goes up formation metal silicide layer 41, then prevent from metal silicide layer 41, to form MSi owing to not only having 2Part, thereby the effect of the resistance inequality of reduction metal silicide layer 41, and can be prevented MSi 2To the excrescent effect of channel region, so effect is extremely remarkable.
In the present embodiment, the metallic element M (for example Ni) that constitutes metal film 12 diffuses to source electrode or drains and (refers to n here with semiconductor regions +N-type semiconductor N zone 9b, p +N-type semiconductor N zone 10b), form the metal silicide layer of forming by MSi 41.Therefore, Semiconductor substrate 1 preferably is made of siliceous (Si) material, for example can be by silicon, polysilicon, amorphous silicon, the SiGe (Si of monocrystalline silicon, impurity xGe 1-x, 0＜x＜1 herein) or carbon doped silicon (carbon doped silicon) (Si xC 1-x, 0.5＜x＜1 herein) etc. formation, most preferably be monocrystalline silicon.In addition, also can use SOI (silicon-on-insulator (Silicon On Insulator)) substrate and so on dielectric substrate, to form the substrate of siliceous (Si) material layer as Semiconductor substrate 1.This for following embodiment too.
If the time spent of doing that makes Semiconductor substrate 1 (be the active region with element separated region 4 regulations, be formed with the active region of MISFET) produce compression in 4 performances of element separated region is suitable for the present embodiment, then effect is obvious.This for following embodiment too.It is the reasons are as follows.
If element separated region 4 makes Semiconductor substrate 1 produce compression, then this compression has the lattice size of dwindling Semiconductor substrate 1 (active region), makes it near MSi 2The effect of lattice size.Therefore, heat-treat, then cause under the effect of lattice size in this compression of Semiconductor substrate 1, diminishing and near MSi if make Semiconductor substrate 1 produce under the state of compression at element separated region 4 2The state of lattice size under heat-treat, metallic element M spreads (moving) easily in the heat treatment thereby make, so MSi takes place easily 2From the misgrowth of metal silicide layer 41 to groove.
And in the present embodiment, it is barrier film 13 that the film that makes Semiconductor substrate 1 produce tensile stress is set on metal film 12, carries out the 1st heat treatment of step S3 under this state, makes metal film 12 and silicon area ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) reaction, the metal silicide layer 41 of formation MSi phase.Therefore, barrier film 13 has the effect of compression (element separated region 4 acts on the compression of the active region that is formed with MISFET) of element separated region 4 of resulting from of offsetting.The tensile stress of barrier film 13 can suppress or prevent to result from that the compression of element separated region 4 dwindles the effect of the lattice size of Semiconductor substrate 1, so can suppress or prevent MSi when the 1st heat treatment of step S3 2From the misgrowth of metal silicide layer 41 to groove.
And then, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5 2Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (being that above-mentioned mismatch α is 0%) of Semiconductor substrate 1 3(T 2＜T 3), more preferably be that above-mentioned mismatch α is 0.01% temperature T 6Below (T 2≤ T 6), more preferably above-mentioned mismatch α is 0.02% temperature T 7Below (T 2≤ T 7).Therefore, even result from the effect that the compression of element separated region 4 has the lattice size of dwindling Semiconductor substrate 1 (active region), also can be by the 2nd heat treated heat treatment temperature T with step S5 2Be controlled at said temperature, suppress or prevent MSi in the 2nd heat treatment of step S5 2(metal disilicide) from metal silicide layer 41 to groove misgrowth.
Under the situation of the present embodiment, the situation that forms element separated region 4 by the ditch 4a inside that is formed at Semiconductor substrate 1 with insulating material (dielectric film 4b, 4c) landfill promptly utilizes the STI method to form the situation of element separated region 4, compare with the situation of utilizing LOCOS method formation element to separate, the compression that acts on the active region between the element separated region 4 becomes big.This is owing to be formed at the active region of action of compressive stress between element separated region 4 that the sidewall extruding active region side of the ditch 4a on the Semiconductor substrate 1 produces.Particularly when the element separated region 4 usefulness insulating materials of landfill ditch 4a inside (being dielectric film 4c here) are dielectric film (for example silicon oxide film) by plasma CVD method (particularly HDP-CVD method) film forming, with O 3-TEOS oxide-film (dielectric film that utilizes the hot CVD method to form) etc. is compared, and the contraction during sintering is little, and the compression that element separated region 4 acts on the active region that forms MISFET becomes big.As mentioned above, be suitable for the present embodiment if act on the compression of the active region that forms MISFET at element separated region 4 when big, then effect is obvious, and this for following embodiment too.
When using CBED (convergent beam electron diffraction) method to measure, the compression that the element separated region 4 that utilizes the STI method to form acts on Semiconductor substrate 1 (zone near element separated region 4 in the active region) is for about-0.035GPa.Therefore, barrier film 13 makes tensile stress that Semiconductor substrate 1 produces more preferably for more than the 0.035GPa (gigapascal), thus, can positively prevent when the 1st heat treatment of step S3, results from the influence (MSi of compression of element separated region 4 2Misgrowth etc.).In addition, barrier film 13 makes tensile stress that Semiconductor substrate 1 produces more preferably below the 2.5GPa (gigapascal), barrier film 13 easy film forming.So the tensile stress that barrier film 13 produces Semiconductor substrate 1 more preferably is about 0.035～2.5GPa (gigapascal).Barrier film 13 makes the above-mentioned numerical value of the tensile stress that Semiconductor substrate 1 produces, and (above-mentioned 0.035～2.5GPa) is the value that is calculated by the amount of warpage (amount of warpage under the room temperature) that goes up Semiconductor substrate 1 when forming barrier film 13 and barrier film 13 integral body whole of a side interarea of Semiconductor substrate 1 monomer (not forming the Semiconductor substrate that gate electrode and impurity diffusion layer and so on constitute the state of thing).Need to prove,, when Semiconductor substrate 1 is the convex warpage up, on Semiconductor substrate 1, produce tensile stress making under the state that faces up that forms barrier film 13.
When being embedded in element and separating insulator with ditch 4a inside and mainly use plasma CVD method (particularly HDP-CVD method) to form (when utilizing plasma CVD method (particularly HDP-CVD method) formation dielectric film 4c), becoming mem stage to form fine and close film, shrink little when after film forming, carrying out sintering.Therefore, the compression that element separated region 4 acts on the Semiconductor substrate 1 (with the active region of element separated region 4 regulations) becomes big, and this compression is easy to generate influence when forming metal silicide layer.Even the compression that element separated region 4 acts on the Semiconductor substrate 1 becomes big, the present embodiment also can prevent to produce harmful effect (MSi for example when forming metal silicide layer 41 2Misgrowth).Therefore, if be embedded in the insulator (insulator of composed component separated region 4 of element separation with ditch 4a inside, be dielectric film 4b, 4c herein) be suitable for the present embodiment when constituting by the main dielectric film that forms by plasma CVD method (particularly HDP-CVD method) (being dielectric film 4c herein), then this effect is extremely obvious.This for following embodiment too.
Next, MSi is described 2The misgrowth of (metal disilicide) and the relation of crystalline texture.
When Semiconductor substrate 1 was silicon (monocrystalline silicon), the crystalline texture of silicon was diamond lattic structure, and crystallographic system is a cubic system, and space group is Fd3m (227), the single crystal lattice length of this crystalline texture corresponding to lattice constant, be the lattice size.
Figure 28 is that the crystalline texture of expression silicon (Si) is the key diagram (perspective view) of diamond lattic structure.Cube shown in Figure 28 is the monocrystalline of silicon (Si), and this cube is the length L of (single crystal lattice) on one side 1For the lattice constant of silicon (Si), be the lattice size of silicon (Si).So, this length L 1Corresponding to the above-mentioned L when Semiconductor substrate 1 is silicon (monocrystalline silicon) S(L 1=L S).Among Figure 28, at the position configuration Si atom of configuration ball.
On the other hand, MSi 2(metal disilicide) is NiSi 2When (nickel disilicide), NiSi 2The crystalline texture of (nickel disilicide) is fluorite structure (CaF 2The type structure), crystallographic system is a cubic system, and space group is Fm3m (225), and the single crystal lattice length of this crystalline texture is the lattice size corresponding to lattice constant.
Figure 29 is expression NiSi 2The crystalline texture of (nickel disilicide) is the key diagram (perspective view) of fluorite structure.Cube shown in Figure 29 is NiSi 2The monocrystalline of (nickel disilicide), the length L on this cubical one side (single crystal lattice) 2Be NiSi 2The lattice constant of (nickel disilicide), be NiSi 2The lattice size of (nickel disilicide).So, this length L 2Corresponding at above-mentioned MSi 2Be NiSi 2The time above-mentioned L M(L 2=L M).Among Figure 29, at the position configuration Ni atom or the Si atom of configuration ball.
Fluorite structure shown in Figure 29 is to have AB 2The structure of the compound of the composition of (A, B are respectively different elements), NiSi 2Corresponding to above-mentioned AB 2The compound of middle A=Ni, B=Si.This fluorite structure is by A element (NiSi 2Situation under be Ni) face-centred cubic structure (structure of Figure 30 (a)) and B element (NiSi 2Situation under for Si) the constituting of simple cubic structure (structure of Figure 30 (b)).
(a) expression of Figure 30 has AB 2A element (NiSi in the fluorite structure of forming 2Situation under be Ni) crystalline texture, (b) of Figure 30 is that expression has an AB 2B element (NiSi in the fluorite structure of forming 2Situation under be Si) the key diagram (perspective view) of crystalline texture.
In the cube shown in Figure 30 (a), at the position configuration Ni of ball element.That is, Figure 30 (a) is the face-centred cubic structure at the center configuration Ni element of cubical each summit and each face of cube.The length and the above-mentioned L on one side (single crystal lattice) of the face-centred cubic structure of Figure 30 (a) 2Identical, with NiSi 2The lattice constant of (nickel disilicide) is NiSi 2The lattice size of (nickel disilicide) is identical.
In the cube shown in Figure 30 (b), at the position configuration Si of ball element.That is, Figure 30 (b) is the simple cubic structure at cubical each apex configuration Si element.The length L on one side (single crystal lattice) of the simple cubic structure of Figure 30 (b) 3Be above-mentioned length L 2Half, have L 2=2L 3Relation.
The structure (face-centred cubic structure) of combination Figure 30 (a) and the structure (simple cubic structure) of Figure 30 (b) make center of gravity unanimity separately, constitute the fluorite structure of Figure 29.
Constitute the lattice size and the NiSi of the single crystalline Si (silicon) of Semiconductor substrate 1 2The lattice state of the same size of (nickel disilicide) is above-mentioned length L corresponding to the lattice constant of silicon (Si) 1And NiSi 2The lattice constant of (nickel disilicide) is above-mentioned length L 2Equate (to be L 1=L 2) state.In addition, constitute the lattice size and the NiSi of the monocrystalline silicon (Si) of Semiconductor substrate 1 2The lattice of (nickel disilicide) said temperature T of the same size 4Lattice constant corresponding to silicon (Si) is above-mentioned length L 1And NiSi 2The lattice constant of (nickel disilicide) is above-mentioned length L 2Consistent (equating, i.e. L 1=L 2) temperature.
The fluorite structure similitude height of the diamond lattic structure of Figure 28 and Figure 29.Promptly, in the fluorite structure of Figure 29, if the site at the Ni of face-centred cubic structure does not dispose Ni, and configuration Si, and 4 sites in 8 Si sites of simple cubic structure (4 sites representing with symbol 61 among Figure 30 (b)) configuration Si, do not dispose Si in 4 sites of residue (4 sites representing with symbol 62 among Figure 30 (b)), then become the structure identical with the diamond lattic structure of Figure 28.
The configuration of Si and the NiSi of Figure 29 in the diamond lattic structure of the silicon of observation Figure 28 2Fluorite structure in the configuration of Si, in the diamond lattic structure of the silicon of Figure 28, be positioned at that { 400}, { 200}, { distance between 2 Si atoms of [110] direction of 100} face is (1/2) 0.5* L 1And at NiSi 2Fluorite structure in, the distance of each face diagonal of the simple cubic structure of the Si of Figure 30 (b) (i.e. the interatomic distance of Si of [110] direction) is (2) 0.5* L 3=(1/2) 0.5* L 2L 1=L 2The time, both unanimities (equating).
By heat-treating Si and Ni counterdiffusion mutually.If the 2nd heat treatment temperature T of step S5 2Lattice size and NiSi near the monocrystalline silicon (Si) that constitutes Semiconductor substrate 1 2Lattice said temperature T of the same size 4, then when the 2nd heat treatment of step S5, the high similarity of diamond lattic structure and fluorite structure has and NiSi the Si of diamond lattic structure 2Fluorite structure in the identical configuration of Si (particularly { Si of 400} face).Therefore, by the 2nd heat treatment of step S5, replace easily between the lattice of Ni and Si, and then generate NiSi easily 2Part.
So, the crystalline texture of Semiconductor substrate 1 and MSi 2When the similitude of the crystalline texture of (metal disilicide) was high, particularly the crystalline texture of Semiconductor substrate 1 was diamond lattic structure, MSi 2When the crystalline texture of (metal disilicide) was fluorite structure, aforesaid MSi significantly took place 2From the excrescent problem of metal silicide course groove or metal silicide layer, form MSi 2Part causes the uneven problem that increases of resistance.
Therefore, if at the crystalline texture and the MSi of Semiconductor substrate 1 2When the similitude of the crystalline texture of (metal disilicide) was high, particularly the crystalline texture in Semiconductor substrate 1 was diamond lattic structure, MSi 2When the crystalline texture of (metal disilicide) is fluorite structure, be suitable for the present embodiment, then effect is remarkable.So Semiconductor substrate 1 is most preferably used monocrystalline silicon, but so long as the material that has the crystalline texture of diamond lattic structure type in the same manner with monocrystalline silicon, even the material beyond the monocrystalline silicon also goes for Semiconductor substrate 1.This is also identical for following embodiment.
If use the Ni film as metal film 12, the above-mentioned MSi that then can form 2NiSi for fluorite structure 2So the effect that is suitable for the present embodiment is remarkable, but in metal film 12, use Ni film MSi in addition, that can form 2During for the metal or alloy of the crystalline texture of fluorite structure type, the present embodiment also is effective.For example, when metal film 12 is nickel alloy film, particularly Ni-Pt (nickel-platinum) alloy film, Ni-Pd (nickel-palladium) alloy film, Ni-Y (nickel-yttrium) alloy film, Ni-Yb (nickel-ytterbium) alloy film, Ni-Er (nickel-erbium) alloy film or Ni-lanthanide series alloy film, the MSi of formation 2Can become fluorite structure (wherein, other metals that the part in the Ni site of the face-centred cubic structure of Figure 30 (a) is configured alloy replace), so preferably be suitable for the present embodiment.This for following embodiment too.
(embodiment 2)
Figure 31 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment, corresponding to Fig. 9 of above-mentioned embodiment 1.After Figure 31 represents to obtain the structure of above-mentioned Fig. 7, utilize the self-aligned silicide treatment process at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Form the manufacturing process flow of the operation of metal silicide layer (metal semiconductor conversion zone) on the surface of N-type semiconductor N zone 10b.Figure 32～Figure 35 is the major part profile in the manufacturing process of semiconductor device of the present embodiment.
In the semiconductor device manufacturing process of the present embodiment until identical with above-mentioned embodiment 1 by in above-mentioned steps S4, carrying out operation that wet clean process removes barrier film 13 and unreacted metal film 12, so omit explanation here, and the operation after the above-mentioned steps S4 described.
Proceed to above-mentioned steps S4 in the same manner with above-mentioned embodiment 1, after obtaining the structure of Figure 32 suitable substantially with above-mentioned Figure 14, as shown in figure 33, on the interarea (whole face) of Semiconductor substrate 1, comprise on the metal silicide layer 41, form (deposition) barrier film (the 2nd barrier film, Stress Control film, block film) 13a (the step S11 of Figure 31).
Next, carry out the 2nd heat treatment of the step S5 identical with above-mentioned embodiment 1.In the present embodiment, the 2nd heat treatment of step S5 is carried out under the state that forms barrier film 13a, and the 2nd heat treated conditioned disjunction effect of step S5 is identical with above-mentioned embodiment 1.
Therefore, identical with above-mentioned embodiment 1, in the present embodiment, the 2nd heat treatment of step S5 neither be in order to make metal silicide layer 41 undergoing phase transition (from M 2Si is mutually to the phase change of MSi phase) carry out, but the stabilizing annealing that carries out for stabilization metallic silicide layer 41.The 2nd heat treated heat treatment temperature T of the step S5 of the present embodiment 2The 2nd heat treated heat treatment temperature T with step S5 in the above-mentioned embodiment 1 2Identical, omit its explanation here.In addition, the atmosphere during the 2nd heat treatment of the step S5 of the present embodiment is also identical with above-mentioned embodiment 1.Identical with above-mentioned embodiment 1, in the present embodiment, also from finishing (for example cut off Semiconductor substrate 1 and make independently semiconductor chip) to the semiconductor device manufacturing after the 2nd heat treatment of step S5, Semiconductor substrate 1 do not reached to be higher than the temperature of the 2nd heat treated heat treatment temperature of step S5.
After the 2nd heat treatment of step S5,, as shown in figure 34, remove barrier film 13a (the step S12 of Figure 31) by carrying out wet clean process etc.At this moment, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p + Kish silicide layer 41 on the surface of N-type semiconductor N zone 10b.Can carry out the wet clean process of step S12 by the wet-cleaned of having used sulfuric acid or the wet-cleaned of having used sulfuric acid and aqueous hydrogen peroxide solution etc.
The later operation of clean is identical with above-mentioned embodiment 1.Promptly, as shown in figure 35, be identically formed dielectric film 42 and dielectric film 43 with above-mentioned embodiment 1, on dielectric film 43,42, form contact hole 44, in contact hole 44, form embolism 45, on the dielectric film 43 of having imbedded embolism 45, form and stop dielectric film 51 and dielectric film 52, formation wiring trench 53, landfill insulated conductor film 54 and copper film formation wiring 55 in wiring trench 53.
Barrier film 13a is identical with barrier film 13, is to make Semiconductor substrate 1 produce the film of tensile stress.Therefore, can use the film identical, can preferably use titanium nitride (TiN) film or titanium (Ti) film as barrier film 13a with barrier film 13.In the present embodiment, the compression that produces for the active region of offsetting 4 pairs of Semiconductor substrate 1 of element separated region, formation makes Semiconductor substrate 1 produce the barrier film 13a of tensile stress, so barrier film 13a can be considered as Stress Control film (film of the stress of the active region of control Semiconductor substrate 1).
As the explanation of in the above-mentioned embodiment 1 barrier film 13 being carried out, the direction of the stress that Semiconductor substrate 1 produces and size not only depend on the material of film, also depend on into embrane method, so according to the reason identical with barrier film 13, when barrier film 13a is titanium nitride (TiN) film, the preferred sputtering method (PVD method) that uses forms, and when barrier film 13a is titanium (Ti) film, preferably utilizes plasma CVD method to form.According to the reason identical with barrier film 13, when barrier film 13a is titanium nitride (TiN) film that has used sputtering method (PVD method) formation, the film-forming temperature of barrier film 13a (underlayer temperature) is preferably below 300 ℃, when barrier film 13a was titanium (Ti) film that has used plasma CVD method formation, the film-forming temperature of barrier film 13a (underlayer temperature) was preferably below 450 ℃.
Tantalum nitride (TaN) film or tantalum (Ta) film also are the films that can make Semiconductor substrate 1 generation tensile stress, so can be used as barrier film 13a.But, when using tantalum nitride (TaN) film or tantalum (Ta) film, during the wet clean process of step S12, must use hydrofluoric acid (HF), might when wet-cleaned, be etched to barrier film 13a part in addition.So, compare with tantalum nitride (TaN) film or tantalum (Ta) film, more preferably use titanium nitride (TiN) film removed easily by the wet clean process of step S12 or titanium (Ti) film as barrier film 13a.The preferable range of the tensile stress of barrier film 13a is also identical with barrier film 13.
Identical with barrier film 13, barrier film 13a is not for seeing through the film of (being difficult to see through) oxygen (O) yet.That is, barrier film 13a is the film of no oxygen permeability.Because barrier film 13a prevents block (O) and sees through, so can prevent to supply with oxygen (O) to metal silicide layer 41 when the 2nd heat treatment of step S5.Can suppress thus or prevent to result from the defective of oxygen, suppress or prevent metallic element M to be spread, thereby can more positively suppress or prevent MSi when the 2nd heat treatment of step S5 by resulting from the defective of oxygen 2From the misgrowth of metal silicide layer 41 to groove.As the above-mentioned barrier film 13a that does not see through oxygen (O), preferred titanium nitride (TiN) film or titanium (Ti) film.
Barrier film 13a is difficult to the film that reacts with metal silicide layer 41, even carry out the 2nd heat treatment of step S5, also with metal silicide layer 41 reactions.If the 2nd heat treatment by step S5 makes barrier film 13a and metal silicide layer 41 reactions, then might cause the composition of metal silicide layer 41 to change, in the present embodiment, by making barrier film 13a is the film that is difficult to metal silicide layer 41 reaction, can prevent that metal silicide layer 41 and barrier film 13a react in the 2nd heat treatment of step S5, thereby can positively form metal silicide layer 41.As the above-mentioned barrier film 13a that reacts with metal silicide layer 41 of being difficult to, preferred titanium nitride (TiN) film or titanium (Ti) film.
In above-mentioned embodiment 1, by the 2nd heat treated heat treatment temperature T of controlled step S5 2, suppress or prevented MSi in the 2nd heat treatment of step S5 2(metal disilicide) from metal silicide layer 41 to groove misgrowth.But,, then preferably reduce MSi as far as possible if consider the more high performance and the high reliabilityization of semiconductor device 2From the misgrowth of metal silicide layer 41 to groove.Therefore, in the present embodiment, after removing barrier film 13 and metal film 12 and exposing the surface of metal silicide layer 41, as step S11, on the interarea (whole face) of Semiconductor substrate 1, comprise on the metal silicide layer 41, form barrier film 13a, under the state that covers metal silicide layer 41 with barrier film 13a, carry out the 2nd heat treatment of step S5 then.This barrier film 13a is identical with barrier film 13, is to make Semiconductor substrate 1 produce the film of tensile stress.
In the present embodiment by under the state that has formed the barrier film 13a that makes Semiconductor substrate 1 produce tensile stress, carrying out the 2nd heat treatment of step S5, compare during with non-isolating film 13a, the tensile stress that barrier film 13a is produced can make the lattice size of Semiconductor substrate 1 become big, makes the lattice size and the MSi of Semiconductor substrate 1 2The difference of lattice size become big, and then can positively prevent the Anomalous Diffusion of metallic element M.Can more positively prevent MSi in the 2nd heat treatment of step S5 thus 2From metal silicide layer 41 to groove misgrowth.
In the present embodiment not only with the 2nd heat treated heat treatment temperature T of step S5 2Be controlled at the temperature of explanation in the above-mentioned embodiment 1, and carry out the 2nd heat treatment of step S5 under the state that has formed the barrier film 13a that makes Semiconductor substrate 1 produce tensile stress, so barrier film 13a has the effect of compression of element separated region 4 of resulting from of offsetting.Can the tensile stress by barrier film 13a suppress or prevent to result from the effect of the lattice size that reduces Semiconductor substrate 1 that the compression of element separated region 4 has, even, also can more positively prevent MSi when the 2nd heat treatment of step S5 so 4 performances of element separated region make Semiconductor substrate 1 (active region) produce the effect of compression 2From metal silicide layer 41 to groove misgrowth.
Therefore, except obtaining the effect of above-mentioned embodiment 1, can also more positively prevent MSi in the 2nd heat treatment of step S5 in the present embodiment 2From metal silicide layer 41 to groove misgrowth.In addition, more positively prevent to produce in the metal silicide layer 41 high-resistance NiSi 2Part, and then can more positively reduce the resistance inequality of metal silicide layer 41.So, can further improve the Performance And Reliability of semiconductor device.
(embodiment 3)
The inventor further studies the operation of the comparative example of above-mentioned Figure 18～Figure 21, discovery is compared with n channel-type MISFET, the problem of junction leakage increase and junction leakage inequality (variation of each transistorized junction leakage) takes place because of forming nickel silicide layer 141b in the source drain of p channel-type MISFET easily.
In order to reduce above-mentioned junction leakage, reduce to be deposited on the thickness of the Ni film 112 on the Semiconductor substrate 1, thereby the thickness that reduces nickel silicide layer 141b is effective.But nickel silicide layer 141b is provided with for low resistanceization.Therefore, if make the thickness attenuation of the nickel silicide layer 141b of n channel-type MISFET and p channel-type MISFET, even then be difficult for influencing the n channel-type MISFET of junction leakage, the low resistance effect that also can cause nickel silicide layer 141b to bring reduces.
So, in the present embodiment, solve the problems referred to above by utilizing following operation to form metal silicide layer.
Figure 36 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment, corresponding to Fig. 9 of above-mentioned embodiment 1.Figure 36 is illustrated in after the structure that obtains above-mentioned Fig. 7, utilizes the self-aligned silicide treatment process at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b forms the manufacturing process flow of the operation of metal silicide layer (metal semiconductor conversion zone).Figure 37 and Figure 38 are the major part profiles in the semiconductor device manufacturing process of the present embodiment, corresponding to above-mentioned Figure 14.
The semiconductor device manufacturing process of the present embodiment is promptly identical with above-mentioned embodiment 1 until the operation that forms metal film 12 and barrier film 13 by above-mentioned steps S1, S2 before the 1st heat treatment step of above-mentioned steps S3, so, omit its explanation herein, the 1st heat treatment step of the step S3a that is equivalent to above-mentioned steps S3 and later operation thereof are described.
Proceed to the operation (to the operation P8 of Figure 11) of above-mentioned steps S1, S2 in the same manner with above-mentioned embodiment 1, obtain (promptly forming metal film 12 and barrier film 13 backs) after the structure of above-mentioned Fig. 8, Semiconductor substrate 1 is implemented the 1st heat treatment (annealing in process) (the step S3a of Figure 36).Same with the 1st heat treatment phase of above-mentioned steps S3, the 1st heat treatment of step S3a preferably is being full of inert gas (for example argon (Ar) gas or helium (He) gas) or nitrogen (N 2) in the environment of atmosphere, under normal pressure, carry out.
By the 1st heat treatment of step S3a, as shown in figure 37, make the polysilicon film that constitutes gate electrode 8a, 8b and metal film 12, and constitute n +N-type semiconductor N zone 9b and p +The monocrystalline silicon (single crystalline Si) and metal film 12 selective reactions of N-type semiconductor N zone 10b, forming the metal semiconductor conversion zone is metal silicide layer 41a.By making gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Each top (upper layer part) of N-type semiconductor N zone 10b and metal film 12 reactions form metal silicide layer 41a, so, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Each surface (upper layer part) of N-type semiconductor N zone 10b forms metal silicide layer 41a.
In the present embodiment 3, the 1st heat treatment of step S3a makes the metallic element M that constitutes metal film 12 and is constituting p +The reactivity of the metal film 12 the when Si of N-type semiconductor N zone 10b reacts is lower than the metallic element M that constitutes metal film 12 and constitutes n +The temperature range of the reactivity of the metal film 12 the when Si of N-type semiconductor N zone 9b reacts is carried out.
That is, the 1st heat treatment stages at step S3a constitutes the metallic element M of metal film 12 and constitutes n +In the reaction of the Si of N-type semiconductor N zone 9b, M all consumes with metallic element, at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) form metal silicide layer 41a, or metallic element M is not all consumed, and at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) the metallic element M of remained unreacted forms metal silicide layer 41a.And constitute the metallic element M of metal film 12 and constitute p at the 1st heat treatment stages of step S3a +In the reaction of the Si of N-type semiconductor N zone 10b, not with metallic element M full consumption, at p +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) the metallic element M of remained unreacted forms metal silicide layer 41a.Herein, as mentioned above, make the metallic element M that constitutes metal film 12 and constituting p +The reactivity of the metal film 12 the when Si of N-type semiconductor N zone 10b reacts is lower than to be made the metallic element M that constitutes metal film 12 and constitutes n +The temperature range of the reactivity of the metal film 12 the when Si of N-type semiconductor N zone 9b reacts is carried out the 1st heat treatment.Thus at the n in the 1st heat treated stage of having carried out step S3a +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) the metal silicide layer 41a of formation the 1st thickness is at the p in the 1st heat treated stage of having carried out step S3a +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) forms metal silicide layer 41a than the 2nd thickness of above-mentioned the 1st thin thickness.
And then in the present embodiment, two metal silicides that the 1st heat treatment by step S3a forms by the metallic element M that constitutes metal film 12 (are M 2Si) the metal silicide layer 41a of Gou Chenging.
That is, by the 1st heat treatment of step S3a, make the Si reaction of metallic element M that constitutes metal film 12 and the polysilicon film that constitutes gate electrode 8a, 8b, (upper layer part of gate electrode 8a, 8b) forms by M on the surface of gate electrode 8a, 8b 2The metal silicide layer 41a that Si forms.In addition, by the 1st heat treatment of step S3a, make the metallic element M and the n that constitute metal film 12 +The Si reaction of N-type semiconductor N zone 9b is at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) forms by M 2The metal silicide layer 41a that Si forms.By the 1st heat treatment of step S3a, make the metallic element M and the p that constitute metal film 12 +The Si reaction of N-type semiconductor N zone 10b is at p +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) forms by M 2The metal silicide layer 41a that Si forms.
Barrier film 13 is the films that are difficult to metal film 12 reaction, also is difficult to film with metal film 12 reactions even preferably carry out the 1st heat treatment of step S3a.If the 1st heat treatment of step S3a causes barrier film 13 and metal film 12 reactions, then might suppress the formation of metal silicide layer 41a, perhaps cause the composition of metal silicide layer 41a to change.Identical with above-mentioned embodiment 1, in the present embodiment, also can be difficult to film with metal film 12 reaction as barrier film 13 by use, the 1st heat treatment that prevents step S3a causes metal film 12 and barrier film 13 reactions, thereby can utilize the 1st heat treatment of step S3a positively to form metal silicide layer 41a.As the above-mentioned barrier film 13 that is difficult to metal film 12 reaction, preferred titanium nitride (TiN) film or titanium (Ti) film.
For example, when metal film 12 is the Ni film, the 1st heat treated temperature of step S3a for example more than 260 ℃, the temperature range that is lower than 320 ℃ is suitable (certainly, because of other condition differences, also may not be limited to this temperature range).In addition, be 270～310 ℃ temperature range of central value most preferably with 290 ℃.The 1st heat treated heat treatment temperature with the step S3a in the present embodiment 3 when below using Figure 39～Figure 41 to describe metal film 12 as the Ni film in detail is set in more than 260 ℃, be lower than 320 ℃ reason.
On Semiconductor substrate, form p +Type silicon area and n +The type silicon area forms Ni film about 10nm and the TiN film about 15nm thereon, makes Ni film and p by heat treatment then +Type silicon area or make Ni film and n +The reaction of type silicon area forms nickel silicide layer, removes unreacted Ni and TiN film, and Figure 39 is the expression dependent curve chart of heat treatment temperature of the sheet resistance of the nickel silicide layer of formation at this moment.The transverse axis of the curve chart of Figure 39 is corresponding to make Ni film and p by heat treatment +Type silicon area or make Ni film and n +The heat treatment temperature of type silicon area reaction, the longitudinal axis of the curve chart of Figure 39 is corresponding to the sheet resistance value of the nickel silicide layer that forms by this heat treatment.The heat treatment that Figure 39 carried out is for to be undertaken about 30 seconds by RTA.In the curve chart of Figure 39, represent to make Ni film and p by heat treatment with white circle +The sheet resistance value of the nickel silicide layer that the reaction of type silicon area forms is represented to make Ni film and n by heat treatment with black circle +The sheet resistance value of the nickel silicide layer that the reaction of type silicon area forms.Need to prove that Figure 39 is corresponding to the above-mentioned Figure 23 that represents with wideer temperature province.
As shown in figure 39, if heat treatment temperature is low, then the nickel silicide layer of Xing Chenging is high-resistance Ni 2Si phase (Ni 2Si is about 30 Ω/ mutually), if the heat treatment temperature height, then the nickel silicide layer of Xing Chenging becomes low-resistance NiSi phase (NiSi is about 10 Ω/ mutually).But, about by Ni 2Si is phase-changed into the temperature of NiSi phase, Ni film and n +Type silicon area when reaction and Ni film and p +During the reaction of type silicon area is different.For example make Ni film and n +During the reaction of type silicon area, by being lower than the heat treatment of 300 ℃ temperature range, the Ni film is not by full consumption, and the Ni of remained unreacted forms Ni 2The nickel silicide layer of Si phase, by the heat treatment of the temperature range more than 300 ℃, below 360 ℃, the Ni film is formed Ni by full consumption 2The nickel silicide layer of Si phase, the heat treatment by the temperature range more than 390 ℃ forms the nickel silicide layer of NiSi phase.And make Ni film and p +During the reaction of type silicon area, by being lower than the heat treatment of 320 ℃ temperature range, the Ni film is not by full consumption, and the Ni of remained unreacted forms Ni 2The nickel silicide layer of Si phase, by more than 320 ℃, the temperature range that is lower than 340 ℃ heat-treats, the Ni film is fallen by full consumption, forms Ni 2The nickel silicide layer of Si phase by heat-treating in the temperature range more than 360 ℃, forms the nickel silicide layer of NiSi phase.
On Semiconductor substrate, form p +Type silicon area and n +The type silicon area forms Ni film about 10nm and the TiN film about 15nm thereon, makes Ni film and p by heat treatment then +Type silicon area or make Ni film and n +The reaction of type silicon area, Figure 40 is the curve chart of the reactivity of expression Ni film at this moment.The transverse axis of the curve of Figure 40 is corresponding to make Ni film and p by heat treatment +Type silicon area or make Ni film and n +The heat treatment temperature of type silicon area reaction, the longitudinal axis of the curve chart of Figure 40 is corresponding to the reactivity of Ni film.Heat treatment shown in Figure 40 is carried out about 30 seconds for utilizing RTA.In addition, in the curve chart of Figure 40, represent to make Ni film and p by heat treatment with white circle +The reactivity of the Ni film the during reaction of type silicon area is represented to make Ni film and n by heat treatment with black circle +The reactivity of the Ni film the during reaction of type silicon area.
As shown in figure 40, if heat treatment temperature is more than 320 ℃, then make Ni film and p +The reactivity of the Ni film in type silicon area when reaction and make Ni film and n +The reactivity of the Ni film the during reaction of type silicon area is basic identical, is 100%, and Ni is fallen by full consumption as can be known.Because Ni fallen by full consumption, so, be more than 320 ℃ the time in heat treatment temperature, be formed at p +(p on the type silicon area surface +The upper layer part of type silicon area) nickel silicide layer (Ni 2The Si phase) thickness be formed at n +(n on the type silicon area surface +The upper layer part of type silicon area) nickel silicide layer (Ni 2The Si phase) thickness is identical.
And when heat treatment temperature is lower than 320 ℃, make Ni film and p +The reactivity of the Ni film in type silicon area when reaction and make Ni film and n +The reactivity difference of the Ni film the during reaction of type silicon area.Heat treatment temperature makes Ni film and n when the scope more than 300 ℃, below 320 ℃ +The reactivity of the Ni film the during reaction of type silicon area is roughly 100%, and Ni is all consumed, n +(n on the type silicon area surface +The upper layer part of type silicon area) forms nickel silicide layer (Ni 2The Si phase).When heat treatment temperature is lower than 300 ℃,, make Ni film and n along with heat treatment temperature reduces +The reactivity of the Ni film the during reaction of type silicon area reduces, and when for example heat treatment temperature was 290 ℃, reactivity was about 98%, and when heat treatment temperature was 270 ℃, reactivity was about 60%.That is, in this heat-treatment temperature range (being lower than 300 ℃), Ni is not by full consumption, at n +(n on the type silicon area surface +The upper layer part of type silicon area) Ni of remained unreacted forms nickel silicide layer (Ni 2The Si phase), its thickness is also along with heat treatment temperature reduces and attenuation.
On the other hand, heat treatment temperature makes Ni film and p when the scope that is lower than 320 ℃ +The reactivity of the Ni film the during reaction of type silicon area reduces and reduces along with heat treatment temperature, and when for example heat treatment temperature was 310 ℃, reactivity was about 80%, and reactivity was about 40% when heat treatment temperature was 270 ℃.That is, when this heat-treatment temperature range (being lower than 320 ℃), Ni is not by full consumption, at p +(p on the type silicon area surface +The upper layer part of type silicon area) Ni of remained unreacted forms Ni 2Si phase nickel silicide layer, its thickness are also along with heat treatment temperature reduces and attenuation.
And then, if heat treatment temperature is lower than 320 ℃, then make Ni film and p +The reactivity of the Ni film the during reaction of type silicon area is lower than makes Ni film and n +The reactivity of the Ni film the during reaction of type silicon area.By making this Ni film and p +The reactivity of the Ni film in type silicon area when reaction with make Ni film and n +The difference of the reactivity of the Ni film in type silicon area when reaction and makes Ni film and n as can be known +Be formed at n during the reaction of type silicon area +(n on the type silicon area surface +The thickness of the nickel silicide layer upper layer part of type silicon area) is compared, and makes Ni film and p +Be formed at p during the reaction of type silicon area +(p on the type silicon area surface +The thickness attenuation of the nickel silicide layer upper layer part of type silicon area).
Figure 41 is that expression makes Ni film and n by above-mentioned heat treatment shown in Figure 40 +The reactivity of the Ni film in type silicon area when reaction with make Ni film and p by heat treatment +The curve chart of the difference of the reactivity of the Ni film the during reaction of type silicon area.
Make Ni film and n by heat treatment +The reactivity of the Ni film in type silicon area when reaction with make Ni film and p by heat treatment +Difference maximum when heat treatment temperature is 290 ℃ of the reactivity of the Ni film the during reaction of type silicon area is about 45%.Be higher than 290 ℃ temperature range in heat treatment temperature, along with heat treatment temperature raises, the difference of this reactivity reduces, and when heat treatment temperature was 310 ℃, the difference of reactivity was about 20%.When heat treatment temperature was lower than 290 ℃ temperature range, along with heat treatment temperature reduces, the difference of its reactivity reduced, and when heat treatment temperature was 270 ℃, the difference of reactivity was about 22%.
By the data of Figure 39～shown in Figure 41 as can be known, if more than 260 ℃, the temperature range that is lower than 320 ℃ heat-treats, and makes Ni film and n +Type silicon area and Ni film and p +The reaction of type silicon area is then at p +(p on the type silicon area surface +The upper layer part of type silicon area) forms Ni 2The nickel silicide layer of Si phase, its thickness is less than being formed on n +(n on the type silicon area surface +The upper layer part of type silicon area) Ni 2The nickel silicide layer of Si phase.
For example, on Semiconductor substrate, form p +Type silicon area and n +The type silicon area forms Ni film about 10nm and the TiN film about 15nm thereon, is that 310 ℃, heat treatment time are 30 seconds heat treatment by heat treatment temperature then, makes Ni film and p +Type silicon area and n +The reaction of type silicon area.At this moment, at n +(n on the type silicon area surface +The upper layer part of type silicon area) Ni of formation thickness 15nm (reactivity is 100%) 2The nickel silicide layer of Si phase is at p +(p on the type silicon area surface +The upper layer part of type silicon area) Ni of formation thickness 12nm (reactivity is 80%) 2The nickel silicide layer of Si phase.Herein, the reactivity in the 1st heat treatment is 100% o'clock, Ni 2The thickness of Si film is about 1.5 times of Ni film thickness.
As mentioned above, in the present embodiment, make metallic element M and the p that constitutes metal film 12 +The reactivity of the metal film 12 the when Si of N-type semiconductor N zone 10b reacts is lower than makes metallic element M and the n that constitutes metal film 12 +The temperature (when metal film 12 was the Ni film, this temperature was more than 260 ℃, is lower than 320 ℃) of the reactivity of the metal film the when Si of N-type semiconductor N zone 9b reacts is carried out the 1st heat treatment of step S3a.Can make the 1st heat treated stage of step S3a be formed at p thus +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) metal silicide layer (M 2Si) thickness of 41a (above-mentioned the 2nd thickness) is formed at n less than the 1st heat treated stage at step S3a +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) metal silicide layer (M 2Si) thickness of 41a (above-mentioned the 1st thickness).
Next, by carrying out wet clean process, remove barrier film 13 and unreacted formation metal film 12 metallic element M (promptly not with gate electrode 8a, 8b, n +N-type semiconductor N zone 9b or p +The metallic element M of the formation metal film 12 of N-type semiconductor N zone 10b reaction) (the step S4 of Figure 36).At this moment, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p + Kish silicide layer 41a on the surface of N-type semiconductor N zone 10b.The wet clean process of step S4 (barrier film 13 and unreacted metal film 12 remove operation) is identical with above-mentioned embodiment 1, can be undertaken by the wet-cleaned of having used sulfuric acid or the wet-cleaned of having used sulfuric acid and aqueous hydrogen peroxide solution etc.
Next, Semiconductor substrate 1 is implemented the 2nd heat treatment (the step S5a of Figure 36).Same with the 2nd heat treatment phase of above-mentioned steps S5, the 2nd heat treatment of step S5a preferably is being full of inert gas (for example Ar gas or He gas) or N 2In the environment of gas atmosphere, under normal pressure, carry out.The 2nd heat treatment of step S5a is carried out under the heat treatment temperature of the 1st heat treated heat treatment temperature that is higher than above-mentioned steps S3a.When metal film 12 was the Ni film, the 2nd heat treatment temperature of step S5a for example can be about 550 ℃.For example, be full of inert gas (for example Ar gas or He gas) or N 2In the environment of gas atmosphere, descend for about 550 ℃, use the RTA method that Semiconductor substrate 1 is implemented about 30 seconds heat treatment, can carry out the 2nd heat treatment of step S5a thus in normal pressure, temperature.By carrying out the 2nd heat treatment of step S5a, as shown in figure 38, the M that the 1st heat treatment by step S3a forms 2The metal silicide layer 41a of Si phase becomes MSi phase (the metal silicide layer 41b of MSi phase), and the ratio of components of metallic element M and Si near 1: 1, forms stable metal silicide layer 41b in stoichiometric proportion.Need to prove that the resistivity of MSi phase is lower than M 2Si reaches MSi mutually 2Phase, metal silicide layer 41b keeps low-resistance MSi phase in the later operation of step S5a (manufacturing to semiconductor device finishes), in the semiconductor device of making (even for example Semiconductor substrate 1 being become the independently state of semiconductor chip), metal silicide layer 41b becomes low-resistance MSi phase.
If by the 2nd heat treatment of step S5a, from M 2The metal silicide layer 41a of Si phase becomes the metal silicide layer 41b of MSi phase, and then thickness also increases.But, be formed at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) metal silicide layer (M 2The increment rate of the thickness when the Si phase) 41a becomes metal silicide layer (MSi phase) 41b be formed at p +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) metal silicide layer (M 2The increment rate of the thickness when the Si phase) 41a becomes metal silicide layer (MSi phase) 41b is identical.So the 1st heat treated stage that maintains step S3a is formed at n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) metal silicide layer (M 2The Si phase) thickness of 41a be formed at p in the 1st heat treated stage of step S3 +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) metal silicide layer (M 2The Si phase) ratio of the thickness of 41a, the 2nd heat treatment by step S5a is at p +(p on the surface of N-type semiconductor N zone 10b +The upper layer part of N-type semiconductor N zone 10b) and n +(n on the surface of N-type semiconductor N zone 9b +The upper layer part of N-type semiconductor N zone 9b) forms metal silicide layer 41b.
For example, on Semiconductor substrate, form p +Type silicon area and n +The type silicon area forms Ni film about 10nm and the TiN film about 15nm thereon, carries out step S3a then, i.e. the 1st heat treatment by 310 ℃ of heat treatment temperatures, heat treatment time 30 seconds makes Ni film and p +Type silicon area and n +The reaction of type silicon area.At this moment, at n +(n on the type silicon area surface +The upper layer part of type silicon area) Ni of formation thickness 15nm (reactivity is 100%) 2The nickel silicide layer of Si phase is at p +(p on the type silicon area surface +The upper layer part of type silicon area) Ni of formation thickness 12nm (reactivity is 80%) 2The nickel silicide layer of Si phase.Then, by carrying out wet clean process, remove TiN film and unreacted Ni after, carry out step S5a, promptly heat-treat the 2nd heat treatment of 550 ℃ of temperature, heat treatment time 30 seconds.Thus at n +(n on the type silicon area surface +The upper layer part of type silicon area) nickel silicide layer of the NiSi phase of formation thickness 21nm (reactivity in the 1st heat treatment is 100% o'clock, and the thickness of NiSi film is about 2.1 times of Ni film thickness) is at p +(p on the type silicon area surface +The upper layer part of type silicon area) nickel silicide layer of the NiSi phase of formation thickness 16.8nm.
For easy understanding, above-mentioned relation is summarized as follows.Figure 42～Figure 46 is the major part profile in the semiconductor device manufacturing process in step S2, S3a, S4, each stage of S5, expression p +Top near zone and the n of N-type semiconductor N zone 10b +The top near zone of N-type semiconductor N zone 9b.Figure 42 represents to carry out the stage (stage before the 1st heat treatment of step S3a) that step S1, S2 form metal film 12 and barrier film 13.Figure 43 represents to have carried out the 1st heat treated stage (carrying out the metal film 12 of step S4 and removing the operation stage before of barrier film 13) of step S3a.Figure 44 represents to have carried out the metal film 12 of step S4 and the stage that barrier film 13 is removed operation (carrying out the 2nd heat treatment stage before of step S5a).Figure 45 represents to have carried out the 2nd heat treated stage (forming dielectric film 42 stage before) of step S5a.
As shown in figure 42, at p +N-type semiconductor N zone 10b and n +N-type semiconductor N zone 9b goes up and forms shared metal film 12, so, the stage before the 1st heat treatment of carrying out step S3a, p +Thickness (thickness) tn1 and the n of the metal film 12 on the 10b of N-type semiconductor N zone +The thickness tn2 identical (being tn1=tn2) of the metal film 12 on the 9b of N-type semiconductor N zone.And,, as shown in figure 43, make p by carrying out the 1st heat treatment of step S3a +N-type semiconductor N zone 10b and n +N-type semiconductor N zone 9b and metal film 12 reactions are at p +N-type semiconductor N zone 10b and n +Form metal silicide layer 41a on the surface of N-type semiconductor N zone 9b.Metal silicide layer 41a is equivalent to the metal silicide layer 41 of above-mentioned embodiment 1, in above-mentioned embodiment 1, the 1st heat treatment by step S3 forms the metal silicide layer 41 of MSi phase, and in the present embodiment, and the 1st heat treatment by step S3a forms M 2The metal silicide layer 41a of Si phase.
As mentioned above, the 1st heat treatment of step S3a is at the p of p channel-type MISFETQp +The reactivity of N-type semiconductor N zone 10b and metal film 12 is lower than the n of n channel-type MISFETQn +The temperature range of the reactivity of N-type semiconductor N zone 9b and metal film 12 is carried out.Herein, p +The reactivity of N-type semiconductor N zone 10b and metal film 12 is corresponding to being positioned at p +Pass through the 1st heat treatment and the p of step S3a in the metal film 12 on the 10b of N-type semiconductor N zone +The 10b reaction of N-type semiconductor N zone forms the ratio of the part of metal silicide layer 41a.Equally, n +The reactivity of N-type semiconductor N zone 9b and metal film 12 is corresponding to being positioned at n +Pass through the 1st heat treatment and the n of step S3a in the metal film 12 on the 9b of N-type semiconductor N zone +The 9b reaction of N-type semiconductor N zone forms the ratio of the part of metal silicide layer 41a.So, in the 1st heat treatment of step S3a, be positioned at p +In the metal film 12 on the 10b of N-type semiconductor N zone and p +The ratio (thickness) of the part of N-type semiconductor N zone 10b reaction is less than being positioned at n +In the metal film 12 on the 9b of N-type semiconductor N zone and n +The ratio (thickness) of the part of N-type semiconductor N zone 9b reaction.In other words, in the 1st heat treatment of step S3a, be positioned at p +Non-reacted parts in the metal film 12 on the 10b of N-type semiconductor N zone is not (with p +The part of N-type semiconductor N zone 10b reaction) ratio (thickness) is greater than being positioned at n +Non-reacted parts in the metal film 12 on the 9b of N-type semiconductor N zone is not (with n +The ratio (thickness) of the part of N-type semiconductor N zone 9b reaction.
Therefore, the 1st heat treatment by step S3a forms the stage of metal silicide layer 41a, as shown in figure 43, is formed at p +The thickness t n3 of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 10b is less than being formed at n +The thickness t n4 of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 9b (is tn3＜tn4).
In the 1st heat treatment of step S3a, be positioned at p +Metal film 12 on the 10b of N-type semiconductor N zone be positioned at n +Metal film 12 on the 9b of N-type semiconductor N zone is compared, and reactivity is low.Therefore, in the 1st heat treatment anteposition in p +Metal film 12 on the 10b of N-type semiconductor N zone through the 1st heat treatment and not all with p +The 10b reaction of N-type semiconductor N zone, a part wherein and p +The 10b reaction of N-type semiconductor N zone.That is, in the 1st heat treatment step of step S3a, at metal film 12 and p +In the reaction of N-type semiconductor N zone 10b, metal film 12 is not fallen (reaction) by full consumption, be formed at p +The lip-deep metal silicide layer 41a of N-type semiconductor N zone 10b goes up the metallic element M of the formation metal film 12 of remained unreacted.So after the 1st heat treatment of step S3a, the non-reacted parts 12a in the metal film 12 remains in p +On the metal silicide layer 41a on the 10b of N-type semiconductor N zone, its thickness (residual thickness) tn5 (is tn5＜tn1) less than initial stage thickness (thickness tn1).
On the other hand, in the 1st heat treatment of step S3a, be positioned at n +Metal film 12 on the 9b of N-type semiconductor N zone be positioned at p +Metal film 12 on the 10b of N-type semiconductor N zone is compared the reactivity height.Therefore, after the 1st heat treatment of step S3a, remain in n +Thickness (residual thickness) tn6 of the non-reacted parts 12a of the metal film 12 on the metal silicide layer 41a on the 9b of N-type semiconductor N zone is less than remaining in p +Thickness (residual thickness) tn5 of the non-reacted parts 12a of the metal film 12 on the metal silicide layer 41a on the 10b of N-type semiconductor N zone (is tn6＜tn5).Need to prove, after the 1st heat treatment of step S3a, be positioned at n +Metal film 12 on the 9b of N-type semiconductor N zone can be all and n +N-type semiconductor N zone 9b reaction also can incomplete reaction, a part and n +The 9b reaction of N-type semiconductor N zone.Be positioned at n +Metal film 12 whole and n on the 9b of N-type semiconductor N zone +When N-type semiconductor N zone 9b reacts, after the 1st heat treatment of step S3a, at n +The non-reacted parts 12a of kish film 12 not on the metal silicide layer 41a on the 9b of N-type semiconductor N zone, above-mentioned thickness (residual thickness) tn6 is 0 (tn6=0).And when being positioned at n +A part and n in the metal film 12 on the 9b of N-type semiconductor N zone +During N-type semiconductor N zone 9b reaction, after the 1st heat treatment of step S3a at n +Metal silicide layer 41a on the 9b of N-type semiconductor N zone goes up the non-reacted parts 12a (tn6＞0) of kish film 12, and its thickness t n6 is less than above-mentioned thickness t n5 (tn6＜tn5).Need to prove that Figure 43 represents n +Situation when the metal silicide layer 41a on the 9b of N-type semiconductor N zone goes up the non-reacted parts 12a of kish film 12, but n +The non-reacted parts 12a of kish film 12 not on the metal silicide layer 41a on the 9b of N-type semiconductor N zone.
After the 1st heat treatment of step S3a, as shown in figure 44, the non-reacted parts 12a by step S4 removes barrier film 13 and metal film 12 then as shown in figure 45, by carrying out the 2nd heat treatment of step S5a, makes M 2The metal silicide layer 41a of Si phase becomes the metal silicide layer 41b of MSi phase.That is, the 2nd heat treatment by step S5a makes M 2The metal silicide layer 41a of Si phase and gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The silicon (Si) of N-type semiconductor N zone 10b further reaction (carries out M 2The reaction of Si+Si → 2MSi), at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +Form on the surface of N-type semiconductor N zone 10b by than M 2Si stablizes mutually and is the metal silicide layer 41b of the MSi phase composition of low-resistivity.Therefore, the 2nd heat treatment of step S5a can make M 2The metal silicide layer 41a of Si phase becomes under the temperature of metal silicide layer 41b of MSi phase and carries out.
p +The thickness t n3 of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 10b is less than n +The thickness t n4 of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 9b (tn3＜tn4), so, p after the 2nd heat treatment of step S5a +The thickness t n7 of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is less than n +The thickness t n8 of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b (is tn7＜tn8).
Figure 46 is the step S1～S5a (S1 of expression according to the present embodiment 3, S2, S3a, S4, S5a) curve chart of distribution (inequality) of leakage current of the nickel silicide layer (in the curve chart of Figure 46, being expressed as " embodiment 3 ") that forms and the nickel silicide layer (in the curve chart of Figure 46, being expressed as " comparative example ") that forms according to the step of comparative example.The transverse axis of the curve chart of Figure 46 is corresponding to leakage current, and the longitudinal axis of the curve chart of Figure 46 is corresponding to probability distribution (cumulative frequency, Cumulative Frequency).The step of the comparative example among Figure 46 (operation) is the step S1～S5a of the present embodiment 3, and wherein the 1st of step S3a the heat treated heat treatment temperature is 320 ℃.
As shown in figure 46, compare with the nickel silicide layer that forms according to the step of above-mentioned comparative example, the nickel silicide layer leakage current inequality of the nickel silicide layer that forms according to step S1～S5a of the present embodiment 3 is little.Think that it be the reasons are as follows.In the comparative example, at p +(p on the type silicon area surface +The upper layer part of type silicon area) and n +(n on the type silicon area surface +The upper layer part of type silicon area) nickel silicide layer of the roughly the same thickness of formation.But, because and n +The type silicon area is compared, and Ni is diffused into p easily +The type silicon area is so be formed at p +(p on the type silicon area surface +Misgrowth takes place in the nickel silicide layer upper layer part of type silicon area) easily.Therefore, although form the nickel silicide layer of same thickness, with n +The type silicide regions is compared, p +The junction leakage inequality takes place in type silicon area easily.
And in the present embodiment 3, be formed at p +(p on the type silicon area surface +The thickness of the nickel silicide layer upper layer part of type silicon area) is less than being formed at n +(n on the surface of type silicide regions +The thickness of the nickel silicide layer upper layer part of type silicon area), so, p can be reduced +Junction leakage inequality in the type silicide regions.
That is, with n +The type silicon area is compared, p +The type silicon area spreads Ni (promoting the reaction of Ni and Si easily) easily, and is formed at n +The lip-deep nickel silicide layer of type silicon area is compared, and is formed at p +Misgrowth takes place in type silicon area lip-deep nickel silicide layer easily.Easily at p +The misgrowth of the nickel silicide layer that the type silicon area takes place mainly is because NiSi 2Part from the nickel silicide course of the NiSi phase semiconductor regions (p under it +Type silicon area, n +The type silicon area) local growth.If NiSi 2Part is from nickel silicide course p +Type silicon area or n +Type silicon area local growth then causes (the NiSi of its misgrowth portion 2) near the composition surface, make this p +Type silicon area or n +The junction leakage of type silicon area increases.In addition,, but take place, exist this excrescent transistor AND gate of generation that this excrescent transistor does not take place in the part because the misgrowth of this nickel silicide layer is not to take place at whole nickel silicide layer, so, each transistorized junction leakage inequality caused.With n +The type silicon area is compared, and nickel silicide layer is easily at p +Type silicon area generation misgrowth is with n +The type silicon area is compared, p +The increase of junction leakage or the increase of junction leakage inequality take place in type silicon area easily.
In order to suppress p +The increase of the increase of the junction leakage of type silicon area or junction leakage inequality reduces to be formed at p +The thickness of the lip-deep nickel silicide layer of type silicon area is effective.If reduce to be formed at p +The thickness of the lip-deep nickel silicide layer of type silicon area, the then quantitative change along with nickel silicide layer few (thickness attenuation) is for carrying out NiSi 2Part misgrowth and to be fed into the Ni quantitative change at NiSi/Si interface few can suppress NiSi 2Part from nickel silicide course p +The growth of type silicon area side local anomaly.Therefore, can reduce the excrescent transistorized occurrence frequency of nickel silicide layer.In addition, along with the nickel silicide layer attenuation, from nickel silicide layer to p +The distance on the composition surface of type silicon area is elongated, and then can reduce junction leakage, so, even nickel silicide layer misgrowth also can suppress the influence of this misgrowth to junction leakage.So, by reducing to be formed at p +The thickness of the lip-deep nickel silicide layer of type silicon area can suppress p +The increase of the increase of the junction leakage of type silicon area and junction leakage inequality.
But, at p +On the type silicon area surface and n +When forming the nickel silicide layer of same thickness on the type silicon area surface, if make p +The lip-deep nickel silicide layer attenuation of type silicon area then causes being difficult to take place misgrowth (NiSi 2Part is from nickel silicide course n +Type silicon area local growth) n +The also attenuation of the lip-deep nickel silicide layer of type silicon area.This causes at n +The effect that forms the reduction resistance that nickel silicide layer produced on the type silicon area surface reduces.
So, make in the present embodiment 3 and be formed at p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is less than being formed at n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.Therefore, by reducing to be formed at easy generation misgrowth (MSi 2The part from metal silicide layer 41b to p +N-type semiconductor N zone 10b local growth) p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b can suppress p +The increase of the junction leakage of N-type semiconductor N zone 10b and the increase of junction leakage inequality.In addition, be formed at by increase and be difficult to take place misgrowth (MSi 2The part from metal silicide layer 41b to n +The local growth of N-type semiconductor N zone 9b) n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b can positively obtain at n +The effect of the reduction resistance that formation metal silicide layer 41b is produced on the surface of N-type semiconductor N zone 9b.
As mentioned above, in the present embodiment 3, can be formed at n keeping +In the time of the thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b, reduce to be formed at p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b.Therefore, can obtain at n simultaneously +Form the low effect of resistance drop that thick relatively metal silicide layer 41b produced on the surface of N-type semiconductor N zone 9b and at p +Form the reduction p that the metal silicide layer 41b that compares relative thin with above-mentioned thickness is produced on the surface of N-type semiconductor N zone 10b +The effect of junction leakage among the 10b of N-type semiconductor N zone and reduction junction leakage inequality.So, can improve the reliability of semiconductor device.Can also improve the performance of semiconductor device.
The 1st heat treated temperature by controlled step S3a can change n +N-type semiconductor N zone 9b goes up and p +The thickness of metal silicide layer 41a on the 10b of N-type semiconductor N zone can make the p after the 2nd heat treatment of step S5a thus +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is less than n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.Therefore, need not to increase the worker ordinal number of semiconductor device, can make p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is less than n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.So, can reduce the worker ordinal number of semiconductor device, and the manufacturing process that can simplify semiconductor device, can reduce the manufacturing cost of semiconductor device.
p +N-type semiconductor N zone 10b and n +The junction depth of N-type semiconductor N zone 9b is shallow more, and the influence to junction leakage during metal silicide layer misgrowth is big more.In the present embodiment, be formed at p by making +The lip-deep metal silicide layer 41b ratio of N-type semiconductor N zone 10b is formed at n +The lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b is thin, improves the problem of the junction leakage that the misgrowth of metal silicide layer causes.Therefore, can make p +N-type semiconductor N zone 10b and n +The junction depth of N-type semiconductor N zone 9b shoals, and energy miniaturization field-effect transistor, helps the miniaturization of semiconductor device.
There is Pt in Pt (platinum) 2Si reaches the PtSi phase mutually, but does not have PtSi 2Phase.But, the inventor finds after deliberation, not only when using Ni film or Ni alloy film as metal film 12, when using the Pt film as metal film 12, MISFET compares with the n channel-type, the increase and the junction leakage inequality of junction leakage also takes place in the source drain of p channel-type MISFET easily, by being suitable for the manufacturing process of the present embodiment, can improve the problem of junction leakage.Therefore, in the present embodiment and following embodiment 4, also can use the Pt film as metal film 12.
When using Ni film or Ni alloy film as metal film 12, as mentioned above, the resistivity of MSi phase is lower than M 2The Si phase is so the metal silicide layer 41b when semiconductor device is finished uses MSi mutually rather than M 2The Si phase.
And when using the Pt film as metal film 12, the metal silicide layer 41b when semiconductor device is finished uses Pt 2Si (two Platinum Silicides) phase rather than PtSi (platinum list silicide) phase.This is because PtSi and Pt 2The resistivity of Si all is about 30 μ Ω cm, Pt 2The silicon consumption of Si is less than the Si consumption of PtSi, compares during for PtSi with metal silicide layer 41b, and metal silicide layer 41b is Pt 2Can increase the distance of metal silicide layer during Si, so can reduce leakage current to knot.
Therefore, when using Pt (platinum) film as metal film 12 and when using Ni film or Ni alloy film as metal film 12, the metallic element M among metal silicide layer 41a, the 41b is different with the ratio of components of Si.As mentioned above, when using Ni film or Ni alloy film as metal film 12, metal silicide layer 41a is M 2The Si phase, metal silicide layer 41b is the MSi phase.
On the other hand, when using Pt (platinum) film,, make as the Pt film of metal film 12 and gate electrode 8a, 8b, n by the 1st heat treatment of above-mentioned steps S3a as metal film 12 +N-type semiconductor N zone 9b and p +The 10b selective reaction of N-type semiconductor N zone forms the metal silicide layer 41a that is made up of the silicide of Pt.Metal silicide layer 41a in such cases by with Pt 2Si (two Platinum Silicides) compares the silicide that more is rich in metal (promptly and Pt 2Si compares, the silicide that the atomic ratio of Pt is big, promptly the atomic ratio of Pt is greater than 2/3 silicide) form, more specifically, by Pt 5Si 2(five platinum disilicides) formed.Be rich in metal herein, and be meant that the atomic ratio of metallic element is many.Remove unreacted Pt film after the 1st heat treatment of step S3a, by the 2nd heat treatment of above-mentioned steps S5a, make metal silicide layer 41a (Pt then 5Si 2) two metal silicides that become by Pt are Pt 2The metal silicide layer 41b that Si (two Platinum Silicides) forms makes it stable.Pt 2Si is stable below 700 ℃, and no phase transformation can obtain Pt 2The metal silicide layer 41b of Si phase.As mentioned above, when using the Pt film as metal film 12, by step S3a the 1st heat treatment, forming by two metal silicides with Pt (constituting the metallic element of metal film 12) (is Pt 2Si) compare the silicide that more is rich in metal and (be Pt herein 5Si 2) the metal silicide layer 41a that forms, by the 2nd heat treatment of step S5a, two metal silicides (dimetalsilicide) that metal silicide layer 41a is become by Pt (constituting the metallic element of metal film 12) (are Pt 2Si) the metal silicide layer 41b of Zu Chenging.But, from Pt 2Local (misgrowth) PtSi phase that produces of the metal silicide layer 41b of Si phase, distance from metal silicide layer 41b to knot is diminished, might increase junction leakage, so, when using Pt (platinum) film as metal film 12, it also is effective being suitable for the present embodiment and following embodiment 4.
But, compare when using the Pt film as metal film 12, be suitable for the manufacturing process of the present embodiment and following embodiment 4 when using Ni film or Ni alloy film (the preferred Ni-Pt alloy film of Ni alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film) as metal film 12, effect is more obvious.
Utilize the thickness (deposition thickness, perpendicular to the thickness of the direction of the interarea of Semiconductor substrate 1) of the metal film 12 that step S1 forms to be preferably 4～33nm in the present embodiment.If metal film 12 is thin excessively, then the thickness of metal silicide layer 41b became thin, and resistance increases.The thickness of metal silicide layer 41b is obtained by the sheet resistance of the desired metal silicide layer 41b of design and the resistivity of silicide material, when metal film 12 is the Ni film, be necessary for the nickel silicide layer (NiSi phase) of the above thickness of 8.4nm, so the lower limit thickness of Ni film is 4nm.If metal film 12 is blocked up, then the thickness of metal silicide layer 41b is blocked up, might cause the increase of leakage current, and is also unfavorable to the miniaturization of MIS.When metal film 12 was the Ni film, the thickness of nickel silicide layer (NiSi phase) was necessary for below the 21nm, and the reactivity when the 1st heat treated lower limit temperature (260 ℃) of step S3 is 30%, so the upper limit thickness of Ni film is 33nm.
Utilize the self-aligned silicide technology, (be n at gate electrode 8a and the source drain of n channel-type MISFETQn herein +N-type semiconductor N zone 9b) surface and gate electrode 8b and the source drain of p channel-type MISFETQp (are p herein +N-type semiconductor N zone 10b) after surface forms low-resistance metal silicide layer 41b, is identically formed wiring with above-mentioned embodiment 1.Figure 47 is the major part profile in the manufacturing process of the semiconductor device after Figure 38.
Promptly, as shown in figure 47, be identically formed dielectric film 42 and dielectric film 43 with above-mentioned embodiment 1, on dielectric film 43,42, form contact hole 44, in contact hole 44, form embolism 45, landfill form on the dielectric film 43 of embolism 45 and stop dielectric film 51 and dielectric film 52, form wiring trench 53, in wiring trench 53, imbed insulated conductor film 54 and copper film, form wiring 55.The flush types wiring that wiring 55 is not limited to utilize inlaying process to form can also be for utilizing the film formed wiring of conductor (for example tungsten wiring or aluminium wiring) that forms pattern etc., and this is also identical in above-mentioned embodiment 1,2 and following embodiment 4～6.
In the present embodiment, in the various heating processes (film formation process of for example various dielectric films or electrically conductive film and so on is followed the operation of the heating of Semiconductor substrate 1) after the 2nd heat treatment of the step S5a of Figure 36, also make the temperature of Semiconductor substrate 1 not be higher than the 2nd heat treated heat treatment temperature of step S5a.Can prevent thus because of the heating (film formation process of for example various dielectric films or electrically conductive film) in the operation after the step S5a, make the metallic element M that constitutes metal silicide layer (MSi phase) 41b at Semiconductor substrate 1 ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) spreads in, cause the characteristic variations of n channel-type MISFETQn and p channel-type MISFETQp.
As mentioned above, can only make the source drain p that is formed at p channel-type MISFETQp according to the present embodiment 3 +The thickness attenuation of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b, and do not change on the surface of gate electrode 8b of the gate electrode 8a that is formed at n channel-type MISFETQn and p channel-type MISFETQp and the source drain n of n channel-type MISFETQn +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.So, do not cause the increase of resistance value of gate electrode 8b of the gate electrode 8a of n channel-type MISFETQn and p channel-type MISFETQp and the source drain n of n channel-type MISFETQn +The junction leakage of N-type semiconductor N zone 9b and the increase of resistance, and can reduce the source drain p of p channel-type MISFETQp +The inequality of the junction leakage of N-type semiconductor N zone 10b.Therefore the characteristic variations of p channel-type MISFETQp can be prevented, and then the performance of semiconductor device can be improved.
(embodiment 4)
In above-mentioned embodiment 3, under the state that does not form barrier film on the metal silicide layer 41a, carry out the 2nd heat treatment of step S5a, but in the present embodiment, as described below, in the manufacturing process of above-mentioned embodiment 3, be provided with the 2nd heat treatment of carrying out step S5a under the state of barrier film 13a.
Figure 48 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment 4, corresponding to Figure 31 of above-mentioned embodiment 2 or Figure 36 of above-mentioned embodiment 3.After Figure 48 represents to obtain the structure of above-mentioned Fig. 7, utilize the self-aligned silicide treatment process at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b forms the manufacturing process flow of the operation of metal silicide layer (metal semiconductor conversion zone).Figure 49～Figure 52 is the major part profile in the manufacturing process of semiconductor device of the present embodiment 4.
The manufacturing process of the semiconductor device of the present embodiment 4 is identical with above-mentioned embodiment 3 to the operation of removing barrier film 13 and unreacted metal film 12 by the wet clean process of carrying out above-mentioned steps S4, so omit explanation here, the operation after the above-mentioned steps S4 described.
Carry out above-mentioned steps S4 in the same manner with above-mentioned embodiment 3, after roughly being equivalent to the structure of Figure 49 of above-mentioned Figure 37, as shown in figure 50, on Semiconductor substrate 1, comprise on the metal silicide layer 41a deposition (formation) barrier film (the 2nd barrier film, Stress Control film, block film) 13a (the step S11 of Figure 48).
The barrier film 13a of above-mentioned steps S11 formation operation is identical with the barrier film 13a formation operation of step S11 in the above-mentioned embodiment 2 in the present embodiment.That is, the preferred material of the barrier film 13a in the present embodiment, become the situation of the barrier film 13a in embrane method and stress (stress that barrier film 13a produces Semiconductor substrate 1) and the above-mentioned embodiment 2 identical.So barrier film 13a makes Semiconductor substrate 1 produce the film of tensile stress.
Next, carry out the 2nd heat treatment of the step S5a identical with above-mentioned embodiment 3.In the present embodiment 4, the 2nd heat treatment of step S5a is carried out under the state that has formed barrier film 13a, and the 2nd heat treated condition of step S5a and effect are identical with above-mentioned embodiment 3.
Identical with above-mentioned embodiment 3, the present embodiment 4 also by carrying out the 2nd heat treatment of step S5a, makes the M that forms in the 1st heat treatment of step S3a 2The metal silicide layer 41a of Si phase becomes the metal silicide layer 41b of MSi phase, and the ratio of components of metallic element M and Si more near 1: 1, forms stable metal silicide layer 41b in stoichiometric proportion.In addition, identical with above-mentioned embodiment 3, in the present embodiment 4, also make the p after the 2nd heat treatment of step S5a +The n of the thickness of lip-deep metal silicide layer (MSi) 41b of N-type semiconductor N zone 10b after less than the 2nd heat treatment of step S5a +The thickness of lip-deep metal silicide layer (MSi) 41b of N-type semiconductor N zone 9b.
Identical with above-mentioned embodiment 3, the 2nd heat treatment of the step S5a in the present embodiment 4 also is being higher than under the heat treatment temperature of the 1st heat treated heat treatment temperature of step S3a to be carried out, and when for example metal film 12 was Ni, heat treatment temperature can be about 550 ℃.In addition, identical with above-mentioned embodiment 3, in the present embodiment 4, also the manufacturing until semiconductor device finishes (for example cutting semiconductor substrate 1 becomes independently semiconductor chip) after the 2nd heat treatment of step S5a, Semiconductor substrate 1 is not in be higher than under the temperature of the 2nd heat treated heat treatment temperature of step S5a.
In addition, barrier film 13a be difficult to metal silicide layer 41a, 41b the reaction film, even carry out the 2nd heat treatment of step S5a, do not react with metal silicide layer 41a, 41b yet.If the 2nd heat treatment of step S5a makes barrier film 13a and metal silicide layer 41a, 41b reaction, then might cause the composition of metal silicide layer 41b to change.Therefore, identical with above-mentioned embodiment 2, in the present embodiment, by make barrier film 13a be difficult to metal silicide layer 41a, 41b the reaction film, metal silicide layer 41a, 41b and barrier film 13a reaction in the 2nd heat treatment of step S5a can be prevented, and then metal silicide layer 41b can be positively formed.As the above-mentioned barrier film 13a that is difficult to metal silicide layer 41a, 41b reaction, preferred titanium nitride (TiN) film or titanium (Ti) film.
By after the 2nd heat treatment of step S5a, carrying out wet clean process etc., shown in Figure 51, remove barrier film 13a (the step S12 of Figure 48).At this moment, gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p + Kish silicide layer 41b on the surface of N-type semiconductor N zone 10b.The wet clean process of step S12 can be undertaken by the wet-cleaned of having used sulfuric acid or the wet-cleaned of having used sulfuric acid and aqueous hydrogen peroxide solution etc.It is identical that the barrier film 13a that the barrier film 13a of above-mentioned steps S12 in the present embodiment removes the step S12 in operation and the above-mentioned embodiment 2 removes operation.
Operation after this is identical with above-mentioned embodiment 3.Promptly, identical with above-mentioned embodiment 1～3, shown in Figure 52, form dielectric film 42 and dielectric film 43, on dielectric film 43,42, form contact hole 44, in contact hole 44, form embolism 45, at landfill form to stop dielectric film 51 and dielectric film 52 on the dielectric film 43 of embolism 45, form wiring trench 53, in wiring trench 53, imbed insulated conductor film 54 and copper film, form wiring 55.
Barrier film 13a in the present embodiment is also identical with barrier film 13, the film that sees through as Stress Control film (film of the stress of control Semiconductor substrate active region) and anti-block, for control action in the stress of Semiconductor substrate 1 with prevent the oxidation etc. of metal film 12 and be arranged on the metal film 12.Therefore, can use the film identical, can preferably use TiN film or Ti film as barrier film 13a with barrier film 13.
With reference to the explanation that Figure 18～Figure 22 carried out, the inventor etc. find forming in the manufacture process of nickel silicide layer NiSi by the self-aligned silicide technology as above-mentioned 2Easy groove misgrowth from nickel silicide course MISFET.Inventor's (the section observation of semiconductor device and composition analysis of section etc.) has by experiment confirmed above-mentioned NiSi 2Excrescent generation.And, if NiSi 2From the misgrowth of nickel silicide course groove, then cause the increase of the leakage current between the source drain of MISFET, perhaps cause the increase of the diffusion resistance in source drain zone.
Research NiSi 2Find main because following 2 reasons from the excrescent reason of nickel silicide course groove.The 1st reason is that action of compressive stress is in silicon area (silicon area that Ni can spread) when forming nickel silicide layer.The 2nd reason is that there is oxygen in the surface when forming nickel silicide layer.In the 1st reason and the 2nd reason, the influence of the 1st reason is big.
MISFET is formed at the active region by the Semiconductor substrate 1 of element separated region 4 regulations, but as described in the 1st reason, the active region that forms MISFET is being produced under the state of compression, when following the heat treatment of the reaction that Ni diffusion (moving) causes, compression helps the Anomalous Diffusion of Ni, NiSi 2Easily from the misgrowth of nickel silicide course groove.Think that reason is if action of compressive stress, then constitutes the lattice size (lattice spacing) of the Si of Semiconductor substrate 1 (active region) in Semiconductor substrate 1 to diminish, near the NiSi of lattice spacing less than Si 2Lattice size (lattice spacing), make thus between the lattice of Ni and Si and replace easily.In addition, as described in the 2nd reason, if there is oxygen, the defective that then oxygen caused increases, and promotes NiSi 2Misgrowth.This is because Ni spreads by the defective that produces easily.
As implement as described in the scheme 1～6, when forming element separated region 4 in the ditch 4a on the Semiconductor substrate 1 by being formed at insulating material ( dielectric film 4b, 4c) landfill, promptly, when utilizing the STI method to form element separated region 4, compare when utilizing LOCOS (Local Oxidation of Silicon) method to form the element separated region, the compression that acts on the active region between the element separated region 4 becomes big.This is owing to be formed at the active region of action of compressive stress between element separated region 4 that the sidewall extruding active region side of the ditch 4a on the Semiconductor substrate 1 produces.Particularly the element separated region 4 usefulness insulating materials (referring to dielectric film 4c here) in the landfill ditch 4a are when utilizing the dielectric film (for example silicon oxide film) of plasma CVD method (particularly HDP-CVD method) film forming, with O 3Compare during-TEOS oxide-film (utilize hot CVD method form dielectric film) etc., the contraction during sintering is little, becomes big so element separated region 4 acts on the compression of the active region that forms MIS.
In the present embodiment 4, resulting under the state that the compression of element separated region 4 (element separated region 4 acts on the compression of the active region that forms MISFET) offset by the barrier film 13a that is made Semiconductor substrate 1 produce tensile stress, carry out the 2nd heat treatment of step S5a, make M 2The metal silicide layer 41a of Si phase becomes low resistance and stable MSi phase metal silicide layer 41b.Can prevent that thus compression from promoting MSi in the 2nd heat treatment of step S5a 2From metal silicide layer 41a, 41b to groove misgrowth.So, in the present embodiment 4,, can also prevent MSi in the 2nd heat treatment of step S5a except obtaining the effect of above-mentioned embodiment 3 2From metal silicide layer 41a, 41b to groove misgrowth.So, can further improve the Performance And Reliability of semiconductor device.
In addition, in the present embodiment 4, carry out the 1st heat treatment step of step S3a, carry out the wet clean process operation of step S4 then, next pass through step S11 on Semiconductor substrate 1, comprise that metal silicide layer 41a go up to form barrier film 13a, before forming barrier film 13a, can carry out and the identical dry type clean of dry type clean (corresponding to the operation P2 of above-mentioned Figure 11) of carrying out before at step S1 (metal film 12 formation operations).Form barrier film 13a under the state of natural oxide film if having on the surface of metal silicide layer 41a, carry out the 2nd heat treatment of step S5a, then the oxygen that contains in the natural oxide film is ingested among metal silicide layer 41a, the 41b.If under this state, carry out the 2nd heat treatment of step S5a, unfavorable conditions such as the resistance value that metal silicide layer 41b then might take place uprises, the uneven increase of resistance value.Therefore, preferably before the formation barrier film 13a of step S11, remove the natural oxide film on the surface of metal silicide layer 41a.So, can after carrying out the wet clean process operation of step S4, carry out dry type clean operation (operation on the surface of dry type clean metal silicide layer 41a), under the state of having removed natural oxide film, carry out the deposition procedures of the barrier film 13a of step S11.This but under the situation of above-mentioned embodiment 2, replaces with step S3 and step S5 with step S3a and step S5a for above-mentioned embodiment 2 too, and metal silicide layer 41a and metal silicide layer 41b are replaced with metal silicide layer 41.
Also can be in the deposition procedures of the barrier film 13a of step S11, form the Ti film in the lower floor of barrier film 13a.The Ti film has the character of easy picked-up oxygen, so after the wet clean process of step S4, even form natural oxide film on the surface of metal silicide layer 41a, also can absorb the oxygen that contains in this natural oxide film by the Ti film and remove natural oxide film.So, in the deposition procedures of the barrier film 13a of step S11, can comprise on the metal silicide layer 41a at first on Semiconductor substrate 1 that depositing Ti film (titanium film) deposits barrier film 13a (preferred in such cases titanium nitride (TiN) film) then.Need to prove, can between the deposition procedures of the barrier film 13a of the wet clean process operation of above-mentioned step S4 and step S11, carry out above-mentioned dry type clean operation, again at barrier film 13a lower floor deposition titanium film.When the lower floor of barrier film 13a was provided with the Ti film, this Ti film also can be considered as the part of barrier film 13a, so barrier film 13a can be considered as being made of the laminate film of the titanium of lower floor (Ti) film and titanium nitride (TiN) film on it.Thus, the wet clean process operation of the 1st heat treatment step and step S4 by step S3a can positively be removed and is formed at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b, p +The natural oxide film on the surface of the metal silicide layer 41a on the surface of N-type semiconductor N zone 10b, and then unfavorable conditions such as the resistance value that can prevent the metal silicide layer 41b that the 2nd heat treatment by step S5a forms uprises, the uneven increase of resistance value.This also is identical for above-mentioned embodiment 2, but under the situation of above-mentioned embodiment 2, step S3a and step S5a is replaced with step S3 and step S5, and metal silicide layer 41a and metal silicide layer 41b are replaced with metal silicide layer 41.
(embodiment 5)
As described below, the present embodiment be the 2nd heat treated heat treatment temperature with step S5a in the manufacturing process of above-mentioned embodiment 3 be set at the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with ceiling temperature.
Figure 53 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment, corresponding to Fig. 9 of above-mentioned embodiment 1 or Figure 36 of above-mentioned embodiment 3.Figure 53 represents to obtain to utilize the self-aligned silicide treatment process at gate electrode 8a, 8b, n after the structure of above-mentioned Fig. 7 +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b forms the manufacturing process flow of the operation of metal silicide layer (metal semiconductor conversion zone).Figure 54～Figure 56 is the major part profile in the manufacturing process of semiconductor device of the present embodiment.
The manufacturing process of the semiconductor device of the present embodiment is to identical with above-mentioned embodiment 3 by carrying out operation that wet clean process removes barrier film 13 and unreacted metal film 12 in above-mentioned steps S4, so, here omit its explanation, the operation after the above-mentioned steps S4 is described.
Proceed to the operation (being step S1, S2, S3a, S4) of above-mentioned steps S4 in the same manner with above-mentioned embodiment 3, obtain the structure of Figure 54 roughly suitable with above-mentioned Figure 37.Then, Semiconductor substrate 1 is carried out the 2nd heat treatment (the step S5b of Figure 53).The 2nd heat treatment of step S5b is equivalent to the 2nd heat treatment of the step S5a of above-mentioned embodiment 3, have with the 2nd heat treatment phase of the step S5a of above-mentioned embodiment 3 with effect.
Same with the 2nd heat treatment phase of above-mentioned steps S5a, the 2nd heat treatment of step S5b preferably is being full of inert gas (for example Ar gas or He gas) or N 2In the environment of gas atmosphere, under normal pressure, carry out.
The 2nd heat treatment of step S5b is carried out under the heat treatment temperature of the 1st heat treated heat treatment temperature that is higher than above-mentioned steps S3a.By carrying out the 2nd heat treatment of step S5b, shown in Figure 55, the M that in the 1st heat treatment of step S3a, forms 2The metal silicide layer 41a of Si phase becomes the metal silicide layer 41b of MSi phase, and the ratio of components of metallic element M and Si more near 1: 1, can form stable metal silicide layer 41b in stoichiometric proportion.Need to prove that the resistivity of MSi phase is lower than M 2Si reaches MSi mutually 2Phase, in the later operation of step S5b (manufacturing to semiconductor device finishes), metal silicide layer 41b also keeps low-resistance MSi phase, in the semiconductor device of making (even for example Semiconductor substrate 1 being become under the state of semiconductor chip independently), metal silicide layer 41b is low-resistance MSi phase.
The M identical with above-mentioned embodiment 3, that the present embodiment forms in the 1st heat treatment by step S3a 2Among the metal silicide layer 41a of Si phase, be formed at n +The thickness of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 9b is also less than being formed at p +The thickness of the lip-deep metal silicide layer 41a of N-type semiconductor N zone 10b.Therefore, identical with above-mentioned embodiment 3, among the metal silicide layer 41b of the MSi phase that the 2nd heat treatment by step S5b in the present embodiment forms, p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is also less than n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.
As the explanation in above-mentioned embodiment 3, with respect to n +N-type semiconductor N zone 9b, metallic element M is easily to p +10b diffusion in N-type semiconductor N zone promotes the reaction of metallic element M and Si easily, so, and be formed at n +The metal silicide layer 41b of the lip-deep MSi phase of N-type semiconductor N zone 9b compares MSi 2Part is being formed at p easily +Generate among the metal silicide layer 41b of the lip-deep MSi phase of N-type semiconductor N zone 10b, thus misgrowth.In order to overcome above-mentioned situation, in above-mentioned embodiment 3 and the present embodiment 5, make to be formed at p +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b is less than being formed at n +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.
But more hope suppresses the misgrowth (MSi of metal silicide layer 41b as far as possible 2The part local growth).With the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with, in the 2nd heat treatment of the step S5b of the present embodiment, if the lattice size of Semiconductor substrate 1 is near MSi 2The lattice size, then also replace easily between the lattice of metallic element M and Si, thus by the 2nd heat treatment make metallic element M easily from metal silicide layer 41a, 41b to semiconductor substrate region (p for example +N-type semiconductor N zone 10b, n +N-type semiconductor N zone 9b) diffusion, MSi 2Part misgrowth easily.
Therefore, the 2nd heat treatment of the step S5b of the present embodiment with the upper limit of heat treatment temperature be set at above-mentioned embodiment 1 in step S5 the 2nd heat treatment phase with, further suppress the misgrowth (MSi of metal silicide layer 41b thus 2The local growth of part).
That is, with the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with, in the present embodiment, also make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than MSi 2Lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 3(T 12＜T 3).When the 2nd heat treatment of carrying out step S5b, do not become Semiconductor substrate 1 and MSi thus 2Lattice state of the same size.The 2nd heat treatment that can further positively suppress or prevent step S5b thus causes metal silicide layer 41a, 41b misgrowth (MSi 2The part local growth), its reason with in the 2nd heat treatment of the step S5 of above-mentioned embodiment 1, can prevent MSi 2Misgrowth roughly the same.
Therefore, with the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with, in the present embodiment, be monocrystalline silicon (Si) substrate and metal film 12 when being the Ni film for example in Semiconductor substrate 1, also make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than monocrystalline silicon (Si) and NiSi 2Lattice said temperature T of the same size 4(T 4=590 ℃) (T 12＜T 4=590 ℃).In addition, be monocrystalline silicon (Si) substrate and metal film 12 during for example for the Ni-Pt alloy film in Semiconductor substrate 1, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than monocrystalline silicon (Si) and Ni 1-xPt xSi 2Lattice said temperature T of the same size 5(T 12＜T 5).Be Ni for example at metal film 12 1-xPd xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than Ni 1-xPd xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.For example, be Ni at metal film 12 1-xYb xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than Ni 1-xYb xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.For example, metal film 12 is Ni 1-xEr xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than Ni 1-xEr xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Be Ni for example at metal film 12 1-xY xDuring alloy film, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than Ni 1-xY xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.Be Ni for example at metal film 12 1-xLn xAlloy film (Ln herein: in the time of lanthanide series), make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than Ni 1- xLn xSi 2Lattice size and the lattice temperature of the same size of Semiconductor substrate 1.
As mentioned above, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5b at least 12Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (being that above-mentioned mismatch α is 0%) of Semiconductor substrate 1 3(T 12＜T 3).And, identical with the step S5 of above-mentioned embodiment 1, in the present embodiment, more preferably make the 2nd heat treated heat treatment temperature T of step S5b 12The time MSi 2Lattice size and poor (absolute value) of the lattice size of Semiconductor substrate 1 be more than 0.01% of lattice size of Semiconductor substrate 1 (being α 〉=0.01%), more preferably more than 0.02% of the lattice size of Semiconductor substrate 1 (being α 〉=0.02%).Need to prove that the definition of mismatch α is also identical with above-mentioned embodiment 1 in the present embodiment.
Therefore, with the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with, also the 2nd of preferred steps S5b the heat treated heat treatment temperature T in the present embodiment 12The time above-mentioned mismatch α greater than 0% (α＞0%), more preferably be (α 〉=0.01%) more than 0.01%, more preferably (α 〉=0.02%) more than 0.02%.In other words, the 2nd of step S5b the heat treated heat treatment temperature T 12More preferably be that above-mentioned mismatch α is 0.01% said temperature T 6Below (T 12≤ T 6), more preferably above-mentioned mismatch α is 0.02% said temperature T 7Below (T 12≤ T 7).In the 2nd heat treatment of step S5b, be in the lattice size and the MSi of Semiconductor substrate 1 thus 2The difference of lattice size be a certain degree than the big difference state, so can more positively prevent metal silicide layer 41a, 41b misgrowth (MSi 2The part local growth).In addition, as mentioned above, be monocrystalline silicon (Si) substrate and metal film 12 during for example for nickel (Ni) film in Semiconductor substrate 1, when promptly metal silicide layer 41b was nickel silicide (NiSi) layer, above-mentioned mismatch α was 0.01% temperature T 6Be about 575 ℃ of (T 6=575 ℃), above-mentioned mismatch α is 0.02% temperature T 7Be about 560 ℃ of (T 7=560 ℃).
Carrying out the 2nd heat treatment of step S5b, (is n at gate electrode 8a and the source drain of n channel-type MISFETQn here +N-type semiconductor N zone 9b) surface and gate electrode 8b and the source drain of p channel-type MISFETQp (are p here +N-type semiconductor N zone 10b) after surface forms the metal silicide layer 41b of MSi phase, carries out the operation identical with above-mentioned embodiment 1,3.
Promptly, identical with above-mentioned embodiment 1,3, shown in Figure 56, form dielectric film 42 and dielectric film 43, on dielectric film 43,42, form contact hole 44, in contact hole 44, form embolism 45, at landfill form to stop dielectric film 51 and dielectric film 52 on the dielectric film 43 of embolism 45, form wiring trench 53, in wiring trench 53, imbed insulated conductor film 54 and copper film, form wiring 55.
In the present embodiment, in the various heating processes (film formation process of for example various dielectric films or electrically conductive film and so on is followed the operation of the heating of Semiconductor substrate 1) after the 2nd heat treatment of the step S5b of Figure 53, also make the temperature of Semiconductor substrate 1 not be higher than the 2nd heat treated heat treatment temperature T of step S5b 12Can prevent that thus the heating (film formation process of for example various dielectric films and electrically conductive film) in the step S5b operation afterwards from making the metallic element M that constitutes metal silicide layer (MSi mutually) 41b be diffused into Semiconductor substrate 1 ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) in, causes the characteristic variations of n channel-type MISFETQn and p channel-type MISFETQp.
In the present embodiment, except the effect that can obtain above-mentioned embodiment 3, also with the 2nd heat treated heat treatment temperature T of step S5b 12The upper limit be set at above-mentioned embodiment 1 in step S5 the 2nd heat treatment phase with.That is, in the present embodiment, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (being that above-mentioned mismatch α is 0%) of Semiconductor substrate 1 3(T 12＜T 3), more preferably be that above-mentioned mismatch α is 0.01% temperature T 6Below (T 12≤ T 6), more preferably above-mentioned mismatch α is 0.02% temperature T 7Below (T 12≤ T 7).The effect of above-mentioned embodiment 3 can be obtained thus, and n can be further positively prevented to be formed at +Reach p on the surface of N-type semiconductor N zone 9b +Misgrowth (the MSi of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b 2The part local growth), can further reduce n +N-type semiconductor N zone 9b and p +Junction leakage among the 10b of N-type semiconductor N zone also can further reduce the inequality of junction leakage.So can further improve the reliability or the performance of semiconductor device.
(embodiment 6)
The present embodiment is as described below, is in the manufacturing process of above-mentioned embodiment 4, the 2nd heat treated heat treatment temperature of step S5a is set at identical with the 2nd heat treated ceiling temperature of the step S5 of above-mentioned embodiment 1.
Figure 57 is the manufacturing process flow diagram of a part of the semiconductor device manufacturing process of expression the present embodiment, corresponding to Figure 31 of above-mentioned embodiment 2 or Figure 48 of above-mentioned embodiment 5.Figure 57 represents to obtain to utilize the self-aligned silicide treatment process at gate electrode 8a, 8b, n after the structure of above-mentioned Fig. 7 +N-type semiconductor N zone 9b and p +The surface of N-type semiconductor N zone 10b forms the manufacturing process flow of the operation of metal silicide layer (metal semiconductor conversion zone).Figure 58～Figure 60 is the major part profile in the manufacturing process of semiconductor device of the present embodiment.
The manufacturing process of the semiconductor device of the present embodiment is identical with above-mentioned embodiment 4 to the operation that forms barrier film 13a in above-mentioned steps S11, omits its explanation here, and above-mentioned steps S11 operation is afterwards described.
Proceed to the operation (being step S1, S2, S3a, S4, S11) of above-mentioned steps S11 in the same manner with above-mentioned embodiment 4, obtain the structure of Figure 58 roughly suitable with above-mentioned Figure 50.Then, to 2nd heat treatment phase together 2nd heat treatment (the step S5b of Figure 57) of Semiconductor substrate 1 enforcement with the step S5b of above-mentioned embodiment 5.
In the present embodiment 6, the 2nd heat treatment of step S5b is carried out under the state that forms barrier film 13a, but the 2nd heat treated condition (comprising ceiling temperature) of step S5b and effect are identical with above-mentioned embodiment 5, so omission repeat specification.
Identical with above-mentioned embodiment 5, in the present embodiment 6, also, make the M that forms in the 1st heat treatment of step S3a by carrying out the 2nd heat treatment of step S5b 2The metal silicide layer 41a of Si phase becomes the metal silicide layer 41b of MSi phase, and the ratio of components that makes metallic element M and Si more near 1: 1, forms low resistance and stable metal silicide layer 41b in stoichiometric proportion.In addition, identical with above-mentioned embodiment 5, in the present embodiment 6, the p after the 2nd heat treatment of step S5b +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 10b also is lower than the n after the 2nd heat treatment of step S5a +The thickness of the lip-deep metal silicide layer 41b of N-type semiconductor N zone 9b.Need to prove that the resistivity of MSi phase is lower than M 2Si reaches MSi mutually 2Phase, and in the later operation of step S5b (manufacturing to semiconductor device finishes), metal silicide layer 41b also keeps low-resistance MSi phase, in the semiconductor device of making (even for example Semiconductor substrate 1 being become under the state of semiconductor chip independently), metal silicide layer 41b also becomes low-resistance MSi phase.
Barrier film 13a be difficult to metal silicide layer 41a, 41b the reaction film, even carry out the 2nd heat treatment of step S5b, do not react with metal silicide layer 41a, 41b yet.If barrier film 13a and metal silicide layer 41a, 41b react in the 2nd heat treatment of step S5b, then might change the composition of metal silicide layer 41b.Therefore, identical with above-mentioned embodiment 2,4, in the present embodiment, also can by make barrier film 13a be difficult to metal silicide layer 41a, 41b the reaction film, prevent metal silicide layer 41a, 41b and barrier film 13a reaction in the 2nd heat treatment of step S5b, thereby can positively form metal silicide layer 41b.As the above-mentioned barrier film 13a that is difficult to metal silicide layer 41a, 41b reaction, preferred titanium nitride (TiN) film or titanium (Ti) film.
After the 2nd heat treatment of step S5b, identical with above-mentioned embodiment 4, shown in Figure 59, in the present embodiment,, remove barrier film 13a (the step S12 of Figure 57) also by carrying out wet clean process etc.At this moment, at gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p + Kish silicide layer 41b on the surface of N-type semiconductor N zone 10b.The barrier film 13a of above-mentioned steps S12 in the present embodiment removes operation and can remove operation with the barrier film 13a of step S12 in the above-mentioned embodiment 2,4 and carry out in the same manner.
Later operation is identical with above-mentioned embodiment 4.Promptly, identical with above-mentioned embodiment 4, shown in Figure 60, form dielectric film 42 and dielectric film 43, on dielectric film 43,42, form contact hole 44, in contact hole 44, form embolism 45, at landfill form to stop dielectric film 51 and dielectric film 52 on the dielectric film 43 of embolism 45, form wiring trench 53, in wiring trench 53, imbed insulated conductor film 54 and copper film, form wiring 55.
In the present embodiment, also make the temperature of the Semiconductor substrate 1 in the various heating processes (film formation process of for example various dielectric films or electrically conductive film and so on is followed the operation of the heating of Semiconductor substrate 1) after the 2nd heat treatment of step S5b of Figure 57 not be higher than the 2nd heat treated heat treatment temperature T of step S5b 12Thus, can prevent that the heating (film formation process of for example various dielectric films or electrically conductive film) in the step S5b operation afterwards from making the metallic element M that constitutes metal silicide layer (MSi phase) 41b be diffused into Semiconductor substrate 1 ( gate electrode 8a, 8b, n +N-type semiconductor N zone 9b and p +N-type semiconductor N zone 10b) in, causes the characteristic variations of n channel-type MISFETQn and p channel-type MISFETQp.
Identical with above-mentioned embodiment 5, in the present embodiment also with the 2nd heat treated heat treatment temperature T of step S5b 12The upper limit be set at the 2nd heat treatment phase of the step S5 of above-mentioned embodiment 1 with.That is, make the 2nd heat treated heat treatment temperature T of step S5b 12Be lower than MSi 2Lattice size and the temperature T of the lattice big or small consistent (being that above-mentioned mismatch α is 0%) of Semiconductor substrate 1 3(T 12＜T 3), more preferably be that above-mentioned mismatch α is 0.01% temperature T 6Below (T 12≤ T 6), more preferably above-mentioned mismatch α is 0.02% temperature T 7Below (T 12≤ T 7).Thus, the effect of above-mentioned embodiment 4 can be obtained, and the misgrowth (MSi of metal silicide layer 41b can be more positively prevented 2The part local growth), can further reduce n +N-type semiconductor N zone 9b and p +Junction leakage among the 10b of N-type semiconductor N zone can also further reduce the inequality of junction leakage.Can also further improve MSi in the 2nd heat treatment that prevents step S5b 2From metal silicide layer 41a, 41b to the excrescent effect of groove.Therefore, can further improve the reliability and the performance of semiconductor device.
Identical with above-mentioned embodiment 1,2, the present embodiment and above-mentioned embodiment 5 are lower than MSi by the 2nd heat treated heat treatment temperature that makes step S5b 2Lattice size and the lattice temperature T of the same size of Semiconductor substrate 1 3, prevent the misgrowth (MSi of metal silicide layer 41b 2The part local growth).Therefore, identical with above-mentioned embodiment 1,2, by there being MSi 2Be suitable for the present embodiment and above-mentioned embodiment 5 when the silicide of phase forms metal silicide layer 41a, 41b, effect is also remarkable.In addition, identical with above-mentioned embodiment 1,2, at the crystalline texture and the MSi of Semiconductor substrate 1 2The similitude of crystalline texture when high, particularly the crystalline texture in Semiconductor substrate 1 is diamond lattic structure, MSi 2Crystalline texture when being fluorite structure, be suitable for the present embodiment and above-mentioned embodiment 5, effect is also remarkable.
Therefore, identical with above-mentioned embodiment 1,2, be suitable for the present embodiment and above-mentioned embodiment 5 when using Ni film or Ni alloy film (the preferred Ni-Pt alloy film of Ni alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film) as metal film 12, effect is also remarkable.In addition, identical with above-mentioned embodiment 1,2, the present embodiment and above-mentioned embodiment 5 also most preferably use monocrystalline silicon as Semiconductor substrate 1, but it is as long as identical with monocrystalline silicon, crystalline texture with diamond lattic structure type gets final product, even the material beyond the monocrystalline silicon also can be preferably used as Semiconductor substrate 1.
More than based on embodiment the invention that the inventor finished is specifically described, certainly, the present invention is not limited to above-mentioned embodiment, can carry out various changes in the scope that does not break away from its aim.
Utilizability on the industry
The present invention is applicable to effectively is equipped with half of semiconductor element with metal silicide layer The manufacturing technology of conductor device.

Claims (49)

1, a kind of manufacture method of semiconductor device comprises following operation:
(a) operation of preparation Semiconductor substrate,
(b) operation of formation semiconductor regions on described Semiconductor substrate,
(c) operation of formation metal film on the described Semiconductor substrate that comprises on the described semiconductor regions,
(d) carry out the 1st heat treatment and make described metal film and the reaction of described semiconductor regions, form the operation of the metal silicide layer of forming by single silicide of the metallic element that constitutes described metal film,
(e) after described (d) operation, remove unreacted described metal film, the operation of residual described metal silicide layer on described semiconductor regions,
(f) after described (e) operation, heat-treat temperature and be higher than the described the 1st the heat treated the 2nd heat treated operation,
(g) after described (f) operation, on the described Semiconductor substrate that comprises on the described metal silicide layer, form the operation of dielectric film,
It is characterized in that the described the 2nd heat treated heat treatment temperature of described (f) operation is lower than lattice the 1st temperature of the same size of lattice size and described Semiconductor substrate of the disilicide of the described metallic element that constitutes described metal film.
2, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described metal film is Ni film or Ni alloy film.
3, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described metal film is Ni film, Ni-Pt alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film.
4, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, after described (f) operation, does not make the temperature of described Semiconductor substrate be higher than the processing of described the 2nd heat treated heat treatment temperature.
5, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described metal film is the Ni film, and described the 1st temperature is 590 ℃.
6, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the resistivity of single silicide phase that constitutes the described metallic element of described metal film is lower than the disilicide phase of the described metallic element that constitutes described metal film,
After described the 2nd heat treatment of described (f) operation, described metal silicide layer still is single silicide phase of described metallic element.
7, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, carries out described the 2nd heat treatment for the stabilisation of described metal silicide layer.
8, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described Semiconductor substrate is made of material.
9, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the crystalline texture of described Semiconductor substrate is diamond lattic structure, and the crystalline texture of the disilicide of described metallic element is fluorite structure.
10, the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that the lattice of the disilicide of described metallic element size is more than 0.01% of lattice size of described Semiconductor substrate with the difference of the lattice size of described Semiconductor substrate under the described the 2nd heat treated heat treatment temperature.
11, the manufacture method of semiconductor device as claimed in claim 1, it is characterized in that the lattice of the disilicide of described metallic element size is more than 0.02% of lattice size of described Semiconductor substrate with the difference of the lattice size of described Semiconductor substrate under the described the 2nd heat treated heat treatment temperature.
12, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described (f) operation is to carry out described the 2nd heat treatment in inert gas or nitrogen atmosphere.
13, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, described semiconductor regions is source electrode or drain electrode semiconductor regions.
14, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that, also has following operation after described (a) operation:
(a1) operation of formation gate insulating film on described Semiconductor substrate,
(a2) operation of formation gate electrode on described gate insulating film,
In described (c) operation, on the described Semiconductor substrate that comprises on the described semiconductor regions, form described metal film, cover described gate electrode.
15, the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, after described (c) operation, before described (d) operation, also has (c1) forms the 1st barrier film on described metal film operation,
In described (e) operation, remove described the 1st barrier film and unreacted described metal film.
16, the manufacture method of semiconductor device as claimed in claim 15 is characterized in that, described the 1st barrier film is to make described Semiconductor substrate produce the film of tensile stress.
17, the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, though described the 1st barrier film be carry out described the 1st heat treatment also not with the film of described metal film reaction.
18, the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, also has the operation on surface that (c2) dry type is cleaned the described semiconductor regions of described Semiconductor substrate interarea before described (c) operation,
After described (c2) operation, described Semiconductor substrate is not placed atmosphere, but carry out described (c) operation and described (c1) operation.
19, the manufacture method of semiconductor device as claimed in claim 16 is characterized in that, also has following operation after described (a) operation:
(a3) on described Semiconductor substrate, form element and separate the operation of using ditch,
(a4) form by being embedded in the operation that described element separates the element separated region that forms with the insulator in the ditch,
The described element separated region that forms in described (a4) operation has the effect that makes described Semiconductor substrate produce compression,
In active region, form described semiconductor regions by described element separated region regulation.
20, the manufacture method of semiconductor device as claimed in claim 15, it is characterized in that, after described (e) operation, before described (f) operation, also has (e1) forms the 2nd barrier film on the described Semiconductor substrate that comprises on the described metal silicide layer operation
After described (f) operation, before described (g) operation, also has the operation that (f1) removes described the 2nd barrier film.
21, the manufacture method of semiconductor device as claimed in claim 20 is characterized in that, described the 1st barrier film and described the 2nd barrier film are to make described Semiconductor substrate produce the film of tensile stress.
22, a kind of manufacture method of semiconductor device comprises following operation:
(a) operation of preparation Semiconductor substrate,
(b) form the element separated region on described Semiconductor substrate, regulation forms the active region of n channel type field effect transistors and forms the operation of the active region of p channel type field effect transistors,
(c) operation of the gate insulating film of the gate insulating film of the described n channel type field effect transistors of formation and described p channel type field effect transistors on described Semiconductor substrate,
(d) on the gate insulating film of described n channel type field effect transistors and form the operation of gate electrode on the gate insulating film of described p channel type field effect transistors respectively,
(e) on described Semiconductor substrate, form the source electrode of described n channel type field effect transistors or drain electrode with semiconductor regions, and the source electrode of described p channel type field effect transistors or drain electrode with the operation of semiconductor regions,
(f) on gate electrode that comprises described n channel type field effect transistors and the semiconductor regions, and the gate electrode of described p channel type field effect transistors and the described Semiconductor substrate on the semiconductor regions on form the operation of metal film,
(g) operation of formation the 1st barrier film on described metal film,
(h) carrying out the 1st heat treatment makes the gate electrode or the semiconductor regions of described metal film and described n channel type field effect transistors and makes described metal film and the gate electrode of described p channel type field effect transistors or semiconductor regions reaction, form the operation of metal silicide layer
(i) after described (h) operation, remove described the 1st barrier film and constitute the metallic element of described metal film, operation at residual described metal silicide layer on the surface of the gate electrode of described n channel type field effect transistors or semiconductor regions and on the surface of the gate electrode of described p channel type field effect transistors or semiconductor regions
(j) carry out the 2nd heat treated operation,
It is characterized in that, in described (h) operation, in the temperature range of the reactivity of the described metal film the when reactivity of the described metal film when the semiconductor regions reaction that makes described metal film and described p channel type field effect transistors is lower than the semiconductor regions reaction that makes described metal film and described n channel type field effect transistors, carry out described the 1st heat treatment.
23, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that, in described (h) operation, the thickness of lip-deep described metal silicide layer of semiconductor regions that is formed at described p channel type field effect transistors is less than the thickness of the lip-deep described metal silicide layer of the semiconductor regions that is formed at described n channel type field effect transistors.
24, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that, in described (j) operation, the thickness of lip-deep described metal silicide layer of semiconductor regions that is formed at described p channel type field effect transistors is less than the thickness of the lip-deep described metal silicide layer of the semiconductor regions that is formed at described n channel type field effect transistors.
25, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that, in described (h) operation, when the semiconductor regions reaction of described metal film and described p channel type field effect transistors, described metal film is by full consumption, the metallic element of the described metal film of formation of remained unreacted on the lip-deep described metal silicide layer of the semiconductor regions that is formed at described p channel type field effect transistors.
26, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, the described the 2nd heat treated temperature of described (j) operation is higher than the described the 1st heat treated temperature of described (h) operation.
27, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, the described metal silicide layer that forms in described (h) operation is made up of two metal silicides of the metallic element that constitutes described metal film,
By described the 2nd heat treatment of described (j) operation, described metal silicide layer becomes the metal silicide layer that the metal list silicide by the described metallic element that constitutes described metal film constitutes.
28, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, described metal film is Ni film, Ni alloy film or Pt film.
29, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that described metal film is Ni film, Ni-Pt alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film, Ni-lanthanide series alloy film or Pt film.
30, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, the described metal silicide layer that forms in described (h) operation is formed by comparing the silicide that more is rich in metal with two metal silicides of the metallic element that constitutes described metal film,
By described the 2nd heat treatment of described (j) operation, described metal silicide layer becomes the metal silicide layer of being made up of two metal silicides of the described metallic element that constitutes described metal film.
31, the manufacture method of semiconductor device as claimed in claim 30 is characterized in that, described metal film is the Pt film.
32, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, described metal film is the Ni film.
33, the manufacture method of semiconductor device as claimed in claim 32 is characterized in that, the described the 1st heat treated temperature of described (h) operation is more than 260 ℃, is lower than 320 ℃.
34, the manufacture method of semiconductor device as claimed in claim 32 is characterized in that, the thickness of the described metal film that forms in described (f) operation is 4nm～33nm.
35, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, though described the 1st barrier film be carry out described the 1st heat treatment also not with the film of described metal silicide layer reaction.
36, the manufacture method of semiconductor device as claimed in claim 22 is characterized in that, described the 1st barrier film is Ti film or TiN film.
37, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that, before described (f) operation, also have (f1) dry type and clean the surface of the gate electrode of described n channel type field effect transistors or semiconductor regions, and the operation on the surface of the gate electrode of described p channel type field effect transistors or semiconductor regions
After described (f1) operation, described Semiconductor substrate is not placed atmosphere, but carry out described (f) operation and described (g) operation.
38, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that, after described (i) operation, before described (j) operation, also has (j1) forms the 2nd barrier film on the described Semiconductor substrate that comprises on the described metal silicide layer operation
After described (j) operation, also has the operation that (j2) removes described the 2nd barrier film.
39, the manufacture method of semiconductor device as claimed in claim 38 is characterized in that, though described the 2nd barrier film be carry out described the 2nd heat treatment also not with the film of described metal silicide layer reaction.
40, the manufacture method of semiconductor device as claimed in claim 38 is characterized in that, described the 2nd barrier film is the TiN film or is the Ti film of lower floor and the laminate film of TiN film with the Ti film.
41, the manufacture method of semiconductor device as claimed in claim 38 is characterized in that, after described (i) operation, before described (j1) operation, also has the operation that (j3) dry type is cleaned the surface of described metal silicide layer.
42, the manufacture method of semiconductor device as claimed in claim 22, it is characterized in that the described the 2nd heat treated heat treatment temperature of described (j) operation is lower than lattice the 1st temperature of the same size of lattice size and described Semiconductor substrate of the disilicide of the described metallic element that constitutes described metal film.
43, the manufacture method of semiconductor device as claimed in claim 42 is characterized in that, the crystalline texture of described Semiconductor substrate is diamond lattic structure, and the crystalline texture of the disilicide of described metallic element is fluorite structure.
44, the manufacture method of semiconductor device as claimed in claim 43, it is characterized in that, under the described the 2nd heat treated heat treatment temperature, the difference of the lattice size of the lattice of the disilicide of described metallic element size and described Semiconductor substrate is more than 0.01% of lattice size of described Semiconductor substrate.
45, the manufacture method of semiconductor device as claimed in claim 44, it is characterized in that, under the described the 2nd heat treated heat treatment temperature, the difference of the lattice size of the lattice of the disilicide of described metallic element size and described Semiconductor substrate is more than 0.02% of lattice size of described Semiconductor substrate.
46, the manufacture method of semiconductor device as claimed in claim 42 is characterized in that, after described (j) operation, does not make the temperature of described Semiconductor substrate be higher than the processing of described the 2nd heat treated heat treatment temperature.
47, the manufacture method of semiconductor device as claimed in claim 42 is characterized in that, described metal film is Ni film, Ni-Pt alloy film, Ni-Pd alloy film, Ni-Y alloy film, Ni-Yb alloy film, Ni-Er alloy film or Ni-lanthanide series alloy film.
48, the manufacture method of semiconductor device as claimed in claim 47 is characterized in that, the resistivity of single silicide phase that constitutes the described metallic element of described metal film is lower than the disilicide phase of the described metallic element that constitutes described metal film,
After described the 2nd heat treatment of described (j) operation, described metal silicide layer still is single silicide phase of described metallic element.
49, the manufacture method of semiconductor device as claimed in claim 48, it is characterized in that, after described (i) operation, before described (j) operation, also has (j1) forms the 2nd barrier film on the described Semiconductor substrate that comprises on the described metal silicide layer operation
After described (j) operation, also has the operation that (j2) removes described the 2nd barrier film.
CN2008101096472A 2007-07-03 2008-06-11 Method of manufacturing semiconductor device Active CN101339904B (en)

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CN104900516A (en) * 2015-06-29 2015-09-09 上海华力微电子有限公司 Method for forming nickel silicide
CN106257672A (en) * 2015-06-18 2016-12-28 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device, semiconductor device and electronic installation
TWI570281B (en) * 2011-09-29 2017-02-11 瑞薩電子股份有限公司 A method for manufacturing a semiconductor device
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JP2002016018A (en) * 2000-06-30 2002-01-18 Sumitomo Heavy Ind Ltd Device and method for treating substrate
JP4011434B2 (en) * 2002-08-15 2007-11-21 富士通株式会社 Semiconductor device manufacturing method and semiconductor device
KR100558006B1 (en) * 2003-11-17 2006-03-06 삼성전자주식회사 Nickel salicide processes and methods of fabricating semiconductor devices using the same
JP2006100338A (en) * 2004-09-28 2006-04-13 Matsushita Electric Ind Co Ltd Method for forming dielectric thin film
JP2007035740A (en) * 2005-07-25 2007-02-08 Tokyo Electron Ltd Film deposition method, film deposition equipment, and storage medium

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TWI570281B (en) * 2011-09-29 2017-02-11 瑞薩電子股份有限公司 A method for manufacturing a semiconductor device
CN103137462A (en) * 2011-11-25 2013-06-05 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned metal silicide
CN103137462B (en) * 2011-11-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 The formation method of self-aligned metal silicate
CN106257672A (en) * 2015-06-18 2016-12-28 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device, semiconductor device and electronic installation
CN104900516A (en) * 2015-06-29 2015-09-09 上海华力微电子有限公司 Method for forming nickel silicide
CN104900516B (en) * 2015-06-29 2018-01-26 上海华力微电子有限公司 A kind of forming method of nickel silicide
CN109962112A (en) * 2019-03-26 2019-07-02 湘潭大学 A kind of ferroelectricity grid field effect transistor and preparation method thereof
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CN117613003B (en) * 2024-01-23 2024-04-16 合肥晶合集成电路股份有限公司 Method for manufacturing semiconductor device and semiconductor device

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