CN103137462A - Method for forming self-aligned metal silicide - Google Patents
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- CN103137462A CN103137462A CN2011103831499A CN201110383149A CN103137462A CN 103137462 A CN103137462 A CN 103137462A CN 2011103831499 A CN2011103831499 A CN 2011103831499A CN 201110383149 A CN201110383149 A CN 201110383149A CN 103137462 A CN103137462 A CN 103137462A
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Abstract
The invention relates to a method for forming self-aligned metal silicide. The method comprises the following steps of: providing a semiconductor substrate, wherein at least one silicon region is formed on the surface of the semiconductor substrate; forming an ion-implanted region on the silicon region; forming a silicon epitaxial layer which covers the surface of the ion-implanted region; forming a nickel metal layer which covers the silicon epitaxial layer; forming a first metal silicide layer on the surface of the silicon region and in the silicon epitaxial layer by a first annealing process; removing the unreacted nickel metal layer; and annealing the first metal silicide layer by a second annealing process to form a second metal silicide layer. The metal silicide layers formed by the method in the embodiment of the invention are high in quality, and the electric properties of a device are high.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the formation method of self-aligned metal silicate.
Background technology
In semiconductor fabrication, metal silicide due to have lower resistivity and and other materials have that good adhesiveness is widely used in source/drain contact and gate contact reduces contact resistance.Dystectic metal and the silicon generation metal silicide that reacts, can form the metal silicide of low-resistivity by a step or multistep annealing process.Along with the raising of semiconductor process technology, particularly at 90nm and following technology node thereof, in order to obtain lower contact resistance, the alloy of nickel and nickel becomes the main material that forms metal silicide.
Disclose a kind of formation method of self-aligned metal silicate in the U.S. Patent application that disclosed publication number is US2009309228A1, the method selects nickel alloy as the material that forms metal silicide.Fig. 1 to Fig. 3 has provided the cross-sectional view in the method formation each stage of self-aligned silicide.
As shown in Figure 1, at first provide semiconductor base 100, described semiconductor base 100 is formed with isolated area 110, in described isolated area 110, is filled with insulating material; Be formed with gate dielectric layer 104 on semiconductor base 100; Be formed with gate electrode 103 on described gate dielectric layer 104, in the both sides of described gate electrode 103 and gate dielectric layer 104, be formed with side wall 105, be formed with source electrode 101 and drain electrode 102 in described gate electrode 103 both sides semiconductor bases 100.
As shown in Figure 2, at the forming metal layer on surface 106 of described semiconductor base 100, described metal level 106 covers described source electrode 101, drain 102, grid 103 and side wall 105, and the material of described metal level 106 is nickel.Further, can form protective layer 107 on metal level 106, the material of described protective layer 107 is titanium nitride (TiN), is used for preventing that metal level 106 is oxidized, and the formation of protective layer 107 is optional.
As shown in Figure 3, described semiconductor base 100 is carried out to annealing process, by annealing, described source electrode 101, drain 102, lip-deep metal level 106 materials of grid 103 and described source electrode 101, drain 102 and grid 103 in the silicon materials generation metal silicide layer that reacts, be respectively 101a, 102a, 103a.The metal level 106 that will not react by selective etch is afterwards removed, and makes metal silicide layer 101a, 102a, the 103a of formation be exposed to the surface of described semiconductor base 100.
But the metal silicide electric property that prior art forms is poor.
Summary of the invention
The problem that the present invention solves is to provide the formation method of the good and stable self-aligned metal silicate of a kind of metal silicide electric property of formation.
For addressing the above problem, the invention provides a kind of formation method of self-aligned metal silicate, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has a silicon area at least; Form ion implanted region at described silicon area; Form the silicon epitaxy layer that covers described ion implanted region surface; Form the nickel metal layer that covers described silicon epitaxy layer; Adopt the first annealing process to form the first metal silicide layer in silicon area surface and described silicon epitaxy layer; Remove unreacted nickel metal layer; Adopt the second annealing process to be annealed to the first metal silicide layer, form the second metal silicide layer.
Optionally, the ionic type of described ion implanted region injection is: H, N, F or Pt; It is perhaps two or more hybrid ionic containing H, N, F or Pt.
Optionally, the formation technique of described ion implanted region is Implantation or plasma treatment.
Optionally, the technological parameter of described Implantation formation ion implanted region is: the ion implantation energy scope is 10KeV to 32KeV, and the concentration of Implantation is 1.0E14cm
-2to 3.2E14cm
-2.
Optionally, the thickness of described ion implanted region is 10 dust to 20 dusts.
Optionally, the thickness of described silicon epitaxy layer is 50 dust to 200 dusts.
Optionally, described silicon area is that source area is or/and drain region.
Optionally, described silicon area is the gate polysilicon layer.
Optionally, described nickel metal layer material is pure nickel or nickel platinum alloy.
Optionally, when described nickel metal layer material is the nickel platinum alloy, in the nickel platinum alloy, the mass percentage content of platinum is 1% to 10%.
Optionally, described the first annealing process is for adopting rapid thermal anneler, and annealing temperature is 200 ℃ to 350 ℃, and annealing time is 0.1 minute to 2 minutes.
Optionally, described the second annealing process is for adopting rapid thermal anneler, and annealing temperature is 300 ℃ to 600 ℃, and the time is 0.1 minute to 2 minutes.
Optionally, described the second metal silicide layer material is the NiSi containing Pt.
Compared with prior art, the present invention has the following advantages:
The formation method of the self-aligned metal silicate of the embodiment of the present invention, first the silicon area at semiconductor substrate surface forms ion implanted region, then form silicon epitaxy layer on the ion implanted region surface, form the metal level containing Ni on the silicon epitaxy layer surface again, after annealing, form the metal silicide layer of platinum nickel with the silicon area surface in described silicon epitaxy layer, owing to thering is ion implanted layer, stop, and metal silicide layer is formed in described silicon epitaxy layer and the silicon area surface, therefore, metal ion can not diffuse to channel region, and the device quality of formation is high.
Further, described ion implanted region, containing the Pt ion, can form stable [Ni with the Ni that diffuses to ion implanted region
xpt
(1-x)] Si, stop that Ni spreads to channel region.
The accompanying drawing explanation
Fig. 1 to Fig. 3 is the cross-sectional view that prior art forms each stage of self-aligned silicide;
Fig. 4 is the formation method flow schematic diagram of the self-aligned metal silicate of the embodiment of the present invention;
Fig. 5 to Figure 11 is the process generalized section of formation method of the self-aligned metal silicate of one embodiment of the invention.
Embodiment
From background technology, the metal silicide electric property that prior art forms is poor, for this reason, the present inventor conducts in-depth research the metal silicide formation method of prior art, find: existing nickel metal layer and the pasc reaction of directly adopting forms metal silicide layer, metallic element in metal silicide layer is unstable, metallic element easily diffuses in substrate, make the silicon atom lattice structure of source area and drain region be upset, more badly, metallic element can diffuse under raceway groove, causes the leakage current of source electrode, drain electrode and substrate contact face.
For above-mentioned defect, the inventor further studies, find: adopt physical gas-phase deposition to carry out sputter to the target of nickel platinum alloy, thereby at described source electrode 101, drain 102, form nickel platinum alloy metal level on grid 103 surfaces, then adopt annealing process to make nickel platinum alloy metal level and pasc reaction formation [Ni
xpt
(1-x)] metal silicide layer of Si, can suppress nickel element and diffuse to substrate, thereby form stable metal silicide layer.
But the inventor furthers investigate discovery through the technique to adopting nickel platinum alloy metal level to form metal silicide layer: the interface of metal silicide layer and substrate is the environment of a Silicon-rich, and [the Ni directly formed
xpt
(1-x)] metal silicide of Si still there will be the metallic element diffusion phenomena, and the diffusion velocity of Ni and Pt is not identical, the inventor studies discovery, and Pt is because metallic atomic radius is larger, and diffusion velocity is slow, and Pt relatively, the diffusion velocity of Ni is than very fast.
Directly adopt the metal silicide layer of nickel platinum alloy metal level, the Ni of metal silicide layer and substrate interface diffuses in substrate and forms NiSi
2and metal silicide layer is due to the diffusion of Ni, thereby make the content of Pt rise, the inventor is further analyzed above-mentioned phenomenon again, finds that the resistance of metal silicide layer rate that Pt content is high is higher, the NiSi that to compare with resistivity be 15 ohm/cm, the metal silicide layer of the Pt that mass percentage content is 5% to 10% (NiSi), resistivity can rise to the 19-25 ohm/cm from 15 ohm/cm, in addition, and NiSi
2resistivity also higher than NiSi, the diffusion of Ni also can cause metal silicide layer that composition is NiSi to NiSi
2change, the Ni that adds metal silicide layer and substrate interface diffuses in substrate and forms NiSi
2thereby, make [the Ni of original setting
xpt
(1-x)] the element proportioning of metal silicide of Si is unbalance, causes device resistance to rise, hydraulic performance decline.
For this reason, the present inventor provides a kind of formation method of self-aligned metal silicate, please refer to Fig. 4, comprises the steps:
Step S101, provide Semiconductor substrate, and described semiconductor substrate surface has a silicon area at least;
Step S102, form ion implanted region at described silicon area;
Step S103, form the silicon epitaxy layer that covers described ion implanted region surface;
Step S104, form the nickel metal layer that covers described silicon epitaxy layer;
Step S105, adopt the first annealing process to form the first metal silicide layer in silicon area surface and described silicon epitaxy layer;
Step S106, remove unreacted nickel metal layer;
Step S107, adopt the second annealing process to be annealed to the first metal silicide layer, forms the second metal silicide layer.
Formation method below in conjunction with a specific embodiment to self-aligned metal silicate of the present invention is described in detail, the process generalized section of the formation method of the self-aligned metal silicate that Fig. 5 to Figure 11 is one embodiment of the invention.
Please refer to Fig. 5, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surfaces have a silicon area at least.
Described Semiconductor substrate 100 surfaces are formed with grid structure 110, and described grid structure 110 comprises gate dielectric layer 111, be formed on the gate polysilicon layer 112 on gate medium surface, be formed on the side wall 113 of described gate dielectric layer 111 and gate polysilicon layer 112 sidewall; Be formed with source area 120 and drain region 130 in described Semiconductor substrate 100.
Described silicon area can be that the interior source area 120 of described Semiconductor substrate 100 is or/and drain region 130; Described silicon area can be also the gate polysilicon layer 112 on described Semiconductor substrate 100 surfaces.
In the present embodiment, take described silicon area does exemplary illustrated as source area 120, drain region 130 and gate polysilicon layer 112 as example.
Please refer to Fig. 6, at described silicon area, form ion implanted region 140.
In the present embodiment, form ion implanted region 140 at described source area 120, drain region 130 and gate polysilicon layer 112.It should be noted that, those skilled in the art also can, according to the needs of actual product, be chosen in described source area 120, drain region 130 and the arbitrary zone of gate polysilicon layer 112 or wherein in two zones, form ion implanted region 140.In the present embodiment, form ion implanted region 140 at described source area 120, drain region 130 and gate polysilicon layer 112 and can save processing step, and improve the electric property of the device formed.
Described ion implanted region 140 is the ion implanted region containing H, N, F or Pt, or is the ion implanted region containing two or more hybrid ionic of H, N, F or Pt.
Preferably, described ion implanted region 140 is Pt ion implanted region or the hybrid ionic injection region that comprises Pt.
The formation technique of described ion implanted region 140 is Implantation (Implant) or plasma treatment (Plasma Treat).
It is example that the Implantation of take forms described ion implanted region 140, and the formation step of described ion implanted region 140 is described in detail:
Form photoetching offset plate figure (not shown) on described Semiconductor substrate 100 surfaces, described photoetching offset plate figure exposes described source area 120, drain region 130 and gate polysilicon layer 112;
Adopt Implantation to carry out Implantation to described source area 120, drain region 130 and gate polysilicon layer 112, the type of described injection ion is H, N, F or Pt, the type of described injection ion or be that two or more hybrid ionic of H, N, F or Pt injects.
The technological parameter that adopts Implantation to form described ion implanted region 140 is: the ion implantation energy scope is 10KeV to 32KeV, and the concentration of Implantation is 1.0E14cm
-2to 3.2E14cm
-2.
Form the diffusion of ion implanted region 140 for the diffusion, particularly Ni of the metallic element that stops follow-up metal silicide, the thickness of described ion implanted region 140 is 10 dust to 20 dusts.
Preferably, the type of described injection ion is Pt or the hybrid ionic that comprises Pt, and the technological parameter of injection is: the ion implantation energy scope is 20KeV to 32KeV, and the concentration of Implantation is 1.0E14cm
-2to 3.2E14cm
-2.
In one embodiment, when the type of described injection ion is Pt, Pt not only has the effect of the diffusion of the diffusion that stops the metallic element in follow-up metal silicide, particularly Ni, and the ion implanted region of Pt can also form stable [Ni with Ni
xpt
(1-x)] the Si metal silicide, thereby make the device stable electrical properties.
In another embodiment, the ion of injection is the hybrid ionic that comprises Pt, and such as being: the hybrid ionic of the hybrid ionic of the hybrid ionic of H and Pt, N and Pt or F and Pt, wherein, the ion implanted region of Pt can also form stable [Ni with Ni
xpt
(1-x)] the Si metal silicide, stop the channel region diffusion of Ni to device, and H, N or F have better interception, thereby make device stability better.
Please refer to Fig. 7, form the silicon epitaxy layer 150 that covers described ion implanted region 140 surfaces.
It is extension that described silicon epitaxy layer 150 forms technique, and the thickness of described silicon epitaxy layer 150 is 50 dust to 200 dusts.
Described silicon epitaxy layer 150, for the nickel metal layer complete reaction of the formation with follow-up, forms the metal silicide of nickel (ratio of nickel and silicon approaches 1: 1), thereby reduces the resistance of silicon area.
It should be noted that, in one embodiment, in subsequent anneal technique, the Pt in Implanted Silicon zone also can diffuse to described silicon epitaxy layer 150, and the metal silicide layer that makes described silicon epitaxy layer 150 complete reactions form is stable and resistivity is low.
Please refer to Fig. 8, form the nickel metal layer 160 that covers described silicon epitaxy layer 150.
Described nickel metal layer 160 reacts for the surface silicon with silicon area and described silicon epitaxy layer 150, forms the metal silicide layer of rich nickel.
Particularly, described nickel metal layer 160 materials are pure nickel or nickel platinum alloy.
When nickel metal layer 160 materials are pure nickel, in subsequent anneal technique, the nickle atom diffusion ratio is very fast, can be fully and described silicon epitaxy layer 150 complete reactions, and react [the Ni of formation nickel with the surface silicon of silicon area
xpt
(1-x)] the Si metal silicide.
When nickel metal layer 160 materials are the nickel platinum alloy, wherein in the nickel platinum alloy, the mass percentage content of platinum is 1% to 10%, and in the metal silicide that adopts the nickel platinum alloy of above-mentioned mass percentage content to form, the ratio of nickel and silicon approaches 1: 1 and metal silicide ([Ni
xpt
(1-x)] Si) structural stability is better.
Please refer to Fig. 9, adopt the first annealing process at silicon area surface and interior formation the first metal silicide layer 170 of described silicon epitaxy layer 150.
Described the first parameter and annealing is for adopting rapid thermal anneler, annealing temperature is 200 ℃ to 350 ℃, annealing time is 0.1 minute to 2 minutes, adopt above-mentioned parameter and annealing can guarantee the fully metal silicide layer of reaction formation platinum nickel of described epitaxial loayer 150, it should be noted that, in the actual process process, silicon area is that source area 120 is or/and drain region 130, perhaps silicon area is gate polysilicon layer 112, and usually in the semiconductor bulk manufacturing process, need plurality of source regions 120, drain region 130, and/or gate polysilicon layer 112 forms metal silicide, above-mentioned source area 120, the width of drain region 130 and/or gate polysilicon layer 112 can be the same or different, when the width of above-mentioned silicon area is difference, if adopt a step annealing technique can't form the metal silicide layer of consistency of thickness, for this reason, embodiments of the invention adopt the first annealing process, select above-mentioned technological parameter, control the diffusion depth of Ni, thereby make the metal silicide layer consistency of thickness of the follow-up formation of silicon area of different in width, also it should be noted that, because the first parameter and annealing is preferably the diffusion depth of controlling Ni, therefore the first metal silicide layer 170 materials that adopt the first annealing process to form are Ni
2si, Ni
2the Si less stable, subsequent technique can adopt the second annealing process to form stable and the low NiSi of resistivity.
It should be noted that, in annealing process, the ion implanted region 140 before formed in step can stop that Ni and/or platinum diffuse to channel region, in addition, when ion implanted region that ion implanted region 140 is platiniferous, the Ni that ion implanted region 140 can be come with diffusion reacts, and forms the metal silicide layer of stable platinum nickel.
In addition, the inventor notices, due to ion implanted region 140 thinner thicknesses, and the ion of ion implanted region 140 is more stable, is stopping that the ion of ion implanted region 140 not there will be diffusion phenomena when being diffused into metallic element and diffuse metal element forms metal silicide.
Please refer to Figure 10, remove unreacted nickel metal layer 160.
Described removal technique is wet method or dry removal processes, and those skilled in the art can, with reference to prior art, here repeat no more.
Please refer to Figure 11, after removing unreacted nickel metal layer 160, also need to carry out the second annealing process, described the second annealing process is for adopting rapid thermal anneler, and annealing temperature is 300 ℃ to 600 ℃, and the time is 0.1 minute to 2 minutes; Adopt above-mentioned the second annealing process, the first metal silicide layer 170 is annealed, make Ni
2the first metal silicide layer 170 of Si is converted to the second metal silicide layer 180 containing the NiSi of Pt.
The resistivity of NiSi is low, and due to the Pt in ion implanted region 140 under the parameter of the second annealing process, react the second metal silicide layer 180 formed containing the NiSi of Pt with NiSi, the second metal silicide layer 180 that contains the NiSi of Pt not only has advantage and the better heat stability that resistivity is low.
The formation method of the self-aligned metal silicate of the embodiment of the present invention, first the silicon area at semiconductor substrate surface forms ion implanted region, then form silicon epitaxy layer on the ion implanted region surface, form the metal level containing Ni on the silicon epitaxy layer surface again, after annealing, form the metal silicide layer of platinum nickel with the silicon area surface in described silicon epitaxy layer, owing to thering is ion implanted layer, stop, and metal silicide layer is formed in described silicon epitaxy layer and the silicon area surface, therefore, metal ion can not diffuse to channel region, and the device quality of formation is high.
Further, described ion implanted region, containing the Pt ion, can form stable [Ni with the Ni that diffuses to ion implanted region
xpt
(1-x)] Si, stop that Ni spreads to channel region.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not break away from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (13)
1. the formation method of a self-aligned metal silicate, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has a silicon area at least;
Form ion implanted region at described silicon area;
Form the silicon epitaxy layer that covers described ion implanted region surface;
Form the nickel metal layer that covers described silicon epitaxy layer;
Adopt the first annealing process to form the first metal silicide layer in silicon area surface and described silicon epitaxy layer;
Remove unreacted nickel metal layer;
Adopt the second annealing process to be annealed to the first metal silicide layer, form the second metal silicide layer.
2. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, the ionic type that described ion implanted region injects is: H, N, F or Pt; It is perhaps two or more hybrid ionic containing H, N, F or Pt.
3. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, the formation technique of described ion implanted region is Implantation or plasma treatment.
4. the formation method of self-aligned metal silicate as claimed in claim 3, is characterized in that, the technological parameter that described Implantation forms ion implanted region is: the ion implantation energy scope is 10KeV to 32KeV, and the concentration of Implantation is 1.0E14cm
-2to 3.2E14cm
-2.
5. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, the thickness of described ion implanted region is 10 dust to 20 dusts.
6. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, the thickness of described silicon epitaxy layer is 50 dust to 200 dusts.
7. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, described silicon area is that source area is or/and drain region.
8. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, described silicon area is the gate polysilicon layer.
9. the formation method of self-aligned metal silicate as claimed in claim 1, is characterized in that, described nickel metal layer material is pure nickel or nickel platinum alloy.
10. the formation method of self-aligned metal silicate as claimed in claim 9, is characterized in that, when described nickel metal layer material is the nickel platinum alloy, in the nickel platinum alloy, the mass percentage content of platinum is 1% to 10%.
11. the formation method of self-aligned metal silicate, is characterized in that as claimed in claim 1, described the first annealing process is for adopting rapid thermal anneler, and annealing temperature is 200 ℃ to 350 ℃, and annealing time is 0.1 minute to 2 minutes.
12. the formation method of self-aligned metal silicate, is characterized in that as claimed in claim 1, described the second annealing process is for adopting rapid thermal anneler, and annealing temperature is 300 ℃ to 600 ℃, and the time is 0.1 minute to 2 minutes.
13. the formation method of self-aligned metal silicate, is characterized in that as claimed in claim 1, described the second metal silicide layer material is the NiSi containing Pt.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835728A (en) * | 2014-02-12 | 2015-08-12 | 北大方正集团有限公司 | Method for forming metal silicide on polycrystalline silicon and semiconductor device |
| CN106158585A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The surface treatment method of wafer, semiconductor device and preparation method thereof |
| WO2020102990A1 (en) * | 2018-11-20 | 2020-05-28 | 长江存储科技有限责任公司 | Formation method and annealing device for epitaxial layer and 3d nand memory |
| CN118263188A (en) * | 2024-05-29 | 2024-06-28 | 浙江创芯集成电路有限公司 | Semiconductor structure and forming method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070072358A1 (en) * | 2005-09-29 | 2007-03-29 | Chih-Ning Wu | Method of manufacturing metal-oxide-semiconductor transistor devices |
| CN1965403A (en) * | 2004-03-17 | 2007-05-16 | 德州仪器公司 | Integrated circuit metal silicide method |
| CN1989598A (en) * | 2004-09-14 | 2007-06-27 | 国际商业机器公司 | Uni-directional diffusion of metal silicide in semiconductor devices |
| CN101339904A (en) * | 2007-07-03 | 2009-01-07 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| CN101432860A (en) * | 2006-05-01 | 2009-05-13 | 国际商业机器公司 | Method for forming self-aligned metal silicide contacts |
| CN101452842A (en) * | 2007-11-30 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Production method for metal electrode capable of reducing leakage current of device |
| CN101764058A (en) * | 2009-12-31 | 2010-06-30 | 复旦大学 | Method for forming ultrathin controllable metal silicide |
| US20100167533A1 (en) * | 2008-12-26 | 2010-07-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor integrated circuit device |
| CN102024690A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| CN102044422A (en) * | 2009-10-19 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metallic silicide |
| US20110104893A1 (en) * | 2009-11-04 | 2011-05-05 | Jubao Zhang | Method for fabricating mos transistor |
| CN102208348A (en) * | 2010-03-29 | 2011-10-05 | 瑞萨电子株式会社 | Method of manufacturing semiconductor device |
-
2011
- 2011-11-25 CN CN201110383149.9A patent/CN103137462B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1965403A (en) * | 2004-03-17 | 2007-05-16 | 德州仪器公司 | Integrated circuit metal silicide method |
| CN1989598A (en) * | 2004-09-14 | 2007-06-27 | 国际商业机器公司 | Uni-directional diffusion of metal silicide in semiconductor devices |
| US20070072358A1 (en) * | 2005-09-29 | 2007-03-29 | Chih-Ning Wu | Method of manufacturing metal-oxide-semiconductor transistor devices |
| CN101432860A (en) * | 2006-05-01 | 2009-05-13 | 国际商业机器公司 | Method for forming self-aligned metal silicide contacts |
| CN101339904A (en) * | 2007-07-03 | 2009-01-07 | 株式会社瑞萨科技 | Method of manufacturing semiconductor device |
| CN101452842A (en) * | 2007-11-30 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Production method for metal electrode capable of reducing leakage current of device |
| US20100167533A1 (en) * | 2008-12-26 | 2010-07-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor integrated circuit device |
| CN102024690A (en) * | 2009-09-23 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
| CN102044422A (en) * | 2009-10-19 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metallic silicide |
| US20110104893A1 (en) * | 2009-11-04 | 2011-05-05 | Jubao Zhang | Method for fabricating mos transistor |
| CN101764058A (en) * | 2009-12-31 | 2010-06-30 | 复旦大学 | Method for forming ultrathin controllable metal silicide |
| CN102208348A (en) * | 2010-03-29 | 2011-10-05 | 瑞萨电子株式会社 | Method of manufacturing semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835728A (en) * | 2014-02-12 | 2015-08-12 | 北大方正集团有限公司 | Method for forming metal silicide on polycrystalline silicon and semiconductor device |
| CN104835728B (en) * | 2014-02-12 | 2017-12-12 | 北大方正集团有限公司 | The method and semiconductor devices of metal silicide are formed on the polysilicon |
| CN106158585A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The surface treatment method of wafer, semiconductor device and preparation method thereof |
| CN106158585B (en) * | 2015-04-03 | 2020-02-11 | 中芯国际集成电路制造(上海)有限公司 | Surface treatment method of wafer, semiconductor device and manufacturing method thereof |
| WO2020102990A1 (en) * | 2018-11-20 | 2020-05-28 | 长江存储科技有限责任公司 | Formation method and annealing device for epitaxial layer and 3d nand memory |
| CN112997272A (en) * | 2018-11-20 | 2021-06-18 | 长江存储科技有限责任公司 | Epitaxial layer and 3D NAND memory forming method and annealing equipment |
| CN112997272B (en) * | 2018-11-20 | 2024-03-29 | 长江存储科技有限责任公司 | Epitaxial layer and forming method and annealing equipment of 3D NAND memory |
| CN118263188A (en) * | 2024-05-29 | 2024-06-28 | 浙江创芯集成电路有限公司 | Semiconductor structure and forming method thereof |
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