TWI338915B - Plasma doping method and method for fabricating semiconductor device using the same - Google Patents

Plasma doping method and method for fabricating semiconductor device using the same Download PDF

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TWI338915B
TWI338915B TW096115529A TW96115529A TWI338915B TW I338915 B TWI338915 B TW I338915B TW 096115529 A TW096115529 A TW 096115529A TW 96115529 A TW96115529 A TW 96115529A TW I338915 B TWI338915 B TW I338915B
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substrate
plasma doping
layer
polysilicon layer
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TW200807514A (en
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Jae-Sung Roh
Jae-Geun Oh
Hyun-Chul Sohn
Sun-Hwan Hwang
Jin-Ku Lee
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32412—Plasma immersion ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

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Description

I33S915 九、發明說明： 本申請案要求優先權保護/其根據在2006年5月11 曰及2007年3月5曰申請之韓國專利申請案第 10-2006-0042509 號及第]0-2007-0021346 號，其所有內容 皆包含於其中以供參照。 【發明所屬之技術領域】 本發明係關於一種製造半導體裝置的方法，特別是一 種在基板或者薄層上執行的電漿（Plasma)摻雜方法。 【先前技術】 通常，在製造半導體裝置期間，執行摻雜來獲得所需 之基板或薄層（例如多晶矽）的電氣特性。主要使用一種光 束線離子佈植方法來作爲一種摻雜方法。該光束線離子佈 植方法係使用電場來加速欲佈植的離子（亦即，具備高的動 能）。該被加速之離子碰撞固態材料的表面。因此，該離子 可被佈植入該基板內。 近來，已使用一種電漿摻雜方法。在該電漿摻雜方法 中，該欲佈植之離子的來源材料係處於氣體狀態》形成電 漿，然後施加一個高的偏壓至欲摻雜的樣品。因此，該電 漿之正離子加速至該樣品的表面且被佈植於其中》所以， 該電漿摻雜方法可執行均勻的摻雜，並且改進摻雜率。而 且，相較於該光束離子佈植方法，因爲該電漿摻雜方法不 需要使用單獨的離子產生源（即，離子束）及加速設備，所 以可降低設備製造成本。 第1A至1C圖係說明一種用以製造半導體裝置的典型 1338915 方法。如第1A圖所示，複數裝置隔離層12形成在基板11 的區段內。在該基板Π上形成閘極絕緣層13，且在該閘極 絕緣層1 3上形成閘極多晶矽層1 4。執行電漿摻雜方法以利 用Ρ型雜質來摻雜該閘極多晶矽層14。 如第1 Β圖所示，執行退火處理來活化摻雜於該閘極多 晶矽層14內的該Ρ型雜質。 如第1C圖所示，在該閘極多晶矽層14上形成金屬矽 化物層（m e t a 1 s Π i c i d e 1 a y e r)，例如閘極矽化鎢層（g a t e tungsten silicide layer)15 ’然後執行閘極圖案化製程來作 爲後續處理。如果執行上述的電漿摻雜方法，在薄層的上 表面上方可會能存在著過高的雜質濃度。 第2圖係說明透過光束線離子佈植方法及電漿摻雜方 法，摻雜在形成有閘極多晶矽層之樣品上的雜質之典型輪 廓的曲線圖。水平軸代表該樣品之深度，而垂直軸代表用 作爲P型雜質的硼濃度。約800A的深度則指出了在該閘極 氧化層之上表面和閘極多晶矽層之間的界面之深度。更詳 細而言’該閘極多晶矽層的深度是約8 Ο Ο A。參照第2圖， 比較透過該電漿摻雜方法而獲得之雜質輪廓與透過該離子 佈植方法而獲得之雜質輪廓。相較於該光束線離子佈植， 當執行電漿摻雜方法時，在該閘極多晶矽層之上表面（例 如，在對應約Ο A之深度的閘極多晶矽層部分）的雜質濃度 係相對較大。特別是雖然在該光束線離子佈植方法中，該 雜質濃度在約200A處呈現出高斯分佈，但在該電漿摻雜方 法中’該雜質濃度於該鬧極多晶砂層之上表面爲最大。 1338915 第3圖係說明在執行退火處理之後，透過光束線離子 佈植方法及電漿摻雜方法而摻雜的雜質之典型輪廓的曲線 圖。參考標記及•代表在該電漿摻雜方法中使用的不同 類型之雜質。透過該退火處理，該雜質被活化下降至閘極 多晶矽層的下表面（例如，在閘極氧化層的上表面周遭）。 在執行該電漿摻雜方法的情況下，在該閘極多晶矽層之上 表面，亦即在該閘極多晶矽層之深度約爲Ο A處量測到最大 的雜質濃度。 如第2和3圖所示，如果執行該電漿摻雜方法，雖然 執行該退火處理，但大量雜質可能存在於該閘極多晶矽層 之上表面上方。在隨後的退火的處理期間，存在於該閘極 多晶矽層之上表面上方的雜質係朝向該閘極多晶矽層（例 如，金屬矽化物層）之上層進行擴散。因此，在該閘極多晶 矽層之表面周遭的摻雜效應突然降低。亦即，在該閘極多 晶矽層之表面會產生相關的雜質空乏效應（impurity depletion effect)。該摻雜效應的減少造成了該閘極多晶矽 層之阻抗的增加。此外，具有由以P+型雜質摻雜的多晶矽 所形成之閘極的P型金屬氧化半導體（PMOS)電晶體之飽和 電流特性可能會劣化。 【發明內容】 本發明之實施例係關於一種電漿摻雜方法，用以降低 在該上層之表面周遭的濃度尖峰。 本發明之實施例致力於提供一種製造半導體裝置的方 法，其中該方法能防止在閘極多晶矽層內之雜質的外擴 1338915 散，因此降低閛極多晶矽層的雜質空乏效應。 在一實施例中，電漿摻雜方法包括在基板上方提供摻 雜源，其中該摻雜源具有欲注入至該基板的摻雜物。施加 至少兩種不同的偏壓，將來自該摻雜源的摻雜物注入至該 基板。 在另一實施例中，製造半導體裝置的方法包括在基板 上方形成多晶矽層。使用電漿摻雜方法並以雜質來摻雜該 多晶矽，其中使用至少兩種不同的偏壓來執行該電漿摻雜 方法。 【實施方式】 根據本發明之實施例，電漿摻雜方法可施加於半導體 裝置製造處理的各種步驟。例如，可施加該電漿摻雜方法， 以摻雜由半導體材料（例如，矽）所形成之主體基板。該半 導體材料是磊晶層。此外’可施加該電漿摻雜方法，以摻 雜在基板之上部上方形成的薄層。特別是，本發明之實施 例的該電漿摻雜方法在摻雜閘極多晶矽層方面很有用。 第4 A至4 D圖係說明一種根據本發明之實施例的製造 半導體裝置的典型方法。如第4A圖所示，多數裝置隔離層 4 2形成在基板4 1 (例如，矽基板）內。透過淺溝槽隔離（s τ j) 方法來形成該裝置隔離層42。 在該基板4 1上方形成閘極絕緣層4 3。該閘極絕緣層 43可以是透過熱氧化法、乾式氧化法或濕式氧化法所形成 的氧化層。 在該閘極絕緣層43上方形成作爲閘極電極的閘極多 1338915 晶矽層44。在高度整合之記憶體裝’置中，該閘極多晶矽層 44之深度在從約400A到約1，20'0A的範圍中。然而，該閛 極多晶矽層44之深度可根據裝置類型而改變》 如第4B圖所示，當變化偏壓量以摻雜該閘極多晶矽層 44時’執行電漿摻雜方法。更詳細而言，摻雜的來源氣體 被加到該閘極多晶矽層44的上部。然後，該來源氣體被轉 換成電漿離子，且藉由對該基板41加上偏壓，該電漿離子 加速進入該閘極多晶矽層44。根據本發明之實施例，該偏 壓量並非固定’而是連續地變化。在摻雜P型雜質之硼（B) 的情況下，使用三氟化硼（BF〇或硼乙烷（B2H6)來作爲該來 源氣體。 在該電漿摻雜方法期間，該偏壓量從低電壓位準變成 高電壓位準，或者從高電壓位準變成低電壓位準。特別是， 如果參考偏壓（Vref)被定在約8kV，該偏壓量能在約 8kV±2kV的範圍內改變。例如，如果使用約8kV的該參考 偏壓（Vref)，藉由施加從約6kV上升到約l〇kV或從約l〇kV 下降至約6kV的偏壓來進行該摻雜。因此，在改變該偏壓 量時，如果執行該電漿摻雜方法，會得到類似光束線離子 佈植方法所獲得之雜質輪廓。特別是，該雜質輪廓會呈現 以比該閘極多晶矽層44之上表面還要低之部分爲基礎的 高斯分佈。 在該電漿摻雜方法期間，對於每個偏壓量，摻雜的劑 量可被均一地保持著。更詳細而言，在約10kV、約9kV、 約8kV、約7kV及約6kV的偏壓量，使用約ixi〇l6atoms/cm2 的劑量來執行該電漿摻雜方法。. 此外，在該電漿摻雜方法期.間，當該偏壓量變化時， 歧摻雜劑里可改變。當加上該參考偏壓時，使用最高的劑 量。因此，該雜質輪廓呈現出高斯分佈。例如，若要使用 約5xl〇 atoms/cm2的劑量及加上從約i〇kv改變到約6kv 的偏壓量來以三個步驟執行該電漿摻雜方法，則在約1〇kV 的偏壓量時’使用約lxl〇16at〇ms/cm2的劑量；在約的 偏壓量時’使用約3xl〇l6atoms/cm2的劑量；以及在約6kV 的偏壓量時’使用約lxl〇l6atoms/cm2的劑量。 如第4C圖所示，執行退火處理來活化摻雜在該閘極多 晶矽層44內之雜質。由於該退火處理，該雜質被活化朝向 該閘極絕緣層43。該退火處理包括使用快速熱處理（RTp)， 並且在溫度範圍從約850°C到約1，l〇(TC中執行該RTP達約 1秒到約60秒。 如上所述，如果在該偏壓量改變時執行該電漿摻雜方 法，該雜質輪廓能在該閘極多晶矽層44之上表面附近呈現 出高斯分佈，類似於透過該光束線離子佈植方法所獲得之 雜質輪廓。 如第4D圖所示，在該閘極多晶矽層44上方形成矽化 鎢層45。若非使用該矽化鎢層45，則可使用其他金屬矽化 物層或矽化物層以外的金屬層。 在該矽化鎢層45形成之後，採用熱處理來作爲隨後的 處理。然而，因爲在該閘極多晶矽層44內的雜質主要分布 在該閘極多晶矽層4 4的中心部分’雖然執行該熱處理’但 -10- 1338915 朝向矽化鎢層45的外擴散（out-diffusion)可受到控制。因 此，可防止該閘極多晶矽層44之阻抗的增加，且P型金屬 氧化半導體（PMOS)電晶體之飽和電流特性不會劣化。 第5圖係各種類型之摻雜方法的反轉電容量（inversion capacitance)的說明圖。參考字母A代表典型地透過佈植硼 而執行的方法。參考字母B代表不改變偏壓量而典型地執 行的電漿摻雜方法。參考字母C代表根據本發明之實施例 而改變偏壓量時所執行的電漿摻雜方法。參照第5圖，比 較被標示爲A' B及C之摻雜方法的各種類型之反轉電容 量。 當採用方法C時，反轉電容量之位準最大。當反轉電 容量之位準較小時，裝置的啓始電壓（threshold voltage)增 加’因此該裝置的操作特性劣化。因此，因爲採用本發明 之實施例的該電漿摻雜方法，該反轉電容量之位準增加， 所以該裝置特性獲得改善》 根據本發明之實施例，在該偏壓量改變時，執行該電 漿摻雜方法。由於該電漿摻雜方法，該雜質輪廓能在該薄 層之上表面附近呈現出高斯分佈，類似於藉由該典型光束 線離子佈植方法所獲得之雜質輪廓。因此，可降低該雜質 的外擴散’且因此可減少該裝置之電氣特性的劣化。 當根據該具體實施例來描述本發明時，只要不違背下 述申請專利範圍中所定義之精神及範圍，熟習該項技藝者 就可進行各種變化和修改。 【圖式簡單說明】 -11- 1338915 第1A至1C圖係說明一種用以’製造半導體裝置的典型 方法。 第2圖係說明分別透過光束線離子佈植方法及電漿摻 雜方法而摻雜的雜質之典型輪廓的曲線圖。 第3圖係說明在執行退火處理之後，分別透過光束線 離子佈植方法及電漿摻雜方法而摻雜的雜質之典型輪廊的 曲線圖。 第4Α至4D圖係說明一種根據本發明之實施例的製造 半導體裝置的方法》 第5圖係各種類型之摻雜方法所獲得之胃胃@ 說明圖。 C 主要元件 符 號 說 明 11 基 板 12 裝 置 隔 離 層 13 閘 極 絕 緣 層 14 閘 極 多 晶 矽 層 15 閘 極 矽 化 鎢 層 41 基 板 42 裝 置 隔 離 層 43 閘 極 絕 緣 層 44 閘 極 多 晶 矽 層 45 矽 化 錫 層I33S915 IX. INSTRUCTIONS: This application claims priority protection/in accordance with Korean Patent Application No. 10-2006-0042509 and No. 0-2007, which were filed on May 11, 2006 and March 5, 2007. No. 0021346, all of which are included for reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a plasma doping method performed on a substrate or a thin layer. [Prior Art] Generally, during the fabrication of a semiconductor device, doping is performed to obtain electrical characteristics of a desired substrate or thin layer (e.g., polysilicon). A beamline ion implantation method is mainly used as a doping method. The beamline ion implantation method uses an electric field to accelerate ions to be implanted (i.e., has high kinetic energy). The accelerated ions collide with the surface of the solid material. Therefore, the ions can be implanted into the substrate. Recently, a plasma doping method has been used. In the plasma doping method, the source material of the ions to be implanted is in a gaseous state to form a plasma, and then a high bias is applied to the sample to be doped. Therefore, the positive ions of the plasma are accelerated to the surface of the sample and are implanted therein. Therefore, the plasma doping method can perform uniform doping and improve the doping ratio. Moreover, compared to the beam ion implantation method, since the plasma doping method does not require the use of a separate ion generating source (i.e., ion beam) and an acceleration device, the manufacturing cost of the device can be reduced. 1A to 1C illustrate a typical 1338915 method for fabricating a semiconductor device. As shown in FIG. 1A, a plurality of device isolation layers 12 are formed in the sections of the substrate 11. A gate insulating layer 13 is formed on the substrate, and a gate polysilicon layer 14 is formed on the gate insulating layer 13. A plasma doping method is performed to dope the gate polysilicon layer 14 with germanium-type impurities. As shown in Fig. 1, an annealing treatment is performed to activate the germanium-type impurity doped in the gate polysilicon layer 14. As shown in FIG. 1C, a metal telluride layer is formed on the gate polysilicon layer 14, for example, a gate tungsten silicide layer 15', and then gate patterning is performed. The process is used as a follow-up process. If the plasma doping method described above is carried out, an excessively high impurity concentration may exist above the upper surface of the thin layer. Fig. 2 is a graph showing a typical profile of impurities doped on a sample having a gate polysilicon layer formed by a beam line ion implantation method and a plasma doping method. The horizontal axis represents the depth of the sample, and the vertical axis represents the boron concentration used as the P-type impurity. A depth of about 800 A indicates the depth of the interface between the upper surface of the gate oxide layer and the gate polysilicon layer. More specifically, the depth of the gate polysilicon layer is about 8 Ο Ο A. Referring to Fig. 2, the impurity profile obtained by the plasma doping method and the impurity profile obtained by the ion implantation method are compared. Compared to the beamline ion implantation, when performing the plasma doping method, the impurity concentration on the surface of the gate polysilicon layer (for example, the portion of the gate polysilicon layer corresponding to the depth of about Ο A) is relatively Larger. In particular, although in the beamline ion implantation method, the impurity concentration exhibits a Gaussian distribution at about 200 A, in the plasma doping method, the impurity concentration is the largest on the surface of the Ravine polycrystalline sand layer. . 1338915 Fig. 3 is a graph showing a typical profile of impurities doped by a beam line ion implantation method and a plasma doping method after performing an annealing treatment. The reference marks and ? represent the different types of impurities used in the plasma doping method. Through the annealing treatment, the impurities are activated to fall to the lower surface of the gate polysilicon layer (e.g., around the upper surface of the gate oxide layer). In the case of performing the plasma doping method, the maximum impurity concentration is measured on the surface of the gate polysilicon layer, i.e., at a depth of the gate polysilicon layer of about Ο A. As shown in Figs. 2 and 3, if the plasma doping method is performed, although the annealing treatment is performed, a large amount of impurities may exist above the upper surface of the gate polysilicon layer. During the subsequent annealing process, impurities present above the upper surface of the gate polysilicon layer diffuse toward the upper layer of the gate polysilicon layer (e.g., metal germanide layer). Therefore, the doping effect around the surface of the gate polysilicon layer suddenly decreases. That is, an associated impurity depletion effect is generated on the surface of the gate polysilicon layer. This reduction in doping effect causes an increase in the impedance of the gate polysilicon layer. Further, the saturation current characteristics of a P-type metal oxide semiconductor (PMOS) transistor having a gate formed of polysilicon doped with a P + -type impurity may be deteriorated. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a plasma doping method for reducing concentration spikes around a surface of the upper layer. Embodiments of the present invention are directed to a method of fabricating a semiconductor device in which the diffusion of impurities in the gate polysilicon layer is prevented, thereby reducing the impurity depletion effect of the drain polysilicon layer. In one embodiment, a plasma doping method includes providing a dopant source over a substrate, wherein the dopant source has a dopant to be implanted into the substrate. A dopant from the dopant source is implanted into the substrate by applying at least two different bias voltages. In another embodiment, a method of fabricating a semiconductor device includes forming a polysilicon layer over a substrate. The polysilicon is doped with a plasma doping method and with impurities, wherein the plasma doping method is performed using at least two different bias voltages. [Embodiment] According to an embodiment of the present invention, a plasma doping method can be applied to various steps of a semiconductor device manufacturing process. For example, the plasma doping method can be applied to dope a body substrate formed of a semiconductor material (eg, germanium). The semiconductor material is an epitaxial layer. Further, the plasma doping method can be applied to dope a thin layer formed over the upper portion of the substrate. In particular, the plasma doping method of embodiments of the present invention is useful in doping a gate polysilicon layer. 4A through 4D illustrate a typical method of fabricating a semiconductor device in accordance with an embodiment of the present invention. As shown in Fig. 4A, a plurality of device isolation layers 42 are formed in a substrate 4 1 (e.g., a germanium substrate). The device isolation layer 42 is formed by a shallow trench isolation (s τ j) method. A gate insulating layer 43 is formed over the substrate 41. The gate insulating layer 43 may be an oxide layer formed by a thermal oxidation method, a dry oxidation method or a wet oxidation method. A gate electrode 134415 as a gate electrode is formed over the gate insulating layer 43. In a highly integrated memory device, the gate polysilicon layer 44 has a depth in the range from about 400A to about 1,20'0A. However, the depth of the germanium polysilicon layer 44 may vary depending on the type of device. As shown in Fig. 4B, the plasma doping method is performed when the bias amount is varied to dope the gate polysilicon layer 44. In more detail, the doped source gas is added to the upper portion of the gate polysilicon layer 44. The source gas is then converted to plasma ions and the plasma ions are accelerated into the gate polysilicon layer 44 by biasing the substrate 41. According to an embodiment of the invention, the amount of bias is not fixed 'but varies continuously. In the case of boron (B) doped with a P-type impurity, boron trifluoride (BF 〇 or boron ethane (B 2 H 6 ) is used as the source gas. During the plasma doping method, the bias amount is from The low voltage level becomes a high voltage level, or changes from a high voltage level to a low voltage level. In particular, if the reference bias voltage (Vref) is set at about 8 kV, the bias amount can be in the range of about 8 kV ± 2 kV. Internal change. For example, if the reference bias voltage (Vref) of about 8 kV is used, the doping is performed by applying a bias voltage that rises from about 6 kV to about 10 kV or from about 10 kV to about 6 kV. When the bias amount is changed, if the plasma doping method is performed, an impurity profile similar to that obtained by the beam line ion implantation method is obtained. In particular, the impurity profile may exhibit a polysilicon layer 44 than the gate. The portion of the upper surface is also a low-based Gaussian distribution. During the plasma doping method, the doping dose can be uniformly maintained for each bias amount. More specifically, at about 10 kV, 9kV, about 8kV, about 7kV and about 6kV bias, using about ixi〇l6atoms/cm2 The plasma doping method is performed by a dose. Further, during the plasma doping method period, when the bias amount is changed, the dissimilar dopant may be changed. When the reference bias is added, the use is performed. The highest dose. Therefore, the impurity profile exhibits a Gaussian distribution. For example, if a dose of about 5xl 〇atoms/cm2 is used and a bias amount is changed from about i〇kv to about 6kv, the three-step execution is performed in three steps. In the plasma doping method, a dose of about lxl 〇 16 at 〇 ms / cm 2 is used at a bias amount of about 1 〇 kV; a dose of about 3 x 1 〇 16 atoms / cm 2 is used at about a bias amount; When a bias amount of about 6 kV is used, 'a dose of about lxl 〇l6 atoms/cm 2 is used. As shown in Fig. 4C, an annealing treatment is performed to activate impurities doped in the gate polysilicon layer 44. Due to the annealing treatment, the impurities The activation is directed toward the gate insulating layer 43. The annealing process includes using a rapid thermal process (RTp) and is performed at a temperature ranging from about 850 ° C to about 1, 10 Torr (the RTP is performed in the TC for about 1 second to about 60 seconds). As described above, if the plasma doping method is performed when the bias amount is changed, the impurity wheel A Gaussian distribution can be exhibited near the upper surface of the gate polysilicon layer 44, similar to the impurity profile obtained by the beamline ion implantation method. As shown in Fig. 4D, a deuteration is formed over the gate polysilicon layer 44. The tungsten layer 45. If the tungsten germanium layer 45 is not used, other metal telluride layers or metal layers other than the germanide layer may be used. After the tungsten germanium layer 45 is formed, heat treatment is used as a subsequent treatment. The impurities in the gate polysilicon layer 44 are mainly distributed in the central portion of the gate polysilicon layer 44. Although the heat treatment is performed, the out-diffusion of the-10-1338915 toward the tungsten carbide layer 45 can be controlled. Therefore, the increase in the impedance of the gate polysilicon layer 44 can be prevented, and the saturation current characteristics of the P-type metal oxide semiconductor (PMOS) transistor are not deteriorated. Fig. 5 is an explanatory diagram of inversion capacitance of various types of doping methods. Reference letter A represents a method that is typically performed by implanting boron. The reference letter B represents a plasma doping method which is typically performed without changing the amount of bias. The reference letter C represents a plasma doping method performed when the bias amount is changed according to an embodiment of the present invention. Referring to Figure 5, the various types of inversion capacitances labeled as A' B and C doping methods are compared. When Method C is used, the level of the reversed capacitance is the largest. When the level of the reversed capacitance is small, the threshold voltage of the device is increased, so the operational characteristics of the device are deteriorated. Therefore, since the plasma doping method of the embodiment of the present invention increases the level of the inversion capacitance, the device characteristics are improved. According to an embodiment of the present invention, when the bias amount is changed, execution is performed. The plasma doping method. Due to the plasma doping method, the impurity profile can exhibit a Gaussian distribution near the upper surface of the thin layer, similar to the impurity profile obtained by the typical beam line ion implantation method. Therefore, the outdiffusion of the impurities can be reduced and thus the deterioration of the electrical characteristics of the device can be reduced. When the present invention is described in terms of the specific embodiments, various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS -11- 1338915 Figs. 1A to 1C illustrate a typical method for manufacturing a semiconductor device. Fig. 2 is a graph showing a typical profile of impurities doped by a beam line ion implantation method and a plasma doping method, respectively. Fig. 3 is a graph showing a typical corridor of impurities doped by a beam line ion implantation method and a plasma doping method, respectively, after performing an annealing treatment. Figs. 4 to 4D illustrate a method of fabricating a semiconductor device according to an embodiment of the present invention. Fig. 5 is a stomach and stomach diagram obtained by various types of doping methods. C Main components Symbol Description 11 Substrate 12 Device Separation layer 13 Gate Insulation Layer 14 Gate Polysilicon Layer 15 Gate Tungsten Tungsten Layer 41 Substrate 42 Device Separation Layer 43 Gate Insulation Layer 44 Gate Polycrystalline Layer 45 Antimony Tin Layer

Claims (1)

1338915 第96Π5529號「電漿摻雜方法與使.用此種方法製造半導體 裝置之方法」專利案 (2010年11月1〇日修正） 十、申請專利範圍： 1. 一種電漿摻雜方法，其包括： 在基板上方提供電漿摻雜源，該電漿摻雜源具有欲注 入至形成在該基板上方之目標層的摻雜物； 在將該摻雜物從該電漿摻雜源注入至該目標層之同 時施加偏壓至該基板，將該偏壓從較低範圍，經由中間 範圍至較高範圍地予以改變，且該摻雜物的劑量在該中 間範圍內比在該較低範圍及較高範圍內高；及 將該基板退火以使該摻雜物之與摻雜深度相關的雜 質輪廓（impurity profile)近似於高斯分佈。 2. 如申請專利範圍第1項之摻雜方法，其中，注入至該基 板的劑量會隨著各該經改變的偏壓量而改變。 3. 如申請專利範圍第1項之摻雜方法，其中，目標層包括 多晶矽層及磊晶層中之一者。 4. 一種製造半導體裝置的方法，該方法包括： 在基板上方形成閘極絕緣層； 在該閘極絕緣層上方形成多晶矽層； 藉由執行電漿摻雜方法以雜質來摻雜該多晶矽層， 其中在執行該電漿摻雜方法之同時施加偏壓至該基板， 1338915 將該偏壓從較低範圍，經由中間範圍至較高範圍地予以 改變，且該雜質的劑量在該中’間範圍內比在該較低範圍 及較高範圍內高； 將該基板退火以使該經摻雜的多晶矽層之與摻雜深 度相關的雜質輪廓近似於高斯分佈。 5. 如申請專利範圍第4項之方法，其中，該退火包括使用快 速熱處理。 6. 如申請專利範圍第4項之方法，其中，該多晶矽層係用來 定義出閘極電極。 7. 如申請專利範圍第4項之方法，其中，更包含形成傳導層， 該傳導層包括位於摻雜有該雜質之該多晶矽層上方的金 屬系材料。 8. 如申請專利範圍第4項之方法，其中，以雜質來摻雜該多 晶矽層還包括： 在該多晶矽層上方提供來源氣體； 將該來源氣體轉換成電漿離子；以及 藉由施加該偏壓來加速該電漿離子朝向該多晶矽 層。 9. 如申請專利範圍第8項之方法，其中，該來源氣體包括三 氟化硼（BF〇或者硼乙烷（β2Η6)。 1 0 ·如申請專利範圍第4項之方法，其中，該多晶矽層深度 之範圍從400A到1，200A。 11·如申請專利範圍第4項之方法，其中，該偏壓量在 8kV±2kV的範圍中變化。 1338915 12.如申請專利範圍第1項之方法，其中’該退火包括使用 快速熱處理。 · 1 3.如申請專利範圍第1項之方法，其中’該電漿掺雜源包 括三氟化硼（BF3)或者硼乙烷（B2H<0。 14.如申請專利範圍第1項之方法，其中’該偏壓量在 8kV 土 2kV的範圍中變化。 1 5 . —種電漿摻雜方法，其包括·· 在基板上方提供電漿摻雜源，該電漿摻雜源具有欲注 入至形成在該基板上方之目標層的摻雜物； 在將該摻雜物從該電漿摻雜源注入至該目標層之同 時施加偏壓至該基板，將該偏壓從較高範圍，經由中間 範圍至較低範圍地予以改變，且該摻雜物的劑量在該中 間範圍內比在該較低範圍及較高範圍內高；及 將該基板退火以使該摻雜物之與摻雜深度相關的雜 質輪廓近似於高斯分佈。1338915 No. 96Π5529 "Plastic doping method and method for manufacturing semiconductor device by this method" Patent (amended on November 1, 2010) X. Patent application scope: 1. A plasma doping method, The method includes: providing a plasma doping source over the substrate, the plasma doping source having a dopant to be implanted into a target layer formed over the substrate; injecting the dopant from the plasma doping source Applying a bias voltage to the substrate while the target layer is applied, the bias voltage is changed from a lower range, through a middle range to a higher range, and the dose of the dopant is lower in the intermediate range than at the lower The range is higher in the upper range; and the substrate is annealed such that the impurity profile associated with the doping depth of the dopant approximates a Gaussian distribution. 2. The doping method of claim 1, wherein the dose injected into the substrate varies with each of the changed bias amounts. 3. The doping method of claim 1, wherein the target layer comprises one of a polysilicon layer and an epitaxial layer. A method of fabricating a semiconductor device, the method comprising: forming a gate insulating layer over a substrate; forming a polysilicon layer over the gate insulating layer; doping the polysilicon layer with impurities by performing a plasma doping method, Wherein the bias is applied to the substrate while the plasma doping method is being performed, 1338915 changes the bias voltage from a lower range, via a middle range to a higher range, and the dose of the impurity is in the middle range The inner ratio is higher in the lower range and the upper range; the substrate is annealed such that the dopant profile associated with the doping depth of the doped polysilicon layer approximates a Gaussian distribution. 5. The method of claim 4, wherein the annealing comprises using a rapid heat treatment. 6. The method of claim 4, wherein the polysilicon layer is used to define a gate electrode. 7. The method of claim 4, further comprising forming a conductive layer comprising a metal-based material over the polysilicon layer doped with the impurity. 8. The method of claim 4, wherein doping the polysilicon layer with impurities further comprises: providing a source gas over the polysilicon layer; converting the source gas into plasma ions; and applying the bias Pressing to accelerate the plasma ions toward the polysilicon layer. 9. The method of claim 8, wherein the source gas comprises boron trifluoride (BF〇 or boroethane (β2Η6). 1 0. The method of claim 4, wherein the polycrystalline germanium The depth of the layer ranges from 400 A to 1,200 A. The method of claim 4, wherein the bias amount varies in the range of 8 kV ± 2 kV. 1338915 12. The method of claim 1 , wherein the annealing comprises the use of rapid thermal processing. The method of claim 1, wherein the plasma doping source comprises boron trifluoride (BF3) or boron fluoride (B2H < The method of claim 1, wherein the bias amount is varied within a range of 8 kV soil 2 kV. A plasma doping method comprising: providing a plasma doping source above the substrate The plasma doping source has a dopant to be implanted into a target layer formed over the substrate; applying a bias voltage to the substrate while implanting the dopant from the plasma doping source to the target layer , the bias voltage is from a higher range, through the middle range to the The range is varied, and the dose of the dopant is higher in the intermediate range than in the lower range and the higher range; and the substrate is annealed to make the impurity profile associated with the doping depth of the dopant Approximate to Gaussian distribution.
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