CN101071768A - Plasma doping method and method for fabricating semiconductor device using the same - Google Patents
Plasma doping method and method for fabricating semiconductor device using the same Download PDFInfo
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- CN101071768A CN101071768A CNA2007101068139A CN200710106813A CN101071768A CN 101071768 A CN101071768 A CN 101071768A CN A2007101068139 A CNA2007101068139 A CN A2007101068139A CN 200710106813 A CN200710106813 A CN 200710106813A CN 101071768 A CN101071768 A CN 101071768A
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002019 doping agent Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 48
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 239000012535 impurity Substances 0.000 claims description 38
- 238000000137 annealing Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 4
- 229910015900 BF3 Inorganic materials 0.000 claims description 2
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 18
- 230000008569 process Effects 0.000 description 11
- 229940090044 injection Drugs 0.000 description 8
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 239000012212 insulator Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 150000001768 cations Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32412—Plasma immersion ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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Abstract
A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.
Description
The cross reference of related application
The present invention requires to enjoy respectively on May 11st, 2006 and the korean patent application 10-2006-0042509 of submission on March 5th, 2007 and the preference of 10-2007-0021346, and it all is incorporated herein by reference.
Technical field
The present invention relates to a kind of method of making semiconductor device, more specifically relate to the plasma doping of on substrate or thin layer, implementing.
Background technology
Usually, during semiconductor device is made, implement to mix to obtain for example required electrical characteristics of polysilicon of substrate or thin layer.The main beamline ion implanters method for implanting that uses is as doping method.The beamline ion implanters method for implanting utilizes electric field to quicken ion (high kinetic energy promptly is provided) to be injected.Ion that is accelerated and solid-state material surface collision.As a result, ion is injected in the substrate.
Recently, utilized plasma doping.In plasma doping, the source material of waiting to inject ion is a gaseous state.Form plasma, then high bias voltage is applied to sample to be mixed.As a result, the cation of plasma quickens to enter into sample surfaces and injects wherein.Therefore, plasma doping can be realized mixing uniformly and improving doping speed.In addition, owing to compare with the ion beam method for implanting, plasma doping does not need to use independent ion that source (being ion beam) and accelerator take place, and therefore can reduce the device fabrication cost.
Figure 1A～1C has illustrated the typical method of making semiconductor device.Shown in Figure 1A, in part substrate 11, form a plurality of device isolation layers 12.On substrate 11, form gate insulator 13, on gate insulator 13, form gate polysilicon layer 14.Implement plasma doping and come doping grid polysilicon layer 14 to utilize p type impurity.
Shown in Figure 1B, implement annealing in process and be entrained in p type impurity in the gate polysilicon layer 14 with activation.
Shown in Fig. 1 C, on gate polysilicon layer 14, form for example gate salicidation tungsten layer 15 of metal silicide layer, implement the gate pattern process then as subsequent treatment.If implement plasma doping, may on the upper surface of thin layer, there be the impurity of excessive concentration according to above explanation.
Fig. 2 is explanation is entrained in the impurity on the sample that is formed with gate polysilicon layer by bunch ion injection method and plasma doping a typical plot.Transverse axis is represented the degree of depth of sample, and the longitudinal axis is represented the concentration as the boron of p type impurity.The degree of depth of about 800 equals the interface degree of depth between gate oxide level upper surface and the gate polysilicon layer.More specifically, the degree of depth of gate polysilicon layer is about 800 .With reference to figure 2, impurity curve that obtains by plasma doping and the impurity curve that obtains by ion injection method are compared.Compare with the beamline ion implanters injection, when implementing plasma doping, the concentration of (for example at the grid polycrystalline silicon layer segment place corresponding to about 0 degree of depth) impurity is relatively large at gate polysilicon layer upper surface place.Especially show as Gaussian Profile in about 200 place impurity concentrations in the beamline ion implanters method for implanting, impurity concentration is in the upper surface place of gate polysilicon layer maximum in plasma doping.
Fig. 3 is the typical plot of impurity after carrying out annealing process that explanation is mixed by bunch ion injection method and plasma doping.Reference numeral ■ and ● be illustrated in the dissimilar impurity that uses in the plasma doping.Impurity can be through annealing in process and the movable downwards basal surface to gate polysilicon layer (for example, approximately the upper surface of gate oxide level).Implementing under the situation of plasma doping, measuring maximum impurity concentration at the upper surface place of gate polysilicon layer, promptly in about 0 degree of depth of gate polysilicon layer.
Shown in Fig. 2 and 3, if implement plasma doping, although implement annealing in process, a large amount of impurity may reside on the upper surface of gate polysilicon layer.In the subsequent anneal process, the impurity that is present on the gate polysilicon layer upper surface spreads to the upper strata of gate polysilicon layer.Therefore, the near surface doping effect at gate polysilicon layer sharply reduces.Promptly may produce relative impurity loss effect in the surface of gate polysilicon layer.The reduction of doping effect causes the increase of gate polysilicon layer resistance.In addition, have by P
+The transistorized saturation current performance of p type metal oxide semiconductor (PMOS) of the grid that the polysilicon of type doping impurity forms may be demoted.
Summary of the invention
Embodiment of the present invention relate to plasma doping, and it reduces near the peak concentration (concentration spike) the topsheet surface.
Embodiment of the present invention relate to provides a kind of method of making semiconductor device, wherein said method can prevent that the interior impurity of gate polysilicon layer to outdiffusion, reducing the impurity loss effect of gate polysilicon layer thus.
In one embodiment, plasma doping is included in doped source is provided on the substrate, and wherein doped source has the dopant of waiting to be injected in the substrate.Apply at least two kinds of different bias voltages so that dopant is injected into substrate from doped source.
In another embodiment, the method for manufacturing semiconductor device is included in and forms polysilicon layer on the substrate.Utilize the plasma doping impurity doped polysilicon, wherein utilize at least two kinds of different bias voltages to implement described plasma doping.
Description of drawings
The typical method of semiconductor device is made in Figure 1A～1C explanation.
Fig. 2 is the figure that the typical curve of the impurity that passes through the doping of bunch ion injection method and plasma doping respectively is described.
Fig. 3 is the figure that the typical curve of impurity after implementing annealing in process that mixes by bunch ion injection method and plasma doping is described respectively.
The method of semiconductor device is made in Fig. 4 A～4D explanation according to an embodiment of the present invention.
Fig. 5 is the figure of the explanation inversion capacitance that various doping method obtained.
Embodiment
According to embodiment of the present invention, plasma doping can be applicable in each step of method, semi-conductor device manufacturing method.For example, plasma doping can be applicable to mix by the semi-conducting material bulk substrate (bulk substrate) that forms of silicon for example.Semi-conducting material is an epitaxial loayer.And plasma doping can be applicable to be entrained in the thin layer that forms on the top of substrate.Particularly, plasma doping can be used for the doping grid polysilicon layer according to embodiments of the present invention.
The method of semiconductor device is made in Fig. 4 A～4D explanation according to an embodiment of the present invention.Shown in Fig. 4 A, for example form a plurality of device isolation layers 42 in the silicon substrate at substrate 41.Device isolation layer 42 forms through shallow-trench isolation (STI) method.
On substrate 41, form gate insulator 43.Gate insulator 43 can be the oxide skin(coating) that forms through thermal oxidation method, dry oxidation or wet oxidation.
On gate insulator 43, be formed for the gate polysilicon layer 44 of gate electrode.In highly integrated memory device, the degree of depth of gate polysilicon layer 44 is about 400 ～about 1200 .But the degree of depth of gate polysilicon layer 44 can change according to the type of device.
Shown in Fig. 4 B, implement the size that plasma doping changes bias voltage simultaneously, with doping grid polysilicon layer 44.In more detail, doped source gas is added to the top of gate polysilicon layer 44.Then, source gas is converted into plasma ion, and by substrate 41 is applied bias voltage, this plasma ion quickens to enter gate polysilicon layer 44.According to embodiment of the present invention, the size of bias voltage is not constant, but continually varying.Under the situation of doped p type boron impurities (B), boron trifluoride (BF
3) or diborane (B
2H
6) be used as source gas.
During plasma doping, the size of bias voltage changes to level high from low voltage level, perhaps changes to low voltage level from level high.Particularly, if benchmark bias voltage (V
Ref) being set to about 8kV, the size of bias voltage can change in the scope of about 8kV ± 2kV.For example, if use the benchmark bias voltage (V of about 8kV
Ref), then apply from about 6kV and rise to the bias voltage of about 10kV or mix from the bias voltage that about 10kV drops to about 6kV.Therefore, if in the size that changes bias voltage, implement plasma doping, can obtain to be similar to the impurity curve that obtains by the beamline ion implanters method for implanting so.Particularly, based on than the lower part of gate polysilicon layer 44 upper surfaces, the impurity curve table reveals Gaussian Profile.
During plasma doping,, can keep dopant dose equably for the size of each bias voltage.More specifically, be under each bias voltage of about 10kV, about 9kV, about 8kV, about 7kV and about 6kV in size, utilize about 1 * 10
16Atom/cm
2Dosage implement plasma doping.
In addition, during plasma doping, dopant dose can change with the size variation of bias voltage.When applying the benchmark bias voltage, use maximum dose level.As a result, the impurity curve table reveals Gaussian Profile.For example, if utilize about 5 * 10
16Atom/cm
2Dosage and apply bias voltage that size changes to about 6kV from about 10kV and divide three to go on foot and implement plasma doping, use about 1 * 10 under the bias voltage of about 10kV size so
16Atom/cm
2Dosage; Under the bias voltage of about 8kV size, use about 3 * 10
16Atom/cm
2Dosage; Under the bias voltage of about 6kV size, use about 1 * 10
16Atom/cm
2Dosage.
Shown in Fig. 4 C, implement annealing process and be entrained in impurity in the gate polysilicon layer 44 with activation.Because annealing process, impurity is to gate insulator 43 activities.Annealing process comprises utilizes rapid thermal treatment (RTP), and RTP carried out about 1 second～about 60 seconds under about 850 ℃～about 1100 ℃ temperature.
As mentioned above, if implement the size that plasma doping changes bias voltage simultaneously, then the impurity curve can show near gate polysilicon layer 44 upper surfaces and be similar to the Gaussian Profile that obtains by the bunch ion injection method.
Shown in Fig. 4 D, on gate polysilicon layer 44, form tungsten silicide layer 45.Can use other metal silicide layers or be different from the metal level of silicide layer, substitute and use tungsten silicide layer 45.
After forming tungsten silicide layer 45, use heat treatment as subsequent process.But because the impurity in the gate polysilicon layer 44 mainly are distributed in the core of gate polysilicon layer 44, though therefore implement heat treatment also can control tungsten silicide layer 45 to outdiffusion.Therefore, can prevent that the resistance of gate polysilicon layer 44 from increasing, and the transistorized saturation current performance of p type metal oxide semiconductor (PMOS) is not demoted.
Fig. 5 is the figure of the inversion capacitance of each doping method of explanation.Reference numeral A represents typically by injecting the method that boron is implemented.Reference numeral B represents not change the size of bias voltage and the plasma doping typically implemented.Reference number C is represented according to embodiments of the present invention another plasma doping of implementing in the size that changes bias voltage.With reference to figure 5, relatively be labeled as the inversion capacitance of every kind of doping method of A, B and C.
Inversion capacitance level maximum when implementing the C method.Along with the inversion capacitance level reduces, the threshold voltage of device increases, and makes the operating characteristics degradation of device thus.Therefore, plasma doping increases the inversion capacitance level owing to using according to embodiments of the present invention, thereby can improve device performance.
According to an embodiment of the present invention, in the size that changes bias voltage, carry out plasma doping.Because can showing, plasma doping, impurity curve be similar to the Gaussian Profile that obtains by typical beamline ion implanters method for implanting near the thin layer upper surface.Therefore, can reduce impurity to outdiffusion, and also can reduce the degradation of device electrical performance thus.
Though the present invention has been described, has it will be readily apparent to one skilled in the art that and to make variations and modifications not departing under the situation of spirit and scope of the invention as defined by the appended claims about specific embodiments.
Claims (20)
1. plasma doping comprises:
Doped source is provided on substrate, and described doped source has the dopant of waiting to be injected in the described substrate; With
Apply at least two kinds of different bias voltages so that described dopant is injected into described substrate from described doped source.
2. the doping method of claim 1 also comprises:
Annealing is doped to described dopant in the described substrate with activation.
3. the doping method of claim 1, wherein the bias voltage that is applied changes to level high from low voltage level.
4. the doping method of claim 1, wherein the bias voltage that is applied changes to low voltage level from level high.
5. the doping method of claim 1, the dosage that wherein is injected into described substrate changes with the size of each bias voltage that applies.
6. the doping method of claim 1 wherein changes the size of the bias voltage that is applied, and makes that the impurity class of a curve with respect to doping depth is similar to Gaussian Profile.
7. the doping method of claim 1, wherein said substrate has polysilicon layer as the upper strata.
8. the doping method of claim 1, wherein said substrate has epitaxial loayer as the upper strata.
9. method of making semiconductor device, described method comprises:
On substrate, form polysilicon layer; With
Utilize plasma doping with the described polysilicon layer of doping impurity, wherein utilize at least two kinds of different bias voltages to implement described plasma doping.
10. the method for claim 9 comprises that also annealing is doped to described impurity in the described polysilicon with activation.
11. comprising, the method for claim 10, wherein said annealing utilize rapid thermal treatment.
12. the method for claim 9, wherein the bias voltage that is applied changes to level high from low voltage level.
13. the method for claim 9, wherein the bias voltage that is applied changes to low voltage level from level high.
14. the method for claim 9 wherein changes the size of the bias voltage applied, makes that the impurity class of a curve with respect to doping depth is similar to Gaussian Profile.
15. the method for claim 9, wherein said polysilicon layer is used to limit gate electrode.
16. the method for claim 9 also is included in and forms the conductive layer that comprises metal_based material on the described polysilicon layer that has been doped with described impurity.
17. the method for claim 9, wherein said doping step comprises:
Source gas is provided on described polysilicon layer;
Described source gas is converted into plasma ion; With
By applying described bias voltage, described plasma ion is quickened to described polysilicon layer.
18. the method for claim 17 is wherein utilized boron trifluoride (BF
3) or diborane (B
2H
6) the described source of acquisition gas.
19. the method for claim 9, wherein said polysilicon layer have the degree of depth of about 400 ～about 1200 .
20. the method for claim 19, the size of wherein said each bias voltage change in the scope of about 8kV ± 2kV.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2006-0042509 | 2006-05-11 | ||
| KR20060042509 | 2006-05-11 | ||
| KR1020060042509 | 2006-05-11 | ||
| KR1020070021346 | 2007-03-05 | ||
| KR1020070021346A KR100844957B1 (en) | 2006-05-11 | 2007-03-05 | Method for fabricating semiconductor device |
| KR10-2007-0021346 | 2007-03-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101071768A true CN101071768A (en) | 2007-11-14 |
| CN101071768B CN101071768B (en) | 2010-06-09 |
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ID=38898871
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|---|---|---|---|
| CN2007101068139A Expired - Fee Related CN101071768B (en) | 2006-05-11 | 2007-05-10 | Plasma doping method and method for fabricating semiconductor device using the same |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100844957B1 (en) |
| CN (1) | CN101071768B (en) |
| TW (1) | TWI338915B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8383496B2 (en) | 2008-08-15 | 2013-02-26 | Kazuhiko Tonari | Plasma doping method and manufacturing method of semiconductor device |
| CN105431928A (en) * | 2013-02-06 | 2016-03-23 | 应用材料公司 | Gas injection apparatus and substrate process chamber incorporating same |
| CN105990150A (en) * | 2014-11-06 | 2016-10-05 | 华亚科技股份有限公司 | Method of fabricating source/drain region and semiconductor structure having source/drain region fabricated by the same |
| CN109473347A (en) * | 2018-12-06 | 2019-03-15 | 北京大学 | A method of introducing impurity into silicon and by impurity activation |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101964132B1 (en) * | 2012-10-15 | 2019-04-01 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| KR102483915B1 (en) * | 2017-10-12 | 2023-01-04 | 주성엔지니어링(주) | Method for forming thin film |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07106265A (en) * | 1993-10-06 | 1995-04-21 | Fuji Electric Co Ltd | Manufacture of silicon carbide semiconductor element |
| JPH1012612A (en) | 1996-06-19 | 1998-01-16 | Matsushita Electric Ind Co Ltd | Formation of nitride oxide film |
| US6376348B1 (en) * | 1997-09-30 | 2002-04-23 | Siemens Aktiengesellschaft | Reliable polycide gate stack with reduced sheet resistance and thickness |
| US6020592A (en) * | 1998-08-03 | 2000-02-01 | Varian Semiconductor Equipment Associates, Inc. | Dose monitor for plasma doping system |
| JP3160263B2 (en) * | 1999-05-14 | 2001-04-25 | キヤノン販売株式会社 | Plasma doping apparatus and plasma doping method |
| EP1055745A1 (en) * | 1999-05-27 | 2000-11-29 | Sony Corporation | Method and apparatus for surface modification |
| JP2004047696A (en) * | 2002-07-11 | 2004-02-12 | Matsushita Electric Ind Co Ltd | Method and apparatus for plasma doping, and matching circuit |
| JP4222841B2 (en) * | 2003-01-15 | 2009-02-12 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
-
2007
- 2007-03-05 KR KR1020070021346A patent/KR100844957B1/en not_active IP Right Cessation
- 2007-05-02 TW TW096115529A patent/TWI338915B/en not_active IP Right Cessation
- 2007-05-10 CN CN2007101068139A patent/CN101071768B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8383496B2 (en) | 2008-08-15 | 2013-02-26 | Kazuhiko Tonari | Plasma doping method and manufacturing method of semiconductor device |
| CN102124543B (en) * | 2008-08-15 | 2013-03-13 | 株式会社爱发科 | Plasma doping method and semiconductor device manufacturing method |
| US8440551B2 (en) | 2008-08-15 | 2013-05-14 | Ulvac, Inc. | Plasma doping method and manufacturing method of semiconductor device |
| CN105431928A (en) * | 2013-02-06 | 2016-03-23 | 应用材料公司 | Gas injection apparatus and substrate process chamber incorporating same |
| CN105431928B (en) * | 2013-02-06 | 2018-02-16 | 应用材料公司 | Gas injection apparatus and the substrate processing chamber for being incorporated to gas injection apparatus |
| CN105990150A (en) * | 2014-11-06 | 2016-10-05 | 华亚科技股份有限公司 | Method of fabricating source/drain region and semiconductor structure having source/drain region fabricated by the same |
| CN109473347A (en) * | 2018-12-06 | 2019-03-15 | 北京大学 | A method of introducing impurity into silicon and by impurity activation |
| CN109473347B (en) * | 2018-12-06 | 2021-08-06 | 北京大学 | Method for introducing impurities into silicon and activating impurities |
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| Publication number | Publication date |
|---|---|
| KR20070109802A (en) | 2007-11-15 |
| KR100844957B1 (en) | 2008-07-09 |
| CN101071768B (en) | 2010-06-09 |
| TW200807514A (en) | 2008-02-01 |
| TWI338915B (en) | 2011-03-11 |
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