CN102446763B - MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention provides a MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof; the manufacturing method comprises the following steps of: providing a semiconductor substrate, and forming a grid electrode structure on the semiconductor substrate; forming side walls on the semiconductor substrate at the two sides of the grid electrode structure; forming source/drain regions in the grid electrode structure and the semiconductor substrate at the two sides of the side walls; forming source/drain inversion regions at the bottoms of the source/drain regions, wherein conductive types of doping ions of the source/drain inversion regions are opposite to conductive types of doping ions of the source/drain regions; and annealing, and activating the doping ions of the source/drain regions and the source/drain inversion regions. The manufacturing method provided by the invention is more suitable for an ultra shallow junction manufacturing technology; and according to the manufacturing method, the junction capacitance and the junction leakage current of the MOS transistor are reduced, the response speed of a system is increased when the transistor is applied to a system, and the power consumption of the system is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly transistorized manufacture method.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is manufactured, and it is widely used in various integrated circuits, and the doping type during according to main charge carrier and manufacture is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of manufacture method of MOS transistor.Please refer to Fig. 1 to Fig. 3, is the manufacture method cross-sectional view of the MOS transistor of prior art.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, at the interior formation isolation structure 102 of described Semiconductor substrate 100, the Semiconductor substrate 100 between described isolation structure 102 is active area, forms dopant well 101 in described active area.
Then, form successively gate dielectric layer 105 and grid 106 in the Semiconductor substrate 100 between described isolation structure 102, described gate dielectric layer 105 and grid 106 form grid structure.
Continuation, with reference to figure 1, is carried out oxidation technology, forms the oxide layer 107 that covers described grid structure.
With reference to figure 2, in the Semiconductor substrate of grid structure both sides formation source/drain extension region 108, surround the bag-shaped injection region 104 of described source/drain extension region 108, described source/drain extension region 108 and bag-shaped injection region 104 form by Implantation.After described Implantation completes, carry out annealing process, the doping ion of activation of source/drain extension region 108 and bag-shaped injection region 104.
With reference to figure 3, in the Semiconductor substrate of grid structure both sides, form the side wall 111 of grid structure.Carry out source/leakage Implantation (S/D implant), the interior formation of the Semiconductor substrate 100 source/drain region 109 in grid structure both sides, last, carry out annealing process, the doping ion in activation of source/drain region 109.
In being the Chinese patent application of CN 101789447A, publication number can find more information about prior art.
Find in practice, the MOS transistor of using prior art to make makes the operating rate of system slower in application, and the power consumption of system is larger.
Summary of the invention
The problem that the present invention solves is to provide a kind of MOS transistor and preparation method thereof, operating rate and the power consumption of system when the MOS transistor that described method is made has improved application.
For addressing the above problem, the manufacture method of a kind of MOS transistor of the present invention, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure;
In the Semiconductor substrate of grid structure both sides, form side wall;
Formation source/drain region in the Semiconductor substrate of described grid structure and side wall both sides;
In /Lou inversion regime, formation source, the bottom in described source/drain region, the conduction type of doping ion of /Lou inversion regime, described source and the conductivity type opposite of the doping ion in described source/drain region;
Anneal, activate the doping ion of described source/drain region and /Lou inversion regime, source.
Alternatively, the height of /Lou inversion regime, described source is 0.3～0.8 times of described source/drain region degree of depth.
Alternatively, formation is injected by primary ions in described source/drain region, and when transistor is nmos pass transistor, the conduction type of the doping ion in described source/drain region is N-type, and the conduction type of the doping ion of /Lou inversion regime, described source is P type; When transistor is PMOS transistor, the conduction type of the doping ion in described source/drain region is P type, and the conduction type of the doping ion of /Lou inversion regime, described source is N-type.
Alternatively, the energy range 30～70KeV of the P type of /Lou inversion regime, described source doping ion, dosage range is 1E13～1E14/cm
2; Energy range 20～the 100KeV of the N-type doping ion of /Lou inversion regime, described source, dosage range is 1E13～1E14/cm
2.
Alternatively, described source/drain region forms by twice Implantation, described Implantation is the first Implantation and the second Implantation, the conduction type of the doping ion of described the first Implantation and the second Implantation is identical, the energy of the first Implantation is higher than the energy of the second Implantation, and the dosage of the first Implantation is less than the dosage of the second Implantation.
Alternatively, the order of described the first Implantation, the second Implantation be the first Implantation prior to the second Implantation, or the second Implantation is prior to the first Implantation;
Described source/leakage transoid Implantation is before the first Implantation and the second Implantation, between the first Implantation and the second Implantation or after the first Implantation and the second Implantation.
Alternatively, described transistor is nmos pass transistor, the conduction type of the doping ion of described the first Implantation and the second Implantation is N-type, and the energy range of described the first Implantation is 10～40KeV, and the dosage range of described the first Implantation is 1E13～5E14/cm
2, the energy range of described the second Implantation is 2～15KeV, dosage range is 5E14～3E15/cm
2; The conduction type of the doping ion of described transoid Implantation is P type, and the energy range of described transoid Implantation is 30～70KeV, and dosage range is 1E13～1E14/cm
2.
Alternatively, described transistor is PMOS transistor, the conduction type of the doping ion of described the first Implantation and the second Implantation is P type, and the energy range of described the first Implantation is 5～12KeV, and the dosage range of described the first Implantation is 1E13～2E14/cm
2, the energy range of described the second Implantation is 1～4KeV, dosage range is 5E14～5E15/cm
2; The conduction type of the doping ion of described transoid Implantation is N-type, and the energy range of described transoid Implantation is 10～100KeV, and dosage range is 1E13～1E14/cm
2.
Alternatively, described in be annealed into rapid thermal annealing, the heating rate of described rapid thermal annealing and rate of temperature fall are 50～120 degrees Celsius/second, described rapid thermal annealing utilizes nitrogen to carry out.
The present invention also provides a kind of MOS transistor, comprising:
Semiconductor substrate, described Semiconductor substrate has grid structure;
Side wall, is positioned in the Semiconductor substrate of described grid structure both sides;
Source/drain region, is positioned at the Semiconductor substrate of grid structure and side wall both sides;
/Lou inversion regime, source, is positioned at bottom, the conduction type of doping ion of /Lou inversion regime, described source and the conductivity type opposite of the doping ion in source/drain region in described source/drain region.
Alternatively, /Lou inversion regime, described source height is 0.3～0.8 times of described source/drain region degree of depth.
Compared with prior art, the present invention has the following advantages:
The present invention is formation source/drain region in the Semiconductor substrate of grid structure and side wall both sides, in /Lou inversion regime, formation source, the bottom in described source/drain region, described source/drain region and /Lou inversion regime, source form by Implantation, the conduction type of doping ion of /Lou inversion regime, described source and the conductivity type opposite of the doping ion in source/drain region, utilize impurity compensation effect in source/drain region bottom (being /Lou inversion regime, source) form depletion region, increased the width of depletion region, thereby reduced transistorized source/drain junction electric capacity, reduced source/drain junction current leakage, thereby reduce the RC time constant of transistor when being applied to system, the operating rate of raising system, and improve the power consumption of system,
Further optimally, the doping Implantation of described source/drain region and /Lou inversion regime, source utilizes rapid thermal anneal process to activate, the heating rate of described rapid thermal annealing and rate of temperature fall are 50～120 degrees Celsius/second, described heating rate and rate of temperature fall can be avoided the horizontal proliferation of source/drain region and /Lou inversion regime, source doping ion, prevent device break-through; The gas of described annealing is nitrogen, and the damage can the source of effectively repairing/leakage transoid Implantation causing in Semiconductor substrate, reduces device creepage.
Accompanying drawing explanation
Fig. 1～Fig. 3 is that the MOS transistor of prior art is made cross-sectional view.
Fig. 4 is MOS transistor manufacture method schematic flow sheet of the present invention.
Fig. 5～Fig. 8 is MOS transistor manufacture method cross-sectional view of the present invention.
Fig. 9 is that the CMOS transistor AND gate prior art of the making of the present invention transistorized junction capacitance of CMOS of making is with grid length change curve.
Embodiment
The MOS transistor that prior art is made makes the operating rate of system slower when being applied to system, and the power consumption of system is larger.Through inventor, study discovery, the transistorized RC time constant of making due to prior art is large, makes the operating rate of system slow; The transistorized leakage current of making due to prior art is large, makes the power consumption of system high.Inventor further studies, and finding to cause the large and large reason of leakage current of described transistorized RC time constant is that transistorized source/drain junction electric capacity and the junction leakage of prior art making is larger.
Inventor also finds, along with dwindling of device feature size, the degree of depth that need to be by reducing source/drain region is to make super shallow junction.This need to reduce the energy of source/leakage Implantation.But the energy that reduces source/leakage Implantation strengthens the activation difficulty of the doping ion in source/drain region, the ion that even partly adulterates cannot activate, thereby the resistance in source/drain region is strengthened, resistance increasing for the source of preventing/drain region, need to be by the dosage of increasing source/leakage Implantation, needing provides low-yield, source/leakage ion implantation technology of high dose, to form the source/drain region that meets technological requirement, but existing ion implantation technology cannot meet above-mentioned requirements, make the degree of depth in source/drain region that existing source/leakage Implantation forms bigger than normal, and be not subject to technology controlling and process.And the dosage in source/drain region strengthens, and makes the doping ion in source/drain region in existing annealing, have the problem of horizontal proliferation, thereby may cause transistor break-through.In order to address the above problem, inventor, through creative work, proposes a kind of manufacture method of MOS transistor, and described method is utilized transoid Implantation, form the degree of depth and be less than the /Lou inversion regime, source in source/drain region, thereby reduce the actual grade in the final source/drain region obtaining.
The manufacture method of a kind of MOS transistor of the present invention, please refer to Fig. 4, and described method comprises:
Step S1, provides Semiconductor substrate, in described Semiconductor substrate, is formed with grid structure;
Step S2 forms side wall in the Semiconductor substrate of grid structure both sides;
Step S3, formation source/drain region in the Semiconductor substrate of described grid structure and side wall both sides;
Step S4, in /Lou inversion regime, formation source, the bottom in described source/drain region, the conduction type of doping ion of /Lou inversion regime, described source and the conductivity type opposite of the doping ion in described source/drain region;
Step S5, anneals, and activates the doping ion of described source/drain region and /Lou inversion regime, source.
Below in conjunction with specific embodiments technical scheme of the present invention is described in detail.Incorporated by reference to accompanying drawing 5～Fig. 8, it is the MOS transistor manufacture method cross-section structure schematic flow sheet of one embodiment of the invention.
First, please refer to Fig. 5, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, be formed with grid structure.
The material of described Semiconductor substrate 200 can be silicon, germanium silicon, silicon-on-insulator etc.In the present embodiment, in described Semiconductor substrate 200, be formed with at least two isolation structures 202, described isolation structure 202 is for isolation mutually between device.Described isolation structure 202 is fleet plough groove isolation structure (STI) or local oxidation structure.
Semiconductor substrate between described isolation structure 202 is transistorized active area.
In other embodiment, in the Semiconductor substrate between described isolation structure 202, be also formed with dopant well 201, Channeling implantation district, threshold voltage injection region.Described dopant well 201, Channeling implantation district, threshold voltage injection region form by Implantation, the type of the doping ion of described dopant well 201, Channeling implantation district, threshold voltage injection region is relevant with the conducting channel type of MOS transistor to be formed, known technology as those skilled in the art, is not described in detail at this.
Described grid structure is in the Semiconductor substrate 200 between adjacent isolation structure 202.Described grid structure comprises the gate dielectric layer 205 being positioned in Semiconductor substrate 200 and the polysilicon gate 206 that is positioned at described gate dielectric layer 205 tops.The material of described gate dielectric layer 205 is silica, silicon oxynitride etc.The manufacture method of described gate dielectric layer 205 and polysilicon gate 206 is same as the prior art, and as those skilled in the art's known technology, therefore not to repeat here.
As preferred embodiment, described grid structure outside is also coated with side wall spacer 207 (offset spacer), and described side wall spacer 207 can be by carrying out oxidation technology making to described polysilicon gate 206.Described side wall spacer 207, for the protection of described grid structure, avoids described grid structure to be subject to the damage of etching technics.
Then, please refer to Fig. 6, in the Semiconductor substrate of described grid structure both sides, form light doping section 208.
Described light doping section 208 forms by light dope Implantation.The conduction type of the doping ion of described light doping section 208 is relevant with the conducting channel of MOS transistor to be formed.Particularly, when transistor to be formed is nmos pass transistor, the conduction type of the doping ion of described light doping section 208 is N-type, and described doping ion can be phosphonium ion, arsenic ion or antimony ion, the energy range of light dope Implantation is 1～30KeV, and dosage range is 1E13～2E15/cm
2.When transistor to be formed is PMOS transistor, the conduction type of the doping ion of described light doping section 208 is P type, described doping ion can be boron ion, boron difluoride ion, the energy range 1～20KeV of light dope Implantation, and dosage range is 1E13～2E15/cm
2.
When the transistor that will form is nmos pass transistor, as an embodiment, the doping ion of the doping ion of described light doping section 208 is phosphonium ion, and the energy range of light dope Implantation is 1～4KeV, and dosage range is 4E14～2E15/cm
2; As another embodiment, the doping ion of described light doping section 208 is arsenic ion, and the Implantation Energy scope of doping Implantation is 6～10KeV, and dosage range is 1E14～1E15/cm
2.
When the transistor that will form is PMOS transistor, as an embodiment, the doping ion of described light doping section 208 is boron ion, and the energy range of light dope Implantation is 2～5KeV, and dosage range is 5E14～2E15/cm
2; As another embodiment, the doping ion of described light doping section 208 is indium ion, and the energy range of light dope Implantation is 1～35KeV, and dosage range is 1E13～1E14/cm
2.
In order to prevent transistor break-through, reduce short-channel effect and the anti-short-channel effect of device, as preferred embodiment, after carrying out light dope Implantation, need to carry out bag-shaped Implantation (pocket implant), form the bag-shaped injection region 204 that surrounds described light doping section 208.The conduction type of the doping ion of described bag-shaped injection region 204 and the conductivity type opposite of light doping section 208.
In order to guarantee that the bag-shaped injection region 204 forming can surround described light doping section 204, it is that 10～30 degree inject that described bag-shaped injection region 204 should adopt angle of inclination.
In the present embodiment, after described light doping section 208 and 204 formation of bag-shaped injection region, carry out annealing steps, to activate the doping ion in described light doping section 208 and bag-shaped injection region 204.Described annealing is preferably rapid thermal annealing.As an embodiment, the gas of described annealing adopts nitrogen, and the heating rate of described annealing and rate of temperature fall scope are 50～120 degrees Celsius/second, effectively to activate the doping ion in described light doping section 208 and bag-shaped injection region 204.
Then, please refer to Fig. 7, in the Semiconductor substrate of described grid structure both sides, form side wall 211.In the present embodiment, described side wall 211 can be single layer structure, and its material is silicon nitride.In other embodiments, described side wall 211 can also be sandwich construction, for example, be the ONO structure that silica-silicon-nitride and silicon oxide forms.
The manufacture method of described side wall 211 is same as the prior art, and the known technology as those skilled in the art, is not described in detail at this.
Then, still with reference to figure 7, formation source/drain region 209 in the Semiconductor substrate of described grid structure and side wall 211 both sides.Described source/drain region 209 forms by ion implantation technology.Formation can be injected by primary ions in described source/drain region 209, also can form by twice or twice above Implantation.
As an embodiment, formation is injected by primary ions in described source/drain region 209.Particularly, when transistor is nmos pass transistor, the conduction type of the doping ion in described source/drain region 209 is N-type, and described N-type ion can be P ion, AS ion; When transistor is PMOS transistor, the conduction type of the doping ion in described source/drain region 209 is P type, and the conduction type of described doping ion can be B ion, BF
2ion.
As another embodiment of the present invention, described source/drain region 209 forms by twice Implantation.Particularly, described source/drain region 209 forms by twice Implantation, described Implantation is the first Implantation and the second Implantation, the conduction type of the doping ion of described the first Implantation and the second Implantation is identical, the energy of wherein said the first Implantation is higher than the energy of the second Implantation, and the dosage of the first Implantation is less than the dosage of the second Implantation.
When described transistor is nmos pass transistor, the conduction type of the doping ion of described the first Implantation and the second Implantation is N-type, and the doping ion of described the first Implantation and the second Implantation can be P ion, AS ion or Sb ion.The energy range of described the first Implantation is 10～40KeV, and the dosage range of described the first Implantation is 1E13～5E14/cm
2, described in state the second Implantation energy range be 2～15KeV, dosage range is 5E14～3E15/cm
2.For example, the doping ion of described the first Implantation can be P ion, and its energy range is 10～40KeV, and dosage range is 1E13～2E14/cm
2, the doping ion of described the second Implantation can P ion, and its energy range is 5E13～3E15/cm
2; Or the doping ion of described the first Implantation can be AS ion, its energy range is 10～40KeV, and dosage range is 3E13～5E14/cm
2, the doping ion of described the second Implantation can be P ion, and its energy range is 10～40KeV, and dosage range is 1E15～3E15cm/
2.
Described transistor is PMOS transistor, and the conduction type of the doping ion of described the first Implantation and the second Implantation is P type, described the first Implantation and the doping ion of the second Implantation can be B ion, BF
2ion, In ion.The energy range of described the first Implantation is 5～12KeV, and the dosage range of described the first Implantation is 1E13～2E14/cm
2, described in state the second Implantation energy range be 1～4KeV, dosage range is 5E14～5E15/cm
2.For example, when the doping ion of described the first Implantation is B ion, its energy range is 5～12KeV, and dosage range is 1E13～2E14/cm
2, the doping ion of described the second Implantation can B ion, and its energy range is 6E14～5E15/cm
2.
It should be noted that, for nmos pass transistor or PMOS transistor, because the degree of depth of the first Implantation is greater than the degree of depth of the second Implantation, the dosage of the second Implantation is greater than the dosage of the first Implantation, and the dosage of the second Implantation is conventionally than large 1～2 order of magnitude of the dosage of the first Implantation (the dosage of the second Implantation is 10～100 times of the first ion implantation dosage), therefore, the resistance in source/drain region 209 is mainly determined by the dopant dose of the second Implantation, the doping ion of described the second Implantation is as the Effective Doping ion in source/drain region 209, the doping ion of described the first Implantation is for the degree of depth in control source/drain region 209, the doping ion distribution of described the first Implantation is 209 bottom in source/drain region.The degree of depth of the doping ion of described the first Implantation is 0.3～0.8 times of the doping ion degree of depth of the second Implantation.
The order of the first Implantation of the present invention, the second Implantation can be for the first Implantation be prior to the second Implantation, or the second Implantation is prior to the first Implantation.As preferred embodiment, described the first Implantation forms prior to the second Implantation, such the first Implantation has destroyed the lattice structure of original Semiconductor substrate, when the second Implantation, the resistance that the doping ion of described the second Implantation is subject to is large, thereby the degree of depth of the second ion shoals, the effective depth in source/drain region 209 is shoaled, optimize the distribution of the doping ion in source/drain region 209, at source/drain region 209 resistance, constant in the situation that, be more conducive to make super shallow junction.
In practice, described source/drain region 209 can also form by 3 times or more times Implantation.The energy that wherein primary ions is injected should be greater than the energy of all the other Implantations, the energy of described all the other Implantations should be identical or approaches (deviation is no more than 10%), the dosage that the dosage sum of described all the other Implantations should be injected much larger than described wherein primary ions, 10～100 times of the dosage sum of described all the other Implantations dosage that wherein primary ions is injected described in should be.
Then, please refer to Fig. 8, in /Lou inversion regime, formation source, the bottom in described source/drain region 209 212, as shown in dash area in Fig. 8./Lou inversion regime, described source 212 forms by Implantation, the conduction type of doping ion of /Lou inversion regime, described source 212 and the conductivity type opposite of the doping ion in source/drain region 209, utilize the conduction type of doping ion and the conductivity type opposite in source/drain region 209 of /Lou inversion regime, source 212, produce impurity compensation effect, thereby 209 the formation depletion region, bottom in source/drain region, increase the width of the depletion region between original source/drain region 209 and Semiconductor substrate 200, thereby reduce source/drain junction electric capacity.
As an embodiment, the height of /Lou inversion regime, described source 212 is 0.3～0.7 times of the degree of depth in described source/drain region 209.The doping ion with the doping ion in source/drain region 209 with films of opposite conductivity is injected in bottom in described source/drain region 209, while forming /Lou inversion regime 212, described source, being distributed as of the doping ion of described Implantation: downward from semiconductor substrate surface, 209 the depth direction along source/drain region, the concentration first increases and then decreases of described doping ion, be Gaussian Profile, the peak concentration of wherein said impurity is positioned at /Lou inversion regime, described source 212.Near source/drain region 209 described peak concentration, because the concentration of doping ion is higher, thereby produce impurity compensation effect, form depletion region, region away from described peak concentration, because the concentration of described doping ion is less, little to the impurity compensation effect of the doping ion in described source/drain region 209, substantially do not affect the conduction type in described source/drain region 209.The present invention forms the parameter of the Implantation of /Lou inversion regime, described source 212 by adjustment, make described doping ion peak value be positioned at /Lou inversion regime, described source 212, and the distribution of described doping ion is concentrated and /Lou inversion regime, source 212, make so that the height of the final /Lou inversion regime, source 212 forming is 0.3～0.7 times of the degree of depth in described source/drain region 209.
The technological parameter of the Implantation of /Lou inversion regime, described source 212 is corresponding with the technological parameter in formation source/drain region 209.Particularly, when formation is injected by primary ions in described source/drain region 209, and when described transistor is nmos pass transistor, the conduction type of the doping ion of /Lou inversion regime, described source 212 is P type, the doping ion of /Lou inversion regime, described source 212 can be In ion, energy range 30～the 70KeV of the doping ion of /Lou inversion regime, described source 212, dosage range is 1E13～1E14/cm
2; When formation is injected by primary ions in described source/drain region 209, and when described transistor is PMOS transistor, the conduction type of the doping ion of /Lou inversion regime, described source 212 is N-type, the doping ion of /Lou inversion regime, described source 212 can be Sb ion, its energy range is 40～100KeV, and dosage range is 1E13～1E14/cm
2, the doping ion of /Lou inversion regime, described source 212 can be also As ion, the energy range 20～50KeV of the doping ion of /Lou inversion regime, described source 212, and dosage range is 1E13～1E14/cm
2.
When described source/drain region 209 forms by more than twice or twice Implantation, the injection parameter setting of /Lou inversion regime, described source 212 can be injected the technique forming in reference source/drain region 209 by primary ions, at this, do not repeat.
It should be noted that, the order that forms the Implantation of /Lou inversion regime, described source 209 and the Implantation in formation source/drain region 209 can be changed arbitrarily, and the Implantation that forms /Lou inversion regime, described source 209 can be before the Implantation in formation source/drain region 209, (if source/drain region 209 is formed by Implantation repeatedly) between the Implantation in formation source/drain region 209 or after forming the Implantation in source/drain region 209.
Then, still, with reference to figure 8, anneal, activate the doping ion of /Lou doped region, 209He source, described source/drain region 212.
Described annealing can, for rapid thermal annealing or boiler tube annealing, be preferably rapid thermal annealing.Because the rapid thermal anneal process time is short, efficiency is high, be therefore preferably rapid thermal annealing.As preferred embodiment, the heating rate of described rapid thermal annealing and rate of temperature fall are 50～120 degrees Celsius/second, within the scope of above-mentioned heating rate and rate of temperature fall, can effectively activate the doping ion of /Lou inversion regime, 209He source, described source/drain region 212, repair the damage that ion implantation technology causes in Semiconductor substrate 100, and, can not cause the doping ion horizontal proliferation of /Lou inversion regime, 209He source, described source/drain region 212, prevent device break-through.
In the present embodiment, the gas of described annealing is nitrogen.Described nitrogen can effectively be repaired the damage that ion implantation technology causes at semiconductor substrate surface.In other embodiment, the gas of described annealing process can also be the mist of nitrogen and oxygen, and wherein the volume ratio in mist of oxygen is 1%～10%, to protect Semiconductor substrate 200 surfaces, reduces implantation dosage loss.
Based on said method, as shown in Figure 8, described MOS transistor comprises the MOS transistor of making:
Dopant well 201, in the Semiconductor substrate 200 between adjacent isolation structures 202;
Grid structure, is positioned at the semiconductor substrate surface of described dopant well 201 tops, and described isolation structure comprises the polysilicon gate 206 that is positioned at described semiconductor substrate surface gate dielectric layer 205 and is positioned at described gate dielectric layer 205 tops;
Bag-shaped injection region 204, is positioned at the Semiconductor substrate 200 of described grid structure both sides, and described bag-shaped injection region 204 surrounds described light doping sections 208;
Source/drain region 209, is positioned at the Semiconductor substrate 200 of described grid structure and side wall 211 both sides;
/Lou inversion regime, source 212, be positioned at the Semiconductor substrate 200 of described grid structure and side wall 211 both sides, /Lou inversion regime, described source 212 is positioned at the bottom in described source/drain region 209, and /Lou inversion regime, described source 212 doping ions have contrary conduction type with the doping ion in described source/drain region 209.
Wherein, as preferred embodiment, the height of /Lou inversion regime, described source 212 is 0.3～0.8 times of described source/drain region 209 degree of depth.
Inventor has carried out WAT test, in the situation that other process conditions are identical, (only increase source/leakage transoid Implantation), utilizing the junction capacitance of the MOS transistor of manufacture method acquisition of the present invention is the every square micron of 1.37 pico farad, and utilize the junction capacitance of the MOS transistor of prior art making, be the every square micron of 1.5 pico farad, method of the present invention reduces approximately 7% by the junction capacitance of MOS transistor.
In order to further illustrate the junction capacitance of the MOS transistor of the present invention's making, change, inventor simulates, and the junction capacitance of the MOS transistor that the MOS transistor that the present invention is made and prior art are made changes and simulates with grid length.Please refer to Fig. 9, wherein transverse axis represents grid length, unit is micron, the longitudinal axis represents transistorized junction capacitance, unit is the every square micron of pico farad, curve B is the curve chart that utilizes the junction capacitance of the MOS transistor that prior art makes to change with grid length, and curve A is the curve chart that utilizes the junction capacitance of the MOS transistor that method of the present invention makes to change with grid length.As seen from the figure, in the situation that grid length is identical, utilize the junction capacitance of the MOS transistor that method of the present invention makes to be less than the junction capacitance of the MOS transistor that prior art makes.
To sum up, MOS transistor provided by the invention and preparation method thereof, described method is utilized the doping ion of /Lou inversion regime, source of bottom, source/drain region and the conductivity type opposite of the doping ion in source/drain region, realize impurity compensation, in formation depletion region, /Lou inversion regime, source, increased the width of source/drain depletion region, reduced source/drain junction electric capacity and leakage current, improve the response speed of transistor application system when system, reduced the power consumption of system.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (6)
1. a manufacture method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure;
In the Semiconductor substrate of grid structure both sides, form side wall;
Formation source/drain region in the Semiconductor substrate of described grid structure and side wall both sides;
In /Lou inversion regime, formation source, the bottom in described source/drain region, the conduction of the doping ion of /Lou inversion regime, described source
The conductivity type opposite of the doping ion in type and described source/drain region;
Anneal, activate the doping ion of described source/drain region and /Lou inversion regime, source;
Described source/drain region forms by twice Implantation, described Implantation is the first Implantation and the second Implantation, the conduction type of the doping ion of described the first Implantation and the second Implantation is identical, the energy of the first Implantation is higher than the energy of the second Implantation, and the dosage of the first Implantation is less than the dosage of the second Implantation;
The order of described the first Implantation, the second Implantation be the first Implantation prior to the second Implantation, or the second Implantation is prior to the first Implantation;
Described source/leakage transoid Implantation is before the first Implantation and the second Implantation, between the first Implantation and the second Implantation or after the first Implantation and the second Implantation;
Described transistor is nmos pass transistor, and the conduction type of the doping ion of described the first Implantation and the second Implantation is N-type, and the energy range of described the first Implantation is 10～40KeV, and the dosage range of described the first Implantation is 1E13～5E14/cm
2, the energy range of described the second Implantation is 2～15KeV, dosage range is 5E14～3E15/cm
2; The conduction type of the doping ion of described transoid Implantation is P type, and the energy range of described transoid Implantation is 30～70KeV, and dosage range is 1E13～1E14/cm
2.
2. the manufacture method of MOS transistor as claimed in claim 1, is characterized in that, the height of /Lou inversion regime, described source is 0.3～0.8 times of described source/drain region degree of depth.
3. the manufacture method of MOS transistor as claimed in claim 1, is characterized in that, described in be annealed into rapid thermal annealing, the heating rate of described rapid thermal annealing and rate of temperature fall are 50～120 degrees Celsius/second, described rapid thermal annealing utilizes nitrogen to carry out.
4. a manufacture method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with grid structure;
In the Semiconductor substrate of grid structure both sides, form side wall;
Formation source/drain region in the Semiconductor substrate of described grid structure and side wall both sides;
In /Lou inversion regime, formation source, the bottom in described source/drain region, the conduction of the doping ion of /Lou inversion regime, described source
The conductivity type opposite of the doping ion in type and described source/drain region;
Anneal, activate the doping ion of described source/drain region and /Lou inversion regime, source;
Described source/drain region forms by twice Implantation, described Implantation is the first Implantation and the second Implantation, the conduction type of the doping ion of described the first Implantation and the second Implantation is identical, the energy of the first Implantation is higher than the energy of the second Implantation, and the dosage of the first Implantation is less than the dosage of the second Implantation;
The order of described the first Implantation, the second Implantation be the first Implantation prior to the second Implantation, or the second Implantation is prior to the first Implantation;
Described source/leakage transoid Implantation is before the first Implantation and the second Implantation, between the first Implantation and the second Implantation or after the first Implantation and the second Implantation;
Described transistor is PMOS transistor, and the conduction type of the doping ion of described the first Implantation and the second Implantation is P type, and the energy range of described the first Implantation is 5～12KeV, and the dosage range of described the first Implantation is 1E13～2E14/cm
2, the energy range of described the second Implantation is 1～4KeV, dosage range is 5E14～5E15/cm
2; The conduction type of the doping ion of described transoid Implantation is N-type, and the energy range of described transoid Implantation is 10～100KeV, and dosage range is 1E13～1E14/cm
2.
5. the manufacture method of MOS transistor as claimed in claim 4, is characterized in that, the height of /Lou inversion regime, described source is 0.3～0.8 times of described source/drain region degree of depth.
6. the manufacture method of MOS transistor as claimed in claim 4, is characterized in that, described in be annealed into rapid thermal annealing, the heating rate of described rapid thermal annealing and rate of temperature fall are 50～120 degrees Celsius/second, described rapid thermal annealing utilizes nitrogen to carry out.
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| EP0683531A3 (en) * | 1994-05-16 | 1996-02-28 | Samsung Electronics Co Ltd | MOSFET with LDD structure and manufacturing method therefor. |
| US5536957A (en) * | 1990-01-16 | 1996-07-16 | Mitsubishi Denki Kabushiki Kaisha | MOS field effect transistor having source/drain regions surrounded by impurity wells |
| CN101312208A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and method for forming same |
| CN101459082A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and forming method thereof |
| CN101621071A (en) * | 2008-07-04 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and manufacturing method thereof |
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|---|---|---|---|---|
| US5536957A (en) * | 1990-01-16 | 1996-07-16 | Mitsubishi Denki Kabushiki Kaisha | MOS field effect transistor having source/drain regions surrounded by impurity wells |
| EP0683531A3 (en) * | 1994-05-16 | 1996-02-28 | Samsung Electronics Co Ltd | MOSFET with LDD structure and manufacturing method therefor. |
| CN101312208A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and method for forming same |
| CN101459082A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | MOS transistor and forming method thereof |
| CN101621071A (en) * | 2008-07-04 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and manufacturing method thereof |
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