CN102938375B - Field effect transistor and forming method thereof - Google Patents
Field effect transistor and forming method thereof Download PDFInfo
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- CN102938375B CN102938375B CN201110233388.6A CN201110233388A CN102938375B CN 102938375 B CN102938375 B CN 102938375B CN 201110233388 A CN201110233388 A CN 201110233388A CN 102938375 B CN102938375 B CN 102938375B
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Abstract
Provided are a field effect transistor and a forming method thereof. The field effect transistor comprises a semiconductor substrate, a gate structure, a light ion injection area, a light doping source/drain region and a heavy doping source/drain region, wherein the gate structure is located on a surface of the semiconductor substrate, a surface of a lateral wall of the gate structure forms a lateral wall, the light ion injection area is located in the semiconductor substrate on two sides of the gate structure, a light ion comprises at least two of a nitrogen ion, a carbon ion and a fluorion iron, the light doping source/drain region is located in the semiconductor substrate on two sides of the gate structure, the depth of a light doping region is smaller than the depth of the light ion injection area, and the heavy doping source/drain region is arranged in the semiconductor substrate on two sides of the lateral wall. The light ion can restrain spreading of foreign ions in the light doping source/drain region to enable junction depth of the formed light doping source/drain region to be shallow and abrupt, remits a short-channel effect and improves electrical properties of the field effect transistor.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of field-effect transistor and formation method.
Background technology
Ion implantation technique is a kind of impurity doping techniques being widely used in various semiconductor device and production of integrated circuits.By controlling the magnitude of current and the voltage that inject ion beam, can the Content and distribution situation of accurate adjustment impurity in target substrate.After ion implantation, annealing in process is carried out to activate the ion injected to described Semiconductor substrate, and the target substrate lattice damage caused when repairing ion implantation.Along with the development of semiconductor technology, the characteristic size of device becomes more and more less, and the longitudinal size (i.e. the degree of depth of device) of device is also in scaled down.At present, usually Formation Depth is needed to be less than the even less for ultra-shallow junctions of 1000 dusts (Ultra Shallow Junctions in semiconductor process, USJ), utilize traditional ion implantation technology usually can not obtain gratifying for ultra-shallow junctions structure, there is following problem the light dope source/drain region utilizing ion implantation to form for ultra-shallow junctions:
(1) because common ion implantation making for ultra-shallow junctions is more difficult, ultra-low calorie implanting impurity ion must be adopted, but foreign ion activity ratio when activated at that ultra-low calorie injects is lower.
(2) after annealed process, foreign ion in described for ultra-shallow junctions can spread, and because the enhanced diffustion effect injecting ion (can cause the damage of lattice due to Semiconductor substrate and cause defect when foreign ion injects, when high annealing, the diffusion length of described foreign ion can increase greatly, cause enhanced diffustion effect), described junction depth is deepened, the channel region length of field-effect transistor diminishes, easily cause short-channel effect (Short Channel Effects, SCE).
In order to solve the problem, publication number is that the american documentation literature of US2008/0233687A1 discloses a kind of method forming field-effect transistor, comprising: etch the Semiconductor substrate of described field effect transistor grid structure both sides, forms shallow trench; Improve the oxygen content of the Semiconductor substrate of described shallow trench inwall, then in described shallow trench extension layer containing the epitaxial loayer of Doped ions, because the Semiconductor substrate with certain oxygen content can suppress the diffusion of Doped ions in epitaxial loayer, described Doped ions can be limited in epitaxial loayer, produce more shallow and more precipitous knot.But because described method needs to form epitaxial loayer, improve the complexity of technique, and well can not solve the enhanced diffustion effect injecting ion.
Summary of the invention
The problem that the present invention solves is to provide a kind of field-effect transistor and formation method, by carrying out light ion injection to the Semiconductor substrate of source/drain region to be formed, suppress the diffusion of the Doped ions forming light dope source/drain region, alleviate the short-channel effect of field-effect transistor.
For solving the problem, technical solution of the present invention provides a kind of field-effect transistor formation method, comprising:
Semiconductor substrate is provided;
Grid structure is formed at described semiconductor substrate surface;
Semiconductor substrate region in described grid structure both sides injects light ion, and described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds;
Semiconductor substrate region in described grid structure both sides forms light dope source/drain region, and the degree of depth of described light dope source/drain region is less than the degree of depth of described light ion injection;
Side wall is formed on described gate structure sidewall surface;
Heavy doping source/drain region is formed in the Semiconductor substrate of described side wall both sides;
Annealing in process is carried out to described Semiconductor substrate.
Optionally, when carbon ion or Nitrogen ion or both mixtures and fluorine ion are together injected into the semiconductor substrate region of described grid structure both sides, described fluorine ion is larger than the angle of inclination of Nitrogen ion, carbon ion implatation, makes the injection zone of fluorine ion can extend into channel region below grid structure.
Optionally, when carbon ion or fluorine ion or both mixtures and Nitrogen ion are together injected into the semiconductor substrate region of described grid structure both sides, the injection depth ratio fluorine ion of described Nitrogen ion, the injection degree of depth of carbon ion are large.
Optionally, the technological parameter of described injection light ion is: the dosage range of injection is 5E14atom/cm
2~ 1E15atom/cm
2, the energy range of injection is 4KeV ~ 20KeV, and the range of tilt angles of injection is 0 ° ~ 15 °.
Optionally, different light ions adopts same technique to inject simultaneously or adopts different process step separately to inject.
Optionally, also comprise, before described injection light ion, carry out pre-amorphous injection in the semiconductor substrate region of described grid structure both sides, the degree of depth of described pre-amorphous injection is greater than the degree of depth of described light dope source/drain region.
Optionally, when field-effect transistor to be formed is PMOS transistor, the ion of described pre-amorphous injection is titanium ion, the mixture of indium ion or indium ion; When field-effect transistor to be formed is nmos pass transistor, the ion of described pre-amorphous injection is titanium ion, the mixture of antimony ion or antimony ion.
Optionally, the technological parameter of described pre-amorphous injection is: the dosage range of injection is 5E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 5KeV ~ 50KeV, and the range of tilt angles of injection is 2 ° ~ 23 °.
Optionally, the concrete technology of described formation light dope source/drain region is: in the semiconductor substrate region of described grid structure both sides, inject N-type impurity ion or p type impurity ion, and the dosage range of injection is 2E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 0.5KeV ~ 4KeV, and the range of tilt angles of injection is 0 ° ~ 15 °.
Optionally, described annealing in process is carried out after described formation light dope source/drain region, or carries out after described formation heavy doping source/drain region, or carries out respectively after above-mentioned two steps.
Optionally, described annealing in process comprises heating furnace annealing, rapid thermal annealing, spike annealing are wherein a kind of.
The embodiment of the present invention additionally provides a kind of field-effect transistor, comprising:
Semiconductor substrate;
Be positioned at the grid structure of described semiconductor substrate surface, the sidewall surfaces of described grid structure is formed with side wall;
Be positioned at the light ion injection zone of the Semiconductor substrate of described grid structure both sides, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds;
Be positioned at the light dope source/drain region of the Semiconductor substrate of described grid structure both sides, the degree of depth of described light doping section is less than the degree of depth of described light ion injection zone;
Be positioned at the heavy-doped source drain region of the Semiconductor substrate of described side wall both sides.
Optionally, described light ion at least comprises fluorine ion, and the injection zone of described fluorine ion extend into the channel region below grid structure.
Optionally, described light ion at least comprises Nitrogen ion, and the injection depth ratio fluorine ion of described Nitrogen ion, the injection degree of depth of carbon ion are large.
Optionally, also comprise, be positioned at the non-crystallization region of the Semiconductor substrate of described grid structure both sides, the degree of depth of described non-crystallization region is greater than the degree of depth of described light dope source/drain region.
Optionally, when field-effect transistor to be formed is PMOS transistor, the foreign ion of described non-crystallization region is mixture or the indium ion of titanium ion and indium ion; When field-effect transistor to be formed is nmos pass transistor, the foreign ion of described non-crystallization region is mixture or the antimony ion of titanium ion and antimony ion.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention is by carrying out light ion injection to the Semiconductor substrate of source/drain region to be formed, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds, owing to being injected into the Nitrogen ion of described Semiconductor substrate, carbon ion, fluorine ion can form particle trap, original position is fixed on the effective ion of particle trap described in making, even if high annealing also not easily spreads, inhibit the N-type of injection or the enhanced diffustion effect of p type impurity ion, define comparatively precipitous and more shallow knot, improve the electric property of field-effect transistor.
Further, the embodiment of the present invention also carries out pre-amorphous injection to the Semiconductor substrate of source/drain region to be formed, because the lattice structure in decrystallized Semiconductor substrate is irregular, the P type of follow-up injection or N-type impurity ion not by periodic lattice arrangement void diffusion to the darker degree of depth, inhibit the diffusion of the foreign ion of light dope source/drain region; And described pre-amorphous injection can form vacancy in the lattice structure of Semiconductor substrate, makes the P type of follow-up injection or N-type impurity ion can occupy vacancy more easily, thus improve the activity ratio of light dope source/drain region P type or N-type impurity ion.In follow-up annealing in process, decrystallized Semiconductor substrate recrystallization, can reduce the impedance of source/drain region, improves the operating current of field-effect transistor.Utilize titanium ion as the injection ion of pre-amorphous injection, after titanium ion annealed process formation titanium silicide, the vacancy that titanium silication is formed can eliminate the defect that ion implantation process medium range terminal produces, and improves the yield of product.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of a kind of field-effect transistor formation method of the embodiment of the present invention;
Fig. 2 to Fig. 9 is the cross-sectional view of a kind of field-effect transistor formation method of the embodiment of the present invention;
Figure 10 is the test result comparison diagram of one embodiment of the invention PMOS transistor formed and the PMOS transistor utilizing prior art to be formed.
Embodiment
Because the Doped ions injected when forming the light dope source/drain region of field-effect transistor in prior art easily spreads, be not easy to form more shallow and more precipitous knot, inventor, through having researched and proposed a kind of field-effect transistor formation method, comprising: provide Semiconductor substrate; Grid structure is formed at described semiconductor substrate surface; Semiconductor substrate region in described grid structure both sides injects light ion, and described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds; Semiconductor substrate region in described grid structure both sides forms light dope source/drain region, and the degree of depth of described light dope source/drain region is less than the degree of depth of described light ion injection; Side wall is formed on described gate structure sidewall surface; Heavy doping source/drain region is formed in the Semiconductor substrate of described side wall both sides; Annealing in process is carried out to described Semiconductor substrate.Because the degree of depth of the depth ratio light dope source/drain region of the light ion of described injection is large, and described in be injected into the Nitrogen ion of described Semiconductor substrate, carbon ion, fluorine ion can serve as particle trap, original position is all fixed on the effective ion of particle trap described in making, even if high annealing also not easily spreads, inhibit the enhanced diffustion effect injecting ion, form more shallow and more precipitous knot, improve the electric property of field-effect transistor.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Please refer to Fig. 1, be the schematic flow sheet of the field-effect transistor formation method of the embodiment of the present invention, specifically comprise:
Step S101, provides Semiconductor substrate;
Step S102, forms grid structure at described semiconductor substrate surface;
Step S103, carries out pre-amorphous injection in the Semiconductor substrate of described grid structure both sides;
Step S104, injects light ion in the Semiconductor substrate of described grid structure both sides, and described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds;
Step S105, forms light dope source/drain region in the Semiconductor substrate of described grid structure both sides, and the degree of depth of described light dope source/drain region is less than the degree of depth of described light ion injection;
Step S106, forms side wall on described gate structure sidewall surface;
Step S107, forms heavy doping source/drain region in the Semiconductor substrate of described side wall both sides;
Step S108, carries out annealing in process to described Semiconductor substrate.
Fig. 2 to Fig. 9 is the cross-sectional view of the field-effect transistor formation method of the embodiment of the present invention.
Please refer to Fig. 2, Semiconductor substrate 100 is provided.Described Semiconductor substrate 100 is silicon substrate, silicon-Germanium substrate, silicon-on-insulator substrate one wherein.In the present embodiment, described Semiconductor substrate 100 is silicon substrate.Those skilled in the art can select the type of described Semiconductor substrate 100 according to semiconductor device to be formed, therefore the type of described Semiconductor substrate should too not limit the scope of the invention.
Also be formed with fleet plough groove isolation structure (not shown) in described Semiconductor substrate 100, described fleet plough groove isolation structure between adjacent device, for the device that electric isolution is adjacent.The concrete formation process of described fleet plough groove isolation structure is the known technology of those skilled in the art, does not repeat them here.
Still continue with reference to figure 2, form grid structure 200 on described Semiconductor substrate 100 surface.
Described grid structure 200 comprises the gate oxide 210 being positioned at described Semiconductor substrate 100 surface, the gate electrode 220 being positioned at described gate oxide 210 surface.The material of described gate oxide 210 is silica or high dielectric material, and the material of described gate electrode 220 is polysilicon, the polysilicon of doping or metal.In other embodiments, silicon oxide layer or silicon nitride layer is formed on described grid structure surface, utilize described silicon oxide layer or silicon nitride layer that follow-up ion implantation technology can be prevented to be injected in gate oxide or gate electrode by foreign ion, affect the electric property of described grid structure.Because the formation method of described grid structure is the known technology of those skilled in the art, do not repeat them here.
Please refer to Fig. 3, in the Semiconductor substrate 100 of described grid structure 200 both sides, carry out pre-amorphous injection.
In order to form for ultra-shallow junctions, suppress the diffusion of the foreign ion of light dope source/drain region, improve the activity ratio that ion is injected in light dope source/drain region simultaneously, can before follow-up injection light ion, with described grid structure 200 and patterned photoresist layer (not shown) for mask, in the Semiconductor substrate 100 of described grid structure 200 both sides, carry out pre-amorphous injection, in the Semiconductor substrate 100 of described grid structure both sides, form non-crystallization region 110.
Because the lattice structure in decrystallized Semiconductor substrate is irregular, the P type of follow-up injection or N-type impurity ion not by periodic lattice arrangement void diffusion to the darker degree of depth, inhibit the diffusion of the foreign ion of light dope source/drain region; And described pre-amorphous injection can form vacancy in the lattice structure of Semiconductor substrate, makes the P type of follow-up injection or N-type impurity ion can occupy vacancy more easily, thus improve the activity ratio of light dope source/drain region P type or N-type impurity ion.And in follow-up annealing in process, decrystallized Semiconductor substrate recrystallization, can reduce the impedance of source/drain region, improve the operating current of field-effect transistor.
When field-effect transistor to be formed is PMOS transistor, the ion of described pre-amorphous injection is mixture or the indium ion of titanium ion and indium ion; When field-effect transistor to be formed is nmos pass transistor, the ion of described pre-amorphous injection is mixture or the antimony ion of titanium ion and antimony ion.Because the atomic radius of described titanium ion, indium ion, antimony ion is larger, easily in Semiconductor substrate, form decrystallized region, and after the annealed process of titanium ion forms titanium silicide, the vacancy that titanium silication is formed can eliminate the defect that ion implantation process medium range terminal produces.Improve the yield of product.
The dosage range of the ion of described pre-amorphous injection is 5E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 5KeV ~ 50KeV, and the range of tilt angles of injection is 2 ° ~ 23 °.By the pre-amorphous injection of larger angle, make decrystallized semiconductor substrate region can extend into the below of grid structure, expand decrystallized region, make described non-crystallization region can wrap the light dope source/drain region of follow-up formation.
In embodiments of the present invention, described angle of inclination is the sharp angle between ion implantation direction and Semiconductor substrate plane normal direction.
Please refer to Fig. 4, in the Semiconductor substrate 100 of described grid structure 200 both sides, inject light ion, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds.
Described light ion is specially the combination of Nitrogen ion and carbon ion, the combination of Nitrogen ion and fluorine ion, the combination of carbon ion and fluorine ion, the combination of Nitrogen ion, carbon ion and fluorine ion.The concrete injection technology of described light ion is: with described grid structure 200 and patterned photoresist layer (not shown) for mask, in the Semiconductor substrate 100 of described grid structure 200 both sides, inject light ion, the dosage range that described light ion injects is 5E14atom/cm
2~ 1E15atom/cm
2, the energy range of injection is 4KeV ~ 20KeV, and the range of tilt angles of injection is 0 ° ~ 15 °, and the injection degree of depth of described light ion is greater than the degree of depth of the light dope source/drain region of follow-up formation.Injected by the light ion of larger angle, make light ion injection zone 120 can extend into the below of grid structure, expand the region that light ion injects, make described light ion injection zone 120 can wrap the light dope source/drain region of follow-up formation.In the present embodiment, the degree of depth of the depth ratio non-crystallization region 110 of described light ion injection zone 120 is large, in other embodiments, and the deep equality of the depth ratio non-crystallization region 110 of described light ion injection zone 120.
Be injected into the Nitrogen ion of described Semiconductor substrate, carbon ion, fluorine ion can form particle trap, original position is fixed on the effective ion of particle trap described in making, even if high annealing also not easily spreads, inhibit the enhanced diffustion effect injecting ion, define comparatively precipitous knot, and described Nitrogen ion, fluorine ion can also repair the defect between silica interface.
Inventor finds through research, when described light ion is carbon ion, although the junction depth of source/drain region can be made to reach requirement, but the leakage current of described source/drain region is larger when the implantation dosage of described carbon ion is excessive, therefore, in the dose ratio prior art of carbon ion implatation described in the embodiment of the present invention, the dosage of carbon ion implatation is little, the leakage current of described source/drain region is also smaller, and the degree of depth of described carbon ion implatation and angle are more equal or bigger than non-crystallization region, the injection zone of carbon ion is made to wrap non-crystallization region, the diffusion of inhibition of impurities ion, when described light ion is Nitrogen ion, although light ion can be suppressed as boron ion, the diffusion of phosphonium ion, but heavy ion can be accelerated as indium ion, the diffusion of antimony ion, and have an angle because described light ion is injected into Semiconductor substrate, the N~+ implantation tilted can cause the sidewall of grid structure thickening, make described light ion can not be injected into the channel region of the below of grid structure, can not spread to channel region by the impurity effectively controlled in light dope source/drain region, therefore, the angle of described N~+ implantation is less, and depth ratio carbon ion, the injection degree of depth of fluorine ion is darker, and with non-crystallization region bottom have certain distance, make the longitudinal diffusion of the injection zone energy inhibition of impurities ion of described Nitrogen ion, and the heavy ion injected when can not accelerate pre-amorphous is as indium ion, the diffusion of antimony ion, when described light ion is fluorine ion, fluorine ion better can repair the horizontal proliferation of interface state defects and inhibition of impurities ion, but it is difficult to improve the direct tunneling leakage that device longitudinal electric field causes, test simultaneously finds that it is limited to the diffusion inhibitory action of longitudinal foreign ion, silicon face impurity can be caused to lose in annealing process simultaneously, therefore, the angle of inclination that fluorine ion described in the embodiment of the present invention injects is greater than Nitrogen ion, carbon ion, in the channel region that the injection zone of fluorine ion can be extend into below grid structure, the defect at the silica interface between channel region and gate oxide can be repaired, can also the horizontal proliferation of inhibition of impurities ion.
By optimizing injection technology, by described Nitrogen ion, carbon ion or fluorine ion simultaneously or division step inject, the optimization at respective ion pair impurity and interface can be played, thus can effectively improve device synthesis characteristic further; On the other hand these are injected into the nitrogen of substrate diverse location, carbon and fluorine ion fractal proportional silicide in the middle part of high-temperature annealing process, these silicides can change internal stress distribution, and this is also in order to improve device operation current further and reduce the approach that defect provides optimization.
Please refer to Fig. 5, in another embodiment, described light ion is the combination of Nitrogen ion, carbon ion, fluorine ion three, described Nitrogen ion, carbon ion, fluorine ion are injected in the Semiconductor substrate of described grid structure both sides in different process step, in other embodiments, described Nitrogen ion, carbon ion, fluorine ion can be injected in the Semiconductor substrate of described grid structure both sides simultaneously.Wherein, compared with Nitrogen ion, carbon ion, the angle of inclination that fluorine ion injects is larger, make the injection zone 121 of fluorine ion can extend in the channel region below grid structure 200, the defect at the silica interface between channel region and gate oxide can be repaired, can also the horizontal proliferation of inhibition of impurities ion; The degree of depth of carbon ion implatation and angle are more equal or bigger than non-crystallization region, the injection zone 122 of carbon ion is made to wrap non-crystallization region 110, the diffusion of inhibition of impurities ion, and due to the dosage of carbon ion implatation in the dose ratio prior art of described carbon ion implatation little, the leakage current of described source/drain region is also smaller; The depth ratio carbon ion of described N~+ implantation, the injection degree of depth of fluorine ion are darker, and with non-crystallization region 110 bottom have certain distance, make the longitudinal diffusion of the injection zone 123 energy inhibition of impurities ion of described Nitrogen ion, and the heavy ion injected when can not accelerate pre-amorphous is as the diffusion of indium ion, antimony ion.
In other embodiments, described light ion is the combination of Nitrogen ion and carbon ion, the combination of Nitrogen ion and fluorine ion, the combination of carbon ion and fluorine ion, by regulating angle and the energy of described injection ion, the optimization at same performance ion pair impurity and interface separately, can effectively improve device synthesis performance.
Please refer to Fig. 6, in the Semiconductor substrate 100 of described grid structure 200 both sides, form light dope source/drain region 130, the degree of depth of described light dope source/drain region 130 is less than the degree of depth of described light ion injection zone 120 and is less than the degree of depth of non-crystallization region 110.
When described field-effect transistor is nmos pass transistor, being injected into the impurity that described Semiconductor substrate 100 forms described light dope source/drain region 130 is N-type impurity (phosphorus or arsenic), when described field-effect transistor is PMOS transistor, being injected into the impurity that described Semiconductor substrate 100 forms light dope source/drain region 130 is p type impurity (boron).The formation process of described light dope source/drain region 130 is: with described grid structure 200 and patterned photoresist layer (not shown) for mask, implanting impurity ion in the Semiconductor substrate 100 of described grid structure 200 both sides, the impurity dose scope of described injection is 2E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 0.5KeV ~ 4KeV, and the range of tilt angles of injection is 0 ° ~ 15 °.The degree of depth of described light dope source/drain region 130 is less than the degree of depth of described light ion injection zone 120 and is less than the degree of depth of non-crystallization region 100, and the P type/N-type impurity in described light dope source/drain region 130 is bound in non-crystallization region 100 and light ion injection zone 120.
In other embodiments, pocket (Pocket) district (not shown) is formed near the exterior lateral area of grid structure by the ion implantation tilted in described light dope source/drain region.When the field-effect transistor of described formation is nmos pass transistor, the ion of injection is p type impurity, and the dosage of injection is the 1/10th even less of the dosage of described light dope source/drain region implanted dopant; When the field-effect transistor of described formation is PMOS transistor, the ion of injection is N-type impurity, and the dosage of injection is the 1/10th even less of the dosage of described light dope source/drain region implanted dopant.By forming pocket region in light dope source/drain region near the exterior lateral area of grid structure, because the Doped ions of described pocket region is electrically contrary with the Doped ions adulterated in source/drain region, described light dope source/drain region is narrowed in the depletion region near area of grid, alleviates short-channel effect.
In other embodiments, the technique forming pocket region can be formed before formation light dope source/drain region.
Please refer to Fig. 7, form side wall 230 in described grid structure 200 sidewall surfaces.Described side wall 230 is silicon oxide layer, silicon nitride layer or both laminated construction.In the present embodiment, described side wall 230 is the laminated construction of silicon oxide layer, silicon nitride layer, concrete formation process is: form the first silicon oxide layer (not shown), the first silicon nitride layer (not shown), the second silicon oxide layer (not shown) in described Semiconductor substrate 100 and grid structure 200 surface, then adopts described grid structure 200 sidewall surfaces that is dry-etched in of not mask to form side wall 230.
Please refer to Fig. 8, in the Semiconductor substrate 100 of described side wall 230 both sides, form heavy doping source/drain region 140.
With described side wall 230 and patterned photoresist layer (not shown) for mask, ion implantation is carried out to the Semiconductor substrate 100 of described side wall 230 both sides and forms heavy doping source/drain region.When transistor to be formed is nmos pass transistor, the ion of described injection is N-type impurity; When transistor to be formed is PMOS transistor, the ion of described injection is p type impurity.Described injection ion dose scope is 2E14atom/cm
2~ 2E15atom/cm
2, can disposable injection or inject several times.Because the technique of the formation heavy doping source/drain region of the embodiment of the present invention is prior art, the formation method of heavy doping source/drain region is the known technology of those skilled in the art, does not repeat them here.
Please refer to Fig. 9, annealing in process is carried out to described Semiconductor substrate 100.
Described annealing in process comprises heating furnace annealing, rapid thermal annealing, spike annealing are wherein a kind of.Described annealing in process is carried out after described formation light dope source/drain region, or carries out after described formation heavy doping source/drain region, or carries out respectively after several step wherein.By described annealing in process, Doped ions is activated, and because non-crystallization region makes Doped ions activity ratio wherein improve after the high temperature anneal, thus make the reduction of source/drain region resistance and the increase of operating current, improve the electric property of source/drain region.
The inhibitory action to ion diffuse due to described non-crystallization region and light ion doping, what the N-type of described formation light dope source/drain region and P type ion can not be spread is too far away, form more shallow and more precipitous light dope source/drain region, be not easy to form short-channel effect, and due to less N-type and P type ion diffuse, make light dope source/drain region have higher ion concentration, impedance diminishes, and the saturation current of described field-effect transistor becomes large.
In annealing process, the light ion of described injection can produce a little diffusion, because different light ion diffusion coefficients is different, makes the degree of depth of light ion injection zones different after annealing can change (not shown).In one embodiment, the depth ratio carbon ion in described N~+ implantation region, the degree of depth of fluorine ion injection zone are large, and in another embodiment, the depth ratio carbon ion in described N~+ implantation region, the degree of depth of fluorine ion injection zone are little or equal.
Please refer to Figure 10, is the test result comparison diagram of one embodiment of the invention PMOS transistor formed and the PMOS transistor utilizing prior art to be formed.The described POMS transistor utilizing prior art to be formed is for light dope source/drain region is doped with the PMOS transistor of carbon ion.Ordinate is drain region leakage current, and abscissa is source-drain area saturation current.The PMOS transistor for prior art formation that dotted line represents, the PMOS transistor for embodiment of the present invention formation that solid line represents.Can be found out very intuitively by Figure 10, when drain region leakage current is 1E+04pA/ μm, the source-drain area saturation current large about 7% of the PMOS transistor that the source-drain area saturation current of PMOS transistor that the embodiment of the present invention is formed is formed than prior art, thus improve the electric property of device.
So far, the embodiment of the present invention provides a kind of field-effect transistor, and the cross-sectional view of described field-effect transistor please refer to Fig. 9, specifically comprises: Semiconductor substrate 100; Be positioned at the grid structure 200 on described Semiconductor substrate 100 surface, the sidewall surfaces of described grid structure 200 is formed with side wall 230; Be positioned at the non-crystallization region 110 of the Semiconductor substrate 100 of described grid structure 200 both sides; Be positioned at the light ion injection zone 120 of the Semiconductor substrate 100 of described grid structure 200 both sides, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds; Be positioned at the light dope source/drain region 130 of the Semiconductor substrate 100 of described grid structure 200 both sides, the degree of depth of described light dope source/drain region 130 is less than the degree of depth of described light ion injection zone 120 and is less than the degree of depth of described non-crystallization region 110; Be positioned at the heavy-doped source drain region 140 of the Semiconductor substrate 100 of described side wall 230 both sides.
In the present embodiment, the degree of depth of the depth ratio non-crystallization region 110 of described light ion injection zone 120 is large, in other embodiments, and the deep equality of the depth ratio non-crystallization region 110 of described light ion injection zone 120.
In the present embodiment, described light ion is the mixture of Nitrogen ion, carbon ion, fluorine ion three, the injection zone of described fluorine ion extend in the channel region below grid structure, described fluorine ion can repair the defect at the silica interface between channel region and gate oxide, can also the horizontal proliferation of inhibition of impurities ion; The injection zone of described carbon ion wraps non-crystallization region, the diffusion of inhibition of impurities ion, and due to the dosage of carbon ion implatation in the dose ratio prior art of described carbon ion implatation little, the leakage current of described source/drain region is also smaller; The depth ratio carbon ion in described N~+ implantation region, the degree of depth of fluorine ion injection zone are all large, and with non-crystallization region bottom have certain distance, make the longitudinal diffusion of the injection zone energy inhibition of impurities ion of described Nitrogen ion, and the heavy ion injected when can not accelerate pre-amorphous is as the diffusion of indium ion, antimony ion.
When field-effect transistor to be formed is PMOS transistor, the foreign ion of described non-crystallization region is mixture or the indium ion of titanium ion and indium ion; When field-effect transistor to be formed is nmos pass transistor, the foreign ion of described non-crystallization region is mixture or the antimony ion of titanium ion and antimony ion.
In other embodiments, pocket region (not shown) is formed in described light dope source/drain region near the exterior lateral area of grid structure.The impurity concentration of described pocket region is the 1/10th even less of the impurity concentration of light dope source/drain region, and the Doped ions of the electrical and light dope source/drain region of the Doped ions of described pocket region is electrical contrary, described light dope source/drain region is narrowed in the depletion region near area of grid, alleviates short-channel effect.
The embodiment of the present invention is by carrying out light ion injection to the Semiconductor substrate of source/drain region to be formed, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds, owing to being injected into the Nitrogen ion of described Semiconductor substrate, carbon ion, fluorine ion can serve as particle trap, original position is fixed on the effective ion of particle trap described in making, even if high annealing also not easily spreads, inhibit the N-type of injection or the enhanced diffustion effect of p type impurity ion, define comparatively precipitous and more shallow knot, improve the electric property of field-effect transistor.
Further, the embodiment of the present invention also carries out pre-amorphous injection to the Semiconductor substrate of source/drain region to be formed, the Semiconductor substrate of light dope source/drain region to be formed becomes decrystallized, because the lattice structure in decrystallized Semiconductor substrate is irregular, the P type of follow-up injection or N-type impurity ion not by periodic lattice arrangement void diffusion to the darker degree of depth, inhibit the diffusion of the foreign ion of light dope source/drain region; And described pre-amorphous injection can form vacancy in the lattice structure of Semiconductor substrate, makes the P type of follow-up injection or N-type impurity ion can occupy vacancy more easily, thus improve the activity ratio of light dope source/drain region P type or N-type impurity ion.In follow-up annealing in process, decrystallized Semiconductor substrate recrystallization, can reduce the impedance of source/drain region, improves the operating current of field-effect transistor.Utilize titanium ion as the injection ion of pre-amorphous injection, after titanium ion annealed process formation titanium silicide, the vacancy that titanium silication is formed can eliminate the defect that ion implantation process medium range terminal produces, and improves the yield of product.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (12)
1. a field-effect transistor formation method, is characterized in that, comprising:
Semiconductor substrate is provided;
Grid structure is formed at described semiconductor substrate surface;
Semiconductor substrate region in described grid structure both sides injects light ion, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds, when carbon ion or Nitrogen ion or both mixtures and fluorine ion are together injected into the semiconductor substrate region of described grid structure both sides, described fluorine ion is larger than the angle of inclination of Nitrogen ion, carbon ion implatation, makes the injection zone of fluorine ion can extend into channel region below grid structure; When carbon ion or fluorine ion or both mixtures and Nitrogen ion are together injected into the semiconductor substrate region of described grid structure both sides, the injection depth ratio fluorine ion of described Nitrogen ion, the injection degree of depth of carbon ion are large;
Semiconductor substrate region in described grid structure both sides forms light dope source/drain region, and the degree of depth of described light dope source/drain region is less than the degree of depth of described light ion injection;
Side wall is formed on described gate structure sidewall surface;
Heavy doping source/drain region is formed in the Semiconductor substrate of described side wall both sides;
Annealing in process is carried out to described Semiconductor substrate.
2. field-effect transistor formation method as claimed in claim 1, it is characterized in that, the technological parameter of described injection light ion is: the dosage range of injection is 5E14atom/cm
2~ 1E15atom/cm
2, the energy range of injection is 4KeV ~ 20KeV, and the range of tilt angles of injection is 0 ° ~ 15 °.
3. field-effect transistor formation method as claimed in claim 1, is characterized in that, different light ions adopts same technique to inject simultaneously or adopts different process step separately to inject.
4. field-effect transistor formation method as claimed in claim 1, it is characterized in that, also comprise, before described injection light ion, carry out pre-amorphous injection in the semiconductor substrate region of described grid structure both sides, the degree of depth of described pre-amorphous injection is greater than the degree of depth of described light dope source/drain region.
5. field-effect transistor formation method as claimed in claim 4, is characterized in that, when field-effect transistor to be formed is PMOS transistor, the ion of described pre-amorphous injection is titanium ion, the mixture of indium ion or indium ion; When field-effect transistor to be formed is nmos pass transistor, the ion of described pre-amorphous injection is titanium ion, the mixture of antimony ion or antimony ion.
6. field-effect transistor formation method as claimed in claim 4, it is characterized in that, the technological parameter of described pre-amorphous injection is: the dosage range of injection is 5E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 5KeV ~ 50KeV, and the range of tilt angles of injection is 2 ° ~ 23 °.
7. field-effect transistor formation method as claimed in claim 1, it is characterized in that, the concrete technology of described formation light dope source/drain region is: in the semiconductor substrate region of described grid structure both sides, inject N-type impurity ion or p type impurity ion, and the dosage range of injection is 2E14atom/cm
2~ 2E15atom/cm
2, the energy range of injection is 0.5KeV ~ 4KeV, and the range of tilt angles of injection is 0 ° ~ 15 °.
8. field-effect transistor formation method as claimed in claim 1, it is characterized in that, described annealing in process is carried out after described formation light dope source/drain region, or carries out after described formation heavy doping source/drain region, or carries out respectively after above-mentioned two steps.
9. field-effect transistor formation method as claimed in claim 8, is characterized in that, described annealing in process comprises heating furnace annealing, rapid thermal annealing, spike annealing are wherein a kind of.
10. a field-effect transistor, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the grid structure of described semiconductor substrate surface, the sidewall surfaces of described grid structure is formed with side wall;
Be positioned at the light ion injection zone of the Semiconductor substrate of described grid structure both sides, described light ion comprises Nitrogen ion, carbon ion, fluorine ion wherein at least two kinds, when described light ion at least comprises fluorine ion, the injection zone of described fluorine ion extend into the channel region below grid structure than Nitrogen ion, carbon ion; When described light ion at least comprises Nitrogen ion, the injection depth ratio fluorine ion of described Nitrogen ion, the injection degree of depth of carbon ion are large;
Be positioned at the light dope source/drain region of the Semiconductor substrate of described grid structure both sides, the degree of depth of described light doping section is less than the degree of depth of described light ion injection zone;
Be positioned at the heavy-doped source drain region of the Semiconductor substrate of described side wall both sides.
11. field-effect transistors as claimed in claim 10, is characterized in that, also comprise, be positioned at the non-crystallization region of the Semiconductor substrate of described grid structure both sides, the degree of depth of described non-crystallization region is greater than the degree of depth of described light dope source/drain region.
12. field-effect transistors as claimed in claim 11, is characterized in that, when field-effect transistor to be formed is PMOS transistor, the foreign ion of described non-crystallization region is mixture or the indium ion of titanium ion and indium ion; When field-effect transistor to be formed is nmos pass transistor, the foreign ion of described non-crystallization region is mixture or the antimony ion of titanium ion and antimony ion.
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| CN109309004A (en) * | 2017-07-26 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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