CN101930923B

CN101930923B - Fabrication method of MOS (Metal Oxide Semiconductor) transistor

Info

Publication number: CN101930923B
Application number: CN 200910054099
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2009-06-26
Filing date: 2009-06-26
Publication date: 2012-12-05
Anticipated expiration: 2029-06-26
Also published as: CN101930923A

Abstract

The invention relates to a fabrication method of an MOS (Metal Oxide Semiconductor) transistor, comprising the steps of: providing a semiconductor substrate, wherein a gate dielectric layer and a polysilicon layer are formed on the semiconductor substrate; etching the gate dielectric layer and the polysilicon layer; oxidizing the etched polysilicon layer; and annealing after oxidizing the etched polysilicon layer. In the invention, after oxidizing the etched polysilicon layer, a step of annealing is added before carrying out LDD injection and Halo injection, thus, most defects formed in the semiconductor substrate can be eliminated, more defects caused by interaction between doped ions from the LDD injection and the Halo injection and defects formed in the polysilicon oxidation process can be prevented, an oxidation enhanced diffusion effect can be inhibited during annealing after carrying out the LDD injection, and the influenced of short channel effect on the device is prevented. Meanwhile, by adopting the annealing after oxidizing the etched polysilicon layer, the invention can achieve the effect of repairing polysilicon gate oxide defects, thereby enhancing the reliability of the device.

Description

The manufacture method of MOS transistor

Technical field

The present invention relates to technical field of semiconductors, particularly the manufacture method of MOS transistor.

Background technology

Along with transistor gate length continue dwindle; Oxidation-enhanced diffusion (Oxidation-EnhancedDiffusion; OED) become the key factor that influences boron ion and phosphonium ion diffusion, because the OED effect has caused transient enhanced diffusion effect (TED); And the transient enhanced diffusion effect not only causes transistorized short-channel effect, and influences transistor channel mobility, junction capacitance and junction leakage.

Prior art discloses a kind of transient enhanced diffusion effect (TED) of utilizing and in crystalline substrates, has obtained the method that predetermined diffusion of impurities distributes; Introduce at least two kinds of dopant ions and a kind of non-foreign ion through same zone in substrate; Influence the diffusion of foreign ion through non-foreign ion; Said non-foreign ion is such as being argon, neon, germanium etc., then 700 to 950 degrees centigrade of annealing down.

, the patent No. can also find more information relevant in being the United States Patent (USP) of US6136673 with technique scheme.

But; In technique scheme, make dopant ion form certain diffusion profile through injecting dopant ion and non-dopant ion at the same time, the non-dopant ion of introducing in this technical scheme is bigger; When injecting, can in substrate, further introduce defective; And this defective can influence the distribution of the foreign ion of injection, and possibly form new enhancing diffuse source, is unfavorable for dwindling and the making of ultra shallow junction of small size device like this; And injection can cause the device Impurity Distribution too complicated plurality of impurities the time, is unfavorable for the control that technology and device property are stable.

Prior art also discloses a kind of method that forms MOS transistor; Concrete technology please refer to Fig. 1, comprises step S101, and Semiconductor substrate is provided; In Semiconductor substrate, form isolation structure; Said isolation structure is divided into different active areas with Semiconductor substrate, in said active area, forms dopant well, in dopant well, adjusts threshold voltage and injects; Step S103 forms gate dielectric layer and polysilicon layer on Semiconductor substrate; Step S105, etching gate dielectric layer and polysilicon form grid structure; Step S107 carries out oxidation to the polysilicon that forms grid structure, forms first oxide layer; Step S109 carries out low-doped drain (LDD) and injects, and carries out halo (Halo) and injects; Step S111 carries out first annealing; Step S113 forms side wall; Step S115 carries out source/drain electrode heavy doping and injects (S/D); Step S119 carries out second annealing.

In fact the above-mentioned processing step that only provides the making MOS transistor relevant with the application, possibly also comprise other steps, such as dopant well is annealed, to the polysilicon step of mixing or the like, enumerate no longer one by one at this.

In the method for above-mentioned formation MOS transistor; Before carrying out low-doped drain (LDD) injection, perhaps carrying out to carry out oxidation to the polysilicon layer of grid structure usually before halo (Halo) injection, polysilicon layer is being protected to form first silicon oxide layer in the polysilicon layer periphery.

Summary of the invention

The problem that the present invention solves provides a kind of MOS transistor and preparation method thereof, because oxidation produces defective in Semiconductor substrate inside, causes short channel or anti-short-channel effect to suppress.

For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprising: Semiconductor substrate is provided, is formed with gate dielectric layer and polysilicon layer on the said Semiconductor substrate; Gate dielectric layer and polysilicon layer are carried out etching; Polysilicon layer after the etching is carried out oxidation, in peripheral first oxide layer that forms of polysilicon layer; Also comprise: carry out post-oxidation anneal.

Said post-oxidation anneal is a rapid thermal annealing.

The temperature range of said annealing is 950 to 1050 degrees centigrade, and annealing time is 30 seconds to 10 minutes.

The temperature range of said annealing is 1000 to 1050 degrees centigrade, and the time is 30 seconds to 1 minute.

Said post-oxidation anneal is for to carry out in tube furnace.

The temperature range of said annealing is 800 to 900 degrees centigrade, and annealing time is 10 to 45 minutes.

The temperature range of said annealing is 800 to 850 degrees centigrade, and annealing time is 20 to 30 minutes.

The gas that feeds during said annealing is inert gas or nitrogen.

Said gas is inert gas, and feeding said inert gas flow is 0.3 to 9 Liter Per Minute.

Said gas is nitrogen, and the range of flow that feeds said nitrogen is 0.3 to 9 Liter Per Minute.

Said gas is nitrogen, and the range of flow that feeds said nitrogen is 0.3 to 5 Liter Per Minute.

Compared with prior art; The present technique scheme has the following advantages: after to the polysilicon layer oxidation after the etching, carry out that LDD injects and Halo adds post-oxidation anneal before injecting; Can most ofly eliminate the defective group and reduction interstitial atom supersaturation concentration that in forming the first oxide layer process, in Semiconductor substrate, form; Like this, can prevent to cause more defects, therefore in follow-up LDD injects and Halo injects dopant ion and the interaction of these defectives; Annealing after follow-up LDD injects can suppress the oxidation-enhanced diffusion effect, prevents that device from receiving the influence of short-channel effect.

Description of drawings

Fig. 1 is the schematic flow sheet of the formation cmos device of prior art;

Fig. 2 is the schematic flow sheet of the formation cmos device of one embodiment of the present of invention;

Fig. 3 to Fig. 7 is the transistorized cross-sectional view of formation nMOS of one embodiment of the present of invention.

Embodiment

As previously mentioned; Inventor of the present invention finds; In oxidizing process, at the intersection of Semiconductor substrate and gate dielectric layer, the defective (comprising group (cluster) and interstitial atom (interstitial)) that can cause semiconductor substrate surface is to the inner extension of Semiconductor substrate.Because (Oxidation-Enhanced Diffusion, OED) effect when auxiliary impurity inwardly spreads, also quicken to the Semiconductor substrate diffusion inside defective to oxidation-enhanced diffusion; And, can not repair these defectives because the oxidization time of oxidizing process is short, these defectives can move in Semiconductor substrate at random everywhere; In addition, after oxidizing process, carry out low-doped drain (LDD) injection, Halo injection and annealing usually, but should anneal present spike (spike) annealing of adopting usually, the time is also very short, also is not sufficient to repair-deficiency; Further again; The dopant ion that follow-up LDD injects and Halo injects also can interact with these defectives and cause more defects; Through above-mentioned effect, causing through the inner defect density ratio of the later half conductive substrate of peroxidating significantly increases originally, causes transient enhanced diffusion effect (TED); Further cause short channel or anti-short-channel effect, influence the performance of device.

Based on above-mentioned experimental study and theoretical derivation, inventor of the present invention provides a kind of manufacture method of new MOS transistor, so that solve the problems of the technologies described above.

Below through describing specific embodiment in detail according to accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:

The present invention at first provides a kind of manufacture method of MOS transistor, specifically please with reference to Fig. 2, comprising: execution in step S11, Semiconductor substrate is provided, and be formed with gate dielectric layer and polysilicon layer on the said Semiconductor substrate; Execution in step S13 carries out etching to gate dielectric layer and polysilicon layer; Execution in step S15 carries out oxidation to the polysilicon layer after the etching, in peripheral first oxide layer that forms of polysilicon layer; Execution in step S17 carries out post-oxidation anneal.

Describing formation MOS transistor technology of the present invention in detail below in conjunction with Fig. 3 to Fig. 7, in the present embodiment, is that example is explained with the transistorized formation technology of nMOS.

At first with reference to Fig. 3, Semiconductor substrate 100 is provided, is formed with isolation structure 101 in the said Semiconductor substrate 100, said isolation structure 101 is divided into Semiconductor substrate 100 the different active areas (unmarked) of MOS transistor to be formed.The conduction type of said Semiconductor substrate 100 can adopt the p type usually for n type or p type.

Also be formed with pad oxide 103 on the said Semiconductor substrate 100, be used for the follow-up ion that injects in the protection of injection ion formation dopant well technology, prevent to inject ion and overflow.

In the active area of Semiconductor substrate 100, introduce first ion, form dopant well 102.The kind of the MOS transistor that said first ion and this active area are to be formed is relevant, if the channel type of MOS transistor to be formed is the n type, then first ion is the p type, such as being generally the boron ion; If the channel type of MOS transistor to be formed is the p type, then first ion is the n type, such as being generally phosphonium ion.MOS transistor in the present embodiment is the n type, so the conduction type of dopant well should be the p type.

Simultaneously, the structure of dopant well 102 can also comprise multiple, is not limited to single dopant well 102 structures of diagram in the present embodiment; Can be the triple-well structure, such as: if Semiconductor substrate is the p type, then can injects n type ion and form first dopant well; Can form p type MOS transistor in this first dopant well; NMOS transistor area in first dopant well is injected p type ion then, forms second dopant well, in this second dopant well, forms n type MOS transistor then.

Then, with reference to Fig. 4, in the dopant well 102 of Semiconductor substrate 100, introduce second ion, to adjust the threshold voltage of MOS transistor to be formed.Usually, introducing second ion at active area forms through injecting.

Inject after second ion, form the second ion district 104 in the channel region of the MOS transistor in isolation well 102.Simultaneously, this second ion district 104 also extends in the source/drain extension region of raceway groove both sides.

Equally in this step; In fact can directly adopt the mask plate that forms isolation well; Second ion that promptly plays the injection of adjustment threshold voltage effect can be not limited to only be infused in the channel region of MOS transistor to be formed, can not bring ill effect equally even be injected into the source/drain extension region of raceway groove both sides.

Said second ion is different and different according to MOS transistor kind to be formed, if the channel type of MOS transistor to be formed is the n type, then second ion is the p type, such as being boron ion or indium ion; If the channel type of MOS transistor to be formed is the p type, then second ion is the n type, such as being phosphonium ion or arsenic ion.

Usually after the formation dopant well and the second ion district, need anneal to the ion that injects, so that its even diffused.This technology is a techniques well known, is not described in detail in this.

With reference to Fig. 5, remove pad oxide 103; On Semiconductor substrate 100, form gate dielectric layer 106 and polysilicon layer 107.

With reference to Fig. 6, etching gate dielectric layer 106 and polysilicon layer 107 form grid structure.

With reference to Fig. 7, the polysilicon layer after the etching 107 is carried out oxidation, form first oxide layer 108.

The purpose that forms first oxide layer 108 is for to protect polysilicon layer.

When but oxidation can bring the advantage of protection polysilicon layer, also brought negative effect.As previously mentioned, although oxidation also is the process of a high-temperature process, in this high-temperature process, can repair the defective in the Semiconductor substrate 100; But because the oxidation-enhanced diffusion effect, in repair-deficiency, can cause in the Semiconductor substrate 100 especially with the defective on the surface (being source to be formed/drain extension region position) of the Semiconductor substrate 100 of gate dielectric layer 106 intersections and quicken to Semiconductor substrate 100 in, to spread; And should diffusion can cause new defective, simultaneously, because follow-up needs carry out LDD and inject; Can cause more defects like this; Therefore, the final number of defects that in Semiconductor substrate 100, forms is greater than number of defects in the original Semiconductor substrate 100, and the increase of defects count; Can bring a series of negative effect, such as short channel or anti-channeling effect etc.

In order to address this problem, the present inventor proposes after etching gate dielectric layer 106 and polysilicon layer 107, to carry out the post-oxidation anneal step.

Said post-oxidation anneal can be divided into two kinds of methods, and a kind of is higher temperature, short period annealing, can be rapid thermal annealing, adopts quick anneal oven to carry out, and is 950 to 1050 degrees centigrade such as the temperature range of annealing, and annealing time is 30 seconds to 10 minutes.

But the inventor finds; Annealing temperature is high more, annealing time is more little; So just can avoid the thermal diffusion of impurity intrinsic to cause long channel device characteristic that excessive variation takes place more; So the combination of annealing temperature of the present invention and annealing time is as the criterion with the variation of unlikely long ditch device (like channel length 10 μ m) threshold voltage 10%; And with unlikely cause in the polygate electrodes to mix be penetrated into channel region and be as the criterion, the doping in the said polygate electrodes be penetrated into channel region with the doping (impurity) of channel region for being no more than 1E15cm ^-3Be as the criterion.Therefore to these MOS devices, annealing temperature can be chosen higher, and annealing time can be shorter, about the further optimization of annealing temperature and time can be with reference to the data of back literary composition.

But the inventor finds; Adopt long period annealing that the threshold voltage of long channel device is descended; Change its device performance, but, can compensate the threshold voltage that descends through other modes so if adopt long period annealing can bring other benefits; Such as realizing, anneal and continue the employing long period through change injection condition to channel region.

And for some other device, such as the NROM device, it can consider that to short-channel effect perhaps short-channel effect also can adopt long period annealing under the little situation of its performance impact.

The method of another kind of annealing is lower temperature, long period annealing, can in tube furnace, anneal, and be 800 to 900 degrees centigrade such as the temperature range of annealing, annealing time is 10 to 45 minutes.Equally, the combination of said annealing temperature and annealing time causes that with unlikely the polysilicon gate variation that is penetrated into raceway groove or long ditch device (like channel length 10 μ m) threshold voltage 10% of mixing in advance is as the criterion.

The annealing of above-mentioned two kinds of schemes, its atmosphere is inert gas or nitrogen, and said inert gas is such as being argon gas, helium, neon etc.Feeding said inert gas flow weight range is 0.3 to 9 Liter Per Minute, if nitrogen, the flow that feeds nitrogen is 0.3 to 9 Liter Per Minute.

But because nitrogen feeds too much, possibly introduce the nitrogen ion at device inside, and the existence of nitrogen ion possibly influence device performance, therefore further optimize, the flow of the nitrogen of feeding is 0.3 to 5 Liter Per Minute.

As an embodiment, if the length of polysilicon layer (being that grid are long) is 55nm, the gas of feeding is argon gas, and flow is 5 Liter Per Minutes, and annealing temperature is 980 degrees centigrade, and annealing time is 50s.

As another embodiment, if the length of polysilicon layer (being that grid are long) is 55nm, the gas of feeding is nitrogen, and flow is 2 Liter Per Minutes, and annealing temperature is 1030 degrees centigrade, and annealing time is 30s.

As another embodiment, if the length of polysilicon layer (being that grid are long) is 55nm, the gas of feeding is argon gas, and flow is 5 Liter Per Minutes, and annealing temperature is 830 degrees centigrade, and annealing time is 20min.

As another embodiment, if the length of polysilicon layer (being that grid are long) is 55nm, the gas of feeding is nitrogen, and flow is 2 Liter Per Minutes, and annealing temperature is 880 degrees centigrade, and annealing time is 10min.

Through after the above-mentioned post-oxidation anneal; Can before carrying out the LDD injection, most of the elimination form defective group (cluster) and the reduction interstitial atom supersaturation concentration that the first oxide layer process forms in Semiconductor substrate; Like this; Can prevent that injecting the dopant ion that injects with Halo at follow-up LDD causes more defects with these owing to defective interaction that oxidation polysilicon process forms; Therefore accordingly, the annealing after LDD injects can suppress the oxidation-enhanced diffusion effect, prevents that device from receiving the influence of short-channel effect.

In actual process; Also need mix to reduce the resistivity of polysilicon layer, especially for nmos pass transistor, although be not described in detail here to the polysilicon layer in the grid structure; Those skilled in the art know, and should too not limit protection scope of the present invention at this.

After post-oxidation anneal, also need carry out LDD and inject injection with Halo, and follow-up formation side wall, formation source/steps such as drain electrode, no longer be described in detail at this.

Respectively semiconductor device of the present invention is simulated under TSUPREM4 in the TCAD simulation softward of employing U.S. Si Nuofeisi (Synopsys) company and the MEDICI environment.The process conditions of simulation are 65nm, and Semiconductor substrate is a silicon.

Table 1 provides the data of not carrying out the post-oxidation anneal and the difference Δ Vt2 of the difference Δ Vt1 that utilizes in the swing curve (rolloff) of the resulting threshold voltage of annealing conditions under the different condition of the present invention high threshold voltage value and minimum threshold voltage value and nominal device and minimum level device (subnominal device) threshold voltage value; NA representes not add the post-oxidation anneal step in the table 1 is the data of the device that forms of prior art; All the other are adding post-oxidation anneal step of the present invention; Annealing temperature is respectively under 800 to 900 degrees centigrade and is annealed into low temperature, long term annealing, and annealing time was respectively 10,20,30 minutes; Be annealed into high temperature, short time annealing under 1000 and 1050 degrees centigrade, annealing time was respectively 10,1,0.5 minutes.

Table 1

Temperature (℃)	Time (minute)	ΔVt1	ΔVt2
				NA	NA	21	20
800	10	21	18
				800	20	20	16
800	30	16	15
				900	10	15	13
900	20	13	12
				900	30	12	9
1000	10	9	14

Can find out from table 1; With do not carry out comparing of post-oxidation anneal, the difference Δ Vt2 of the difference Δ Vt1 of threshold voltage and threshold voltage value all reduces, and the high words of the difference of threshold voltage say that the threshold voltage of bright this device is unstable; Device performance is unstable; Therefore add the stability that post-oxidation anneal helps improving device, can explain that thus annotating the adding post-oxidation anneal can effectively suppress short-channel effect and anti-short-channel effect (RSCE), so the performance of MOS transistor is much relatively stable.

Through discovering that the annealing conditions of further optimizing is that temperature range is 1000 to 1050 degrees centigrade for higher temperature, short time annealing (promptly in quick anneal oven), the time is 30 seconds to 1 minute.Although in table 1; In higher temperature, the short time annealing data, the threshold voltage difference of short period (such as 0.5 minute) is compared bigger with the threshold voltage difference of long period (such as 10 minutes), but finds through research its swing curve (roll-off) (not shown); Adopt the whole decline of threshold voltage of long period annealing excessive; Compensate even can inject ion, but the ion that needs to inject too much still is unfavorable for the stable of device performance, the performance of therefore comprehensive its swing curve at channel region; Further optimizing annealing conditions is that temperature range is 1000 to 1050 degrees centigrade, and the time is 30 seconds to 1 minute.

From table 1, for lower temperature, long term annealing (promptly in tube furnace), the annealing conditions of further optimizing is 800 to 850 degrees centigrade, and the time is 20 to 30 minutes, and this optimal conditions also is to combine the threshold voltage difference of swing curve table 1 to confirm.

And compare with higher temperature, short time annealing (promptly in quick anneal oven); The condition of the post-oxidation anneal of further optimizing again is that annealing temperature is 800 to 850 degrees centigrade; Time is 20 to 30 minutes, and promptly tube annealing is compared with short annealing, has more superiority.This mainly is because the reparation that lower temperature is annealed, long term annealing more helps defective in the Semiconductor substrate; And because this fashion is not carried out low doping source/drain electrode injection or halo injects; The caused transient enhanced diffusion effect of long term annealing is also not obvious; Therefore optimized annealing conditions of the present invention is that annealing temperature is 800 to 850 degrees centigrade, and the time is 20 to 30 minutes.

Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

1000	1	14	15
				1000	0.5	15	7
1050	10	7	12
				1050	0.5	12	10
1050	1	10	9

Claims

1. the manufacture method of a MOS transistor is characterized in that, comprising:

Semiconductor substrate is provided, is formed with gate dielectric layer and polysilicon layer on the said Semiconductor substrate;

Gate dielectric layer and polysilicon layer are carried out etching;

Polysilicon layer after the etching is carried out oxidation, in peripheral first oxide layer that forms of polysilicon layer;

Carry out post-oxidation anneal, to eliminate the defective of Semiconductor substrate and the generation of gate dielectric layer intersection in forming the first oxide layer process;

Carrying out LDD injects;

Carry out LDD and inject after annealing.

2. the manufacture method of MOS transistor according to claim 1 is characterized in that, said post-oxidation anneal is a rapid thermal annealing.

3. the manufacture method of MOS transistor according to claim 2 is characterized in that, the temperature range of said annealing is 950 to 1050 degrees centigrade, and annealing time is 30 seconds to 10 minutes.

4. the manufacture method of MOS transistor according to claim 3 is characterized in that, the temperature range of said annealing is 1000 to 1050 degrees centigrade, and the time is 30 seconds to 1 minute.

5. the manufacture method of MOS transistor according to claim 1 is characterized in that, said post-oxidation anneal is for to carry out in tube furnace.

6. the manufacture method of MOS transistor according to claim 5 is characterized in that, the temperature range of said annealing is 800 to 900 degrees centigrade, and annealing time is 10 to 45 minutes.

7. the manufacture method of MOS transistor according to claim 6 is characterized in that, the temperature range of said annealing is 800 to 850 degrees centigrade, and annealing time is 20 to 30 minutes.

8. according to the manufacture method of each described MOS transistor in the claim 3 to 7, it is characterized in that the gas that feeds during said annealing is inert gas or nitrogen.

9. the manufacture method of MOS transistor according to claim 8 is characterized in that, said gas is inert gas, and feeding said inert gas flow is 0.3 to 9 Liter Per Minute.

10. the manufacture method of MOS transistor according to claim 8 is characterized in that, said gas is nitrogen, and the range of flow that feeds said nitrogen is 0.3 to 9 Liter Per Minute.

11. the manufacture method of MOS transistor according to claim 10 is characterized in that, said gas is nitrogen, and the range of flow that feeds said nitrogen is 0.3 to 5 Liter Per Minute.