200807514 九、發明說明： 本申請案要求優先權保護，其根據在2006年5月1 1 曰及2007年3月5日申請之韓國專利申請案第 1 0-2006-0042509 號及第 1 0-2007-002 1 346 號，其所有內容 皆包含於其中以供參照。 【發明所屬之技術領域】 本發明係關於一種製造半導體裝置的方法，特別是一 種在基板或者薄層上執行的電漿（Plasma)摻雜方法。 【先前技術】 通常，在製造半導體裝置期間，執行摻雜來獲得所需 之基板或薄層（例如複晶矽）的電氣特性。主要使用一種光 束線離子佈植方法來作爲一種摻雜方法。該光束線離子佈 植方法係使用電場來加速欲佈植的離子（亦即，具備高的動 能）。該被加速之離子碰撞固態材料的表面。因此，該離子 可被佈植入該基板內。 近來，已使用一種電漿摻雜方法。在該電漿摻雜方法 中，該欲佈植之離子的來源材料係處於氣體狀態。形成電 漿，然後施加一個高的偏壓至欲摻雜的樣品。因此，該電 漿之正離子加速至該樣品的表面且被佈植於其中。所以， 該電漿摻雜方法可執行均勻的摻雜，並且改進摻雜率。而 且，相較於該光束離子佈植方法，因爲該電漿摻雜方法不 需要使用單獨的離子產生源（即，離子束）及加速設備，所 以可降低設備製造成本。 第1A至1C圖係說明一種用以製造半導體裝置的典型 200807514 方法。如第1 A圖所示，複數裝置隔離層1 2形成在基板1 1 的區段內。在該基板1 1上形成閘極絕緣層1 3，且在該閘極 絕緣層1 3上形成閘極複晶矽層1 4。執行電漿摻雜方法以利 用P型雜質來摻雜該閘極複晶矽層14。 如第1 B圖所示，執行退火處理來活化摻雜於該閘極複 晶矽層14內的該P型雜質。 如第1 C圖所示，在該閘極複晶矽層1 4上形成金屬矽 化物層（metal silicide layer)，例如閘極砂化鎢層（gate tungsten silicide layer)15，然後執行鬧極圖案化製程來作 爲後續處理。如果執行上述的電漿摻雜方法，在薄層的上 表面上方可會能存在著過高的雜質濃度。 第2圖係說明透過光束線離子佈植方法及電漿摻雜方 法，摻雜在形成有閘極複晶矽層之樣品上的雜質之典型線 型的曲線圖。水平軸代表該樣品之深度，而垂直軸代表用 作爲P型雜質的硼濃度。約800A的深度則指出了在該閘極 氧化層之上表面和閘極複晶矽層之間的界面之深度。更詳 細而言，該閘極複晶矽層的深度是約800A。參照第2圖， 比較透過該電漿摻雜方法而獲得之雜質線型與透過該離子 佈植方法而獲得之雜質線型。相較於該光束線離子佈植， 當執行電漿摻雜方法時，在該閘極複晶矽層之上表面（例 如，在對應約0A之深度的閘極複晶矽層部分）的雜質濃度 係相對較大。特別是雖然在該光束線離子佈植方法中’該 雜質濃度在約200A處呈現出高斯分佈，但在該電漿摻雜方 法中，該雜質濃度於該閘極複晶矽層之上表面爲最大。 200807514 第3圖係說明在執行退火處理之後，透過光束線離子 佈植方法及電漿摻雜方法而摻雜的雜質之典型線型的曲線 圖。參考標記及_代表在該電漿摻雜方法中使用的不同 類型之雜質。透過該退火處理，該雜質被活化下降至閘極 複晶矽層的下表面（例如，在閘極氧化層的上表面周遭）。 在執行該電漿摻雜方法的情況下，在該閘極複晶矽層之上 表面，亦即在該閘極複晶矽層之深度約爲0 A處量測到最大 的雜質濃度。 如第2和3圖所示，如果執行該電漿摻雜方法，雖然 執行該退火處理，但大量雜質可能存在於該閘極複晶矽層 之上表面上方。在隨後的退火的處理期間，存在於該閘極 複晶矽層之上表面上方的雜質係朝向該閘極複晶矽層（例 如，金屬矽化物層）之上層進行擴散。因此，在該閘極複晶 矽層之表面周遭的摻雜效應突然降低。亦即，在該閘極複 晶矽層之表面會產生相關的雜質空乏效應（impurity depletion effect)。該摻雜效應的減少造成了該閘極複晶矽 層之阻抗的增加。此外，具有由以P +型雜質摻雜的複晶矽 所形成之閘極的P型金屬氧化半導體（PM0S)電晶體之飽和 電流特性可能會劣化。 【發明內容】 本發明之實施例係關於一種電漿摻雜方法，用以降低 在該上層之表面周遭的濃度尖峰。 本發明之實施例致力於提供一種製造半導體裝置的方 法，其中該方法能防止在閘極複晶矽層內之雜質的外擴 200807514 散，因此降低閘極複晶矽層的雜質空乏效應。 在一實施例中，電漿摻雜方法包括在基板上方提供摻 雜源，其中該摻雜源具有欲注入至該基板的摻雜物。施加 至少兩種不同的偏壓，將來自該摻雜源的摻雜物注入至該 基板。 在另一實施例中，製造半導體裝置的方法包括在基板 上方形成複晶矽層。使用電漿摻雜方法並以雜質來摻雜該 複晶矽，其中使用至少兩種不同的偏壓來執行該電漿摻雜 方法。 【實施方式】 根據本發明之實施例，電漿摻雜方法可施加於半導體 裝置製造處理的各種步驟。例如，可施加該電漿摻雜方法， 以摻雜由半導體材料（例如，矽）所形成之主體基板。該半 導體材料是磊晶層。此外，可施加該電漿摻雜方法，以摻 雜在基板之上部上方形成的薄層。特別是，本發明之實施 例的該電漿摻雜方法在摻雜閘極複晶矽層方面很有用。 第4A至4D圖係說明一種根據本發明之實施例的製造 半導體裝置的典型方法。如第4A圖所示，多數裝置隔離層 42形成在基板41 (例如，矽基板）內。透過淺溝槽隔離（STI) 方法來形成該裝置隔離層42。 在該基板4 1上方形成閘極絕緣層4 3。該閘極絕緣層 43可以是透過熱氧化法、乾式氧化法或濕式氧化法所形成 的氧化層。 在該閘極絕緣層43上方形成作爲閘極電極的閘極複 200807514 晶矽層44。在高度整合之記憶體裝置中，該閘極複晶矽層 44之深度在從約400A到約1，200A的範圍中。然而，該閘 極複晶矽層44之深度可根據裝置類型而改變。 如第4B圖所示，當變化偏壓量以摻雜該閘極複晶矽層 44時，執行電漿摻雜方法。更詳細而言，摻雜的來源氣體 被加到該閘極複晶矽層44的上部。然後，該來源氣體被轉 換成電漿離子，且藉由對該基板41加上偏壓，該電漿離子 加速進入該閘極複晶矽層44。根據本發明之實施例，該偏 壓量並非固定，而是連續地變化。在摻雜P型雜質之硼（B) 的情況下，使用三氟化硼（BF3)或硼乙烷（B2H6)來作爲該來 源氣體。 在該電漿摻雜方法期間，該偏壓量從低電壓位準變成 局電壓位準，或者從尚電壓位準變成低電壓位準。特別是， 如果參考偏壓（Vref)被定在約8kV，該偏壓量能在約 8kV±2kV的範圍內改變。例如，如果使用約8kV的該參考 偏壓（Vref)，藉由施加從約6kV上升到約10kV或從約10kV 下降至約6kV的偏壓來進行該摻雜。因此，在改變該偏壓 量時，如果執行該電漿摻雜方法，會得到類似光束線離子 佈植方法所獲得之雜質線型。特別是，該雜質線型會呈現 以比該閘極複晶矽層44之上表面還要低之部分爲基礎的 高斯分佈。 在該電漿摻雜方法期間，對於每個偏壓量，摻雜的劑 量可被均一地保持著。更詳細而言，在約10kV、約9kV、 約8kV、約7kV及約6kV的偏壓量，使用約lxi〇16atoms/cm2 200807514 的劑量來執行該電漿摻雜方法。 此外，在該電漿摻雜方法期間，當該偏壓 該摻雜劑量可改變。當加上該參考偏壓時，使 量。因此，該雜質線型呈現出高斯分佈。例如 約5xl016atoms/cm2的劑量及加上從約10kV改i 的偏壓量來以三個步驟執行該電漿摻雜方法， 的偏壓量時，使用約lxl010atoms/cm2的劑量； 偏壓量時，使用約3 X 1 016 a t 〇 m s / c m2的劑量·，以 的偏壓量時，使用約lxl016atoms/cm2的劑量。 如第4C圖所示，執行退火處理來活化摻雜 晶矽層44內之雜質。由於該退火處理，該雜質 該閘極絕緣層43。該退火處理包括使用快速熱 並且在溫度範圍從約850°C到約1，100°C中執行 1秒到約60秒。 如上所述，如果在該偏壓量改變時執行該 法，該雜質線型能在該閘極複晶矽層44之上表 出高斯分佈，類似於透過該光束線離子佈植方 雜質線型。 如第4D圖所示，在該閘極複晶矽層44上 鎢層45。若非使用該矽化鎢層45，則可使用其 物層或矽化物層以外的金屬層。 在該矽化鎢層45形成之後，採用熱處理來 處理。然而，因爲在該閘極複晶矽層44內的雜 在該閘極複晶矽層44的中心部分，雖然執行該 量變化時， 用最高的劑 ，若要使用 I到約6kV 則在約10kV 在約8kV的 及在約6kV 在該閘極複 被活化朝向 處理（RTP)， 該RTP達約 電漿摻雜方 面附近呈現 法所獲得之 方形成矽化 他金屬矽化 作爲隨後的 質主要分布 熱處理，但 -10- 200807514 朝向矽化鎢層45的外擴散（out-diffusion)可受到控制。因 此，可防止該閘極複晶矽層44之阻抗的增加，且P型金屬 氧化半導體（PM0S)電晶體之飽和電流特性不會劣化。 第5圖係各種類型之摻雜方法的反轉電容量（inversi〇n capacitance)的說明圖。參考字母A代表典型地透過佈植硼 而執行的方法。參考字母B代表不改變偏壓量而典型地執 行的電漿摻雜方法。參考字母C代表根據本發明之實施例 而改變偏壓量時所執行的電漿摻雜方法。參照第5圖，比 較被標示爲A、B及C之摻雜方法的各種類型之反轉電容 量。 當採用方法C時，反轉電容量之位準最大。當反轉電 容量之位準較小時，裝置的啓始電壓（threshold voltage)增 加，因此該裝置的操作特性劣化。因此，因爲採用本發明 之實施例的該電漿摻雜方法，該反轉電容量之位準增加， 所以該裝置特性獲得改善。 根據本發明之實施例，在該偏壓量改變時，執行該電 漿摻雜方法。由於該電漿摻雜方法，該雜質線型能在該薄 層之上表面附近呈現出高斯分佈，類似於藉由該典型光束 線離子佈植方法所獲得之雜質線型。因此，可降低該雜質 的外擴散，且因此可減少該裝置之電氣特性的劣化。 當根據該具體實施例來描述本發明時，只要不違背下 述申請專利範圍中所定義之精神及範圍，熟習該項技藝者 就可進行各種變化和修改。 【圖式簡單說明】 -11- 200807514 第1A至1C圖係說明一種用以製造半導體裝置的典型 方法。 第2圖係說明分別透過光束線離子佈植方法及電漿摻 雜方法而摻雜的雜質之典型線型的曲線圖。 第3圖係說明在執行退火處理之後，分別透過光束線 離子佈植方法及電漿摻雜方法而摻雜的雜質之典型線型的 曲線圖。 第4Α至4D圖係說明一種根據本發明之實施例的製造 半導體裝置的方法。 第5圖係各種類型之摻雜方法所獲得之反轉電容量的 說明圖。 【主要元件符號說明】 11 基 板 12 裝 置 隔 離 層 13 閘 極 絕 緣 層 14 閘 極 複 晶 矽 層 15 閘 極 矽 化 鎢 層 4 1 基 板 42 裝 置 隔 離 層 43 閘 極 絕 緣 層 44 閘 極 複 晶 矽 層 45 矽 化 鶴 層 -12-200807514 IX. INSTRUCTIONS: This application claims priority protection according to Korean Patent Application No. 1 0-2006-0042509 and No. 1 0-Applications filed on May 1, 2006 and March 5, 2007. 2007-002 1 346, all of which is incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a plasma doping method performed on a substrate or a thin layer. [Prior Art] Generally, during the fabrication of a semiconductor device, doping is performed to obtain electrical characteristics of a desired substrate or thin layer (e.g., a germanium). A beamline ion implantation method is mainly used as a doping method. The beamline ion implantation method uses an electric field to accelerate ions to be implanted (i.e., has high kinetic energy). The accelerated ions collide with the surface of the solid material. Therefore, the ions can be implanted into the substrate. Recently, a plasma doping method has been used. In the plasma doping method, the source material of the ions to be implanted is in a gaseous state. A plasma is formed and then a high bias is applied to the sample to be doped. Therefore, the positive ions of the plasma are accelerated to the surface of the sample and are implanted therein. Therefore, the plasma doping method can perform uniform doping and improve the doping ratio. Moreover, compared to the beam ion implantation method, since the plasma doping method does not require the use of a separate ion generating source (i.e., ion beam) and an acceleration device, the manufacturing cost of the device can be reduced. 1A to 1C illustrate a typical 200807514 method for fabricating a semiconductor device. As shown in FIG. 1A, a plurality of device isolation layers 12 are formed in the sections of the substrate 11. A gate insulating layer 13 is formed on the substrate 11 and a gate polysilicon layer 14 is formed on the gate insulating layer 13. A plasma doping method is performed to dope the gate polysilicon layer 14 with a P-type impurity. As shown in Fig. 1B, an annealing treatment is performed to activate the P-type impurity doped in the gate polysilicon layer 14. As shown in FIG. 1C, a metal silicide layer, such as a gate tungsten silicide layer 15, is formed on the gate polysilicon layer 14, and then the pattern is executed. The process is used as a follow-up process. If the plasma doping method described above is carried out, an excessively high impurity concentration may exist above the upper surface of the thin layer. Fig. 2 is a graph showing a typical line pattern of impurities doped on a sample formed with a gate polysilicon layer by a beam line ion implantation method and a plasma doping method. The horizontal axis represents the depth of the sample, and the vertical axis represents the boron concentration used as the P-type impurity. A depth of about 800 A indicates the depth of the interface between the upper surface of the gate oxide layer and the gate polysilicon layer. In more detail, the gate polysilicon layer has a depth of about 800 Å. Referring to Fig. 2, the impurity line type obtained by the plasma doping method and the impurity line type obtained by the ion implantation method are compared. Compared to the beam line ion implantation, when performing the plasma doping method, impurities on the surface of the gate polysilicon layer (for example, at the portion of the gate polysilicon layer corresponding to a depth of about 0 A) The concentration system is relatively large. In particular, although the impurity concentration exhibits a Gaussian distribution at about 200 A in the beamline ion implantation method, in the plasma doping method, the impurity concentration is on the upper surface of the gate polysilicon layer. maximum. 200807514 Fig. 3 is a graph showing a typical line pattern of impurities doped by a beam line ion implantation method and a plasma doping method after performing an annealing treatment. The reference marks and _ represent the different types of impurities used in the plasma doping method. Through the annealing treatment, the impurities are activated to fall to the lower surface of the gate polysilicon layer (e.g., around the upper surface of the gate oxide layer). In the case of performing the plasma doping method, the maximum impurity concentration is measured on the surface above the gate polysilicon layer, i.e., at a depth of about 0 A at the gate polysilicon layer. As shown in Figs. 2 and 3, if the plasma doping method is performed, although the annealing treatment is performed, a large amount of impurities may exist above the upper surface of the gate polysilicon layer. During the subsequent annealing process, impurities present above the upper surface of the gated germanium layer are diffused toward the upper layer of the gate polysilicon layer (e.g., metal germanide layer). Therefore, the doping effect around the surface of the gate polysilicon layer suddenly decreases. That is, an associated impurity depletion effect is generated on the surface of the gate polysilicon layer. This reduction in doping effect causes an increase in the impedance of the gate polysilicon layer. Further, the saturation current characteristics of a P-type metal oxide semiconductor (PMOS) transistor having a gate formed of a polysilicon doped with a P + -type impurity may be deteriorated. SUMMARY OF THE INVENTION Embodiments of the present invention are directed to a plasma doping method for reducing concentration spikes around a surface of the upper layer. Embodiments of the present invention are directed to a method of fabricating a semiconductor device in which the external expansion of impurities in the gate polysilicon layer is prevented, thereby reducing the impurity depletion effect of the gate polysilicon layer. In one embodiment, a plasma doping method includes providing a dopant source over a substrate, wherein the dopant source has a dopant to be implanted into the substrate. A dopant from the dopant source is implanted into the substrate by applying at least two different bias voltages. In another embodiment, a method of fabricating a semiconductor device includes forming a polysilicon layer over a substrate. The plasma doping method is doped using a plasma doping method, and the plasma doping method is performed using at least two different bias voltages. [Embodiment] According to an embodiment of the present invention, a plasma doping method can be applied to various steps of a semiconductor device manufacturing process. For example, the plasma doping method can be applied to dope a body substrate formed of a semiconductor material (eg, germanium). The semiconductor material is an epitaxial layer. Additionally, the plasma doping method can be applied to dope a thin layer formed over the upper portion of the substrate. In particular, the plasma doping method of an embodiment of the present invention is useful in doping a gated polysilicon layer. 4A through 4D illustrate an exemplary method of fabricating a semiconductor device in accordance with an embodiment of the present invention. As shown in Fig. 4A, a plurality of device isolation layers 42 are formed in a substrate 41 (e.g., a germanium substrate). The device isolation layer 42 is formed by a shallow trench isolation (STI) method. A gate insulating layer 43 is formed over the substrate 41. The gate insulating layer 43 may be an oxide layer formed by a thermal oxidation method, a dry oxidation method or a wet oxidation method. A gate resolving layer 200807514 is formed over the gate insulating layer 43 as a gate electrode. In a highly integrated memory device, the gate polysilicon layer 44 has a depth in the range of from about 400A to about 1,200A. However, the depth of the gate polysilicon layer 44 can vary depending on the type of device. As shown in Fig. 4B, when the bias amount is varied to dope the gate polysilicon layer 44, a plasma doping method is performed. In more detail, the doped source gas is added to the upper portion of the gate polysilicon layer 44. The source gas is then converted to plasma ions and the plasma ions are accelerated into the gate polysilicon layer 44 by biasing the substrate 41. According to an embodiment of the invention, the amount of bias is not fixed but varies continuously. In the case of boron (B) doped with a P-type impurity, boron trifluoride (BF3) or boron hydride (B2H6) is used as the source gas. During the plasma doping method, the bias amount changes from a low voltage level to a local voltage level, or from a still voltage level to a low voltage level. In particular, if the reference bias voltage (Vref) is set at about 8 kV, the bias amount can be varied within a range of about 8 kV ± 2 kV. For example, if a reference bias voltage (Vref) of about 8 kV is used, the doping is performed by applying a bias voltage that rises from about 6 kV to about 10 kV or from about 10 kV to about 6 kV. Therefore, when the bias amount is changed, if the plasma doping method is performed, an impurity line type similar to that obtained by the beam line ion implantation method is obtained. In particular, the impurity line type exhibits a Gaussian distribution based on a portion lower than the upper surface of the gate polysilicon layer 44. During the plasma doping method, the doping amount can be uniformly maintained for each bias amount. In more detail, the plasma doping method is performed using a dose of about 1 xi 〇 16 atoms/cm 2 200807514 at a bias amount of about 10 kV, about 9 kV, about 8 kV, about 7 kV, and about 6 kV. Moreover, during the plasma doping method, the doping amount can be varied when the bias is applied. When the reference bias is applied, the amount is used. Therefore, the impurity line type exhibits a Gaussian distribution. For example, a dose of about 5xl016 atoms/cm2 and a bias amount of about 10 kV to be used to perform the plasma doping method in three steps, a dose of about lxl010 atoms/cm2 is used; A dose of about 3 x 1 016 at 〇ms / c m2 is used, and a dose of about lxl016 atoms/cm2 is used. As shown in Fig. 4C, an annealing treatment is performed to activate the impurities in the doped germanium layer 44. Due to the annealing treatment, the impurity is the gate insulating layer 43. The annealing treatment involves the use of rapid heat and is carried out for 1 second to about 60 seconds at a temperature ranging from about 850 ° C to about 1,100 ° C. As described above, if the method is performed while the bias amount is changed, the impurity line type can exhibit a Gaussian distribution over the gate polysilicon layer 44, similar to the ion line pattern of the ion implantation through the beam line. As shown in Fig. 4D, a tungsten layer 45 is formed on the gate polysilicon layer 44. If the tungsten-deposited tungsten layer 45 is not used, a metal layer other than the material layer or the vaporized layer can be used. After the formation of the tungsten-deposited tungsten layer 45, it is treated by heat treatment. However, since the impurity in the gate polysilicon layer 44 is in the central portion of the gate polysilicon layer 44, although the amount of change is performed, the highest dose is used, and if I is to use about 6 kV, 10kV at about 8kV and at about 6kV in the gate is activated by the orientation-oriented treatment (RTP), the RTP reaches about the plasma doping side, and the method obtained by the nearby method forms a deuterated metal deuteration as a subsequent mass distribution heat treatment. , but --10-200807514 The out-diffusion towards the tungsten-deposited tungsten layer 45 can be controlled. Therefore, the increase in the impedance of the gate polysilicon layer 44 can be prevented, and the saturation current characteristics of the P-type metal oxide semiconductor (PMOS) transistor are not deteriorated. Fig. 5 is an explanatory diagram of inversitivity of various types of doping methods. Reference letter A represents a method that is typically performed by implanting boron. The reference letter B represents a plasma doping method which is typically performed without changing the amount of bias. The reference letter C represents a plasma doping method performed when the bias amount is changed according to an embodiment of the present invention. Referring to Figure 5, the various types of inversion capacitances of the doping methods labeled A, B, and C are compared. When Method C is used, the level of the reversed capacitance is the largest. When the level of the reversed capacitance is small, the threshold voltage of the device increases, and thus the operational characteristics of the device deteriorate. Therefore, since the level of the inversion capacitance is increased by the plasma doping method of the embodiment of the present invention, the characteristics of the device are improved. According to an embodiment of the invention, the plasma doping method is performed when the bias amount is changed. Due to the plasma doping method, the impurity line type exhibits a Gaussian distribution near the upper surface of the thin layer, similar to the impurity line type obtained by the typical beam line ion implantation method. Therefore, the out-diffusion of the impurities can be reduced, and thus the deterioration of the electrical characteristics of the device can be reduced. When the present invention is described in terms of the specific embodiments, various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS -11- 200807514 Figures 1A to 1C illustrate a typical method for fabricating a semiconductor device. Fig. 2 is a graph showing a typical line type of impurities doped by a beam line ion implantation method and a plasma doping method, respectively. Fig. 3 is a graph showing a typical line type of impurities doped by a beam line ion implantation method and a plasma doping method, respectively, after performing an annealing treatment. Figures 4 to 4D illustrate a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. Fig. 5 is an explanatory diagram of the inversion capacitance obtained by various types of doping methods. [Main component symbol description] 11 Substrate 12 Device isolation layer 13 Gate insulation layer 14 Gate polysilicon layer 15 Gate tungsten germanium layer 4 1 Substrate 42 Device isolation layer 43 Gate insulation layer 44 Gate polysilicon layer 45矽化鹤层-12-