CN102983104A - Manufacturing method of complementary metal oxide semiconductor (CMOS) transistors - Google Patents
Manufacturing method of complementary metal oxide semiconductor (CMOS) transistors Download PDFInfo
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- CN102983104A CN102983104A CN2011102643666A CN201110264366A CN102983104A CN 102983104 A CN102983104 A CN 102983104A CN 2011102643666 A CN2011102643666 A CN 2011102643666A CN 201110264366 A CN201110264366 A CN 201110264366A CN 102983104 A CN102983104 A CN 102983104A
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Abstract
The invention discloses a manufacturing method of complementary metal oxide semiconductor (CMOS) transistors. Pre-non-crystallizing injection for a polycrystalline silicon layer of an N-channel metal oxide semiconductor (NMOS) area is achieved, ions injected in a pre-non-crystallizing mode enables polycrystalline silicon of the polycrystalline silicon layer to be converted into noncrystalline silicon in a following high-temperature annealing process, stress is also produced in the conversion process, the stress is exerted on a semiconductor substrate of the NMOS area, and therefore stress memorizing effects of NMOS transistors are improved, electronic mobility and drive currents of the NMOS transistors are further improved, and the purpose that integral performance of the CMOS transistors is improved is achieved.
Description
Technical field
The present invention relates to integrated circuit and make the field, relate in particular to the transistorized manufacture method of a kind of CMOS.
Background technology
Along with transistorized size in the semiconductor technology production process is constantly dwindled, the voltage and current of transistor unit need of work constantly reduces, and the speed of transistor switch is also accelerated thereupon, the semiconductor technology each side is required significantly to improve thereupon.For improving the performance of semiconductor device, industry has proposed kinds of processes and method, comprising gate last process and stress memory technique.
Along with transistorized part has been accomplished the thickness of several molecules and atom to form the limit that semi-conductive material has reached the physical electrical characteristic.Existing technique adopts silicon dioxide (SiO usually
2) as the material of gate dielectric layer, the silicon dioxide layer in the transistor has narrowed down to and only had at first 1/10th so far, even reaches the thickness that 5 oxygen atoms are only arranged.Gate dielectric layer is as the insulating barrier between spacer gates conductive layer and its lower floor (for example Semiconductor substrate), can not dwindle again, otherwise the leakage current that produces can allow transistor work, if improve the effectively voltage and current of work, more can make chip power-consumption increase to surprising stage.Therefore, industry has found the material-high dielectric constant material (High-K Material) that has higher dielectric constant and better field effect characteristic than silicon dioxide, in order to better separation grid and other parts of transistor, significantly reduces electrical leakage quantity.Simultaneously, for compatible with high dielectric constant material, adopt metal material to replace original polysilicon as the grid conductive layer material, thereby formed new grid structure.The grid structure of metal material is in the high-temperature annealing process process, and the problems affect performance of semiconductor device such as gate depletion and RC delay can occur significantly to change, cause its work function (Work Function).
Problem for the grid structure that solves above-mentioned metal material, formed gate last process (Gate-Last Process), namely form first the illusory gate stack with polysilicon layer, after carrying out source leakage injection and high-temperature annealing process, remove again the polysilicon layer in the illusory gate stack, and deposit metallic material, finally form metal gates.
Simultaneously, for improving the transistorized device performance of CMOS, industry is introduced stress memory technique, namely by introduce stress in the raceway groove of Semiconductor substrate, so that performance of devices improves, the technique of improving device performance by stress has become the common technological means of semiconductor applications.Stress memory technique is included in CMOS transistor top deposition stressor layers (such as nitration case etc.) in the prior art, carry out high-temperature annealing process so that stress is remembered on semiconductor device, stress is remembered behind the active area of grid polycrystalline silicon or diffusion region or Semiconductor substrate removes stressor layers.Thereby use stress to be improved the mobility in electronics or hole, improved the performance of device integral body.Especially the nmos pass transistor in the CMOS transistor, stress memory technique is stress application (when being compression) in a longitudinal direction, can improve the electron mobility of nmos pass transistor, improve nmos pass transistor drive current (Idrive), and then improve the performance of nmos pass transistor.
Except above-mentioned stress memory method, how to realize in gate last process better that better stress memory effect also becomes the industry problem demanding prompt solution.
Summary of the invention
The purpose of this invention is to provide the transistorized manufacture method of a kind of CMOS, to improve the stress memory effect of nmos pass transistor.
For addressing the above problem, the transistorized manufacture method of a kind of CMOS of the present invention comprises:
Semi-conductive substrate is provided, and described Semiconductor substrate comprises nmos area territory and PMOS zone;
On described Semiconductor substrate, form successively dielectric layer and polysilicon layer;
Polysilicon layer on described nmos area territory carries out pre-amorphous injection;
Form silicon nitride layer at described polysilicon layer;
The described silicon nitride layer of etched portions, polysilicon layer and dielectric layer to form the NMOS gate stack in described nmos area territory, form the PMOS gate stack in described PMOS zone;
Form the NMOS grid curb wall at described NMOS gate stack sidewall, form the PMOS grid curb wall at described PMOS gate stack sidewall;
Carry out high-temperature annealing process.
Further, the step that the polysilicon layer on described nmos area territory carries out pre-amorphous injection comprises: at described polysilicon layer surface-coated photoresist layer; The described photoresist layer of patterning is positioned at photoresist layer on the described nmos area territory with removal, exposes the polysilicon layer in described nmos area territory; Carry out pre-amorphous injection to described Semiconductor substrate; Remove remaining photoresist layer.
Further, the ion of described pre-amorphous injection comprises a kind of or its combination of boron, phosphorus, germanium, arsenic.
Further, the Implantation Energy of described pre-amorphous injection is 5KeV～25KeV.
Further, in the step that forms described NMOS grid curb wall and PMOS grid curb wall and carry out between the step of high-temperature annealing process, also comprise, in the Semiconductor substrate of described NMOS gate stack both sides, form the NMOS source-drain area and be positioned at NMOS metal silicide region above the described NMOS source-drain area; And in the Semiconductor substrate of described PMOS gate stack both sides, form the PMOS source-drain area and be positioned at PMOS metal silicide region above the described PMOS source-drain area.
Further, the material of NMOS metal silicide region and PMOS metal silicide region is a kind of or its combination in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and the tantalum silicide.
Further, the step that forms described NMOS grid curb wall and PMOS grid curb wall with carry out between the step of high-temperature annealing process, also be included in described nmos area field surface covering stressor layers.
Further, the material of described stressor layers is silicon nitride, and thickness is 200 dusts～600 dusts.
Further, the stress of described stressor layers generation is-500MPa～1600MPa.
Further, the annealing temperature of described high-temperature annealing process is 900 ℃～1300 ℃.
Further, the thickness of described polysilicon layer is 500 dusts～700 dusts.
Further, the thickness of described silicon nitride layer is 300 dusts～500 dusts.
Than prior art, the present invention carries out pre-amorphous injection by the polysilicon layer to the nmos area territory, the ion of pre-amorphous injection makes polysilicon layer be converted into amorphous silicon by polysilicon at follow-up high-temperature annealing process, and in conversion process, produce stress, this effect of stress is in the Semiconductor substrate in described nmos area territory, improved the stress memory effect of nmos pass transistor, further improve electron mobility and the drive current of nmos pass transistor, thereby reach the purpose that improves the transistorized overall performance of cmos device.
Description of drawings
Fig. 1 is the schematic flow sheet of the transistorized manufacture method of CMOS in the embodiment of the invention one.
Fig. 2～Fig. 8 is the structural representation in the transistorized manufacturing process of CMOS in the embodiment of the invention one.
Fig. 9 is the structural representation in the transistorized manufacturing process of CMOS in the embodiment of the invention two.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
The transistorized manufacture method of CMOS of the present invention mainly for improving the transistorized performance of CMOS that adopts gate last process (Gate-Last Process), improves the performance of nmos pass transistor by adopting new stress memory method.Certainly, the method for the invention can be applied to equally adopt and form first in the transistorized manufacture craft of CMOS of grid technology (Gate-First Process).
Embodiment one
Fig. 1 is the schematic flow sheet of the transistorized manufacture method of CMOS in the embodiment of the invention one.Fig. 2～Fig. 8 is the structural representation in the transistorized manufacturing process of CMOS in the embodiment of the invention one.
In conjunction with Fig. 1～shown in Figure 8, the transistorized manufacture method of the CMOS of present embodiment may further comprise the steps:
Step S01: as shown in Figure 2, provide semi-conductive substrate 100, described Semiconductor substrate 100 comprises nmos area territory 10 and PMOS zone 20;
Wherein, described Semiconductor substrate 100 can be monocrystalline silicon, the semi-conducting materials such as polysilicon or germanium silicon compound, also be formed with various isolated components and various doped regions etc. in order to form the necessary structure of semiconductor device in the described Semiconductor substrate 100, described isolated component for example is fleet plough groove isolation structure (STI) 102, described doped region (not indicating among the figure) for example is the N trap, P trap and lightly-doped source drain region (LDD), said structure is determined according to actual semiconductor device manufacture craft process, be well known to those skilled in the art technology contents, do not repeat them here.
Step S02: as shown in Figure 2, on described Semiconductor substrate 100, form successively dielectric layer 101 and polysilicon layer 103;
Described dielectric layer 101 can be adopted as common dielectric material, for example a kind of or its combination in oxide, nitride, the nitrogen oxide, and described dielectric layer 101 can adopt thermal oxidation method or chemical vapour deposition technique (CVD) to form.Described polysilicon layer 103 comprises the polysilicon layer 103a that is formed on the nmos area territory 10 and is formed at polysilicon layer 103b on the PMOS zone 20, described polysilicon layer 103 can adopt chemical vapour deposition technique to form, and the thickness of described polysilicon layer 103 is 500 dusts～700 dusts.
Step S03: such as Fig. 3～shown in Figure 5, carry out pre-amorphous injection to the polysilicon layer 103a in described nmos area territory 10;
The process of carrying out described pre-amorphous injection specifically may further comprise the steps: at first, at described polysilicon layer 103a, 103b surface-coated photoresist layer; Then, the described photoresist layer of patterning keeps the photoresist layer 300 that is positioned on the described PMOS zone 20, exposes the polysilicon layer 103a in described nmos area territory 10, forms as shown in Figure 3 structure; As shown in Figure 4, then, carry out pre-amorphous injection (Pre Amorphization Implant to described Semiconductor substrate 100, PAI) 200, through after the described pre-amorphous injection 200, polysilicon layer 103a in described nmos area territory 10 has pre-amorphous ion, and the polysilicon layer 103b in PMOS zone 20 blocks the lower ion that does not inject described pre-amorphous injection 200 at photoresist layer 300.Wherein better, the ion of described pre-amorphous injection 200 can be a kind of or its combination of boron, phosphorus, germanium, arsenic, and the Implantation Energy of described pre-amorphous injection 200 is 5KeV～25KeV; At last, remove remaining photoresist layer 300 on the described PMOS zone 20, form as shown in Figure 5 structure.
After carrying out pre-amorphous injection 200 to the polysilicon layer 103a in described nmos area territory 10, in the polysilicon layer 103a in described nmos area territory 10, form pre-amorphous ion, described pre-amorphous ion is in follow-up high-temperature annealing process, make the polysilicon of the polysilicon layer 103a in nmos area territory 10 be converted into amorphous silicon, in conversion process, produce stress, this effect of stress is in the Semiconductor substrate 100 in nmos area territory 10, thereby reach the electron mobility that improves nmos pass transistor, improve the nmos pass transistor drive current, and then improve the effect of the performance of nmos pass transistor.
Step S04: as shown in Figure 6, form silicon nitride layer 105 at described polysilicon layer 103;
Described silicon nitride layer 105 can adopt chemical vapour deposition technique to form, and the thickness of described silicon nitride layer 105 is 300 dusts～500 dusts.Described silicon nitride layer 105 is covered on described polysilicon layer 103a, the 103b; for the protection of polysilicon layer 103a, 103b; prevent from forming simultaneously metal silicide on polysilicon layer 103a, the 103b, avoid when follow-up removal polysilicon layer 103a, 103b, being difficult to remove because the metal silicide on it stops.
Step S05: as shown in Figure 7, the described silicon nitride layer 105 of etched portions, polysilicon layer 103a, 103b and dielectric layer 101, with the 10 formation NMOS gate stack 106a in described nmos area territory, 10 form PMOS gate stack 106b in described PMOS zone;
Detailed process is as follows: spin coating photoresist film on described nitration case 105 (not indicating among the figure), photoresist film is exposed and develops, graphical photoresist film, remove the described silicon nitride layer 105 of part, polysilicon layer 103a, 103b and dielectric layer 101 take described graphical photoresist film as mask successively etching, 10 form NMOS gate stack 106a in described nmos area territory, 10 form PMOS gate stack 106b in described PMOS zone, the final structure that forms as shown in Figure 7.
Step S06: as shown in Figure 8, form NMOS grid curb wall 107a at described NMOS gate stack 106a sidewall, form PMOS grid curb wall 107b at described PMOS gate stack 106b sidewall;
Better, the material of described NMOS grid curb wall 107a and described PMOS grid curb wall 107b is oxide layer or nitration case, also can be ONO (oxide layer-nitride layer-oxide layer) structure or ON (oxide layer-nitration case) structure, described NMOS grid curb wall 107a and described PMOS grid curb wall 107b can adopt the method for chemical vapour deposition (CVD) and etching to form, be the common technique means that those skilled in the art were familiar with, do not give unnecessary details so do not do at this.
After forming described NMOS grid curb wall 106a and PMOS grid curb wall 107a, form NMOS source-drain area 108a and the NMOS metal silicide region 109a that is positioned at described NMOS source-drain area 108a top, and PMOS source-drain area 108b and the PMOS metal silicide region 109b that is positioned at described PMOS source-drain area 108b top.Particularly, at first, injection is leaked in the source of carrying out N-type doping ion in the Semiconductor substrate 100 of described NMOS gate stack 106a both sides, form NMOS source-drain area 108a, injection is leaked in the source of carrying out P type doping ion in the Semiconductor substrate 100 of described PMOS gate stack 106b both sides, forms PMOS source-drain area 108b; Then, above described NMOS source-drain area 108a, form NMOS metal silicide region 109a, above described PMOS source-drain area 108b, form PMOS metal silicide region 109b.
Wherein, in Semiconductor substrate 100 surfaces, metal forms metal silicide with pasc reaction to the mode that described NMOS metal silicide region 109a and PMOS metal silicide region 109b preferably utilize chemical vapour deposition (CVD) (CVD) or physical vapour deposition (PVD) (PVD) in high-temperature annealing process with metal deposition.The material of described NMOS metal silicide region 109a and PMOS metal silicide region 109b is a kind of or its combination in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and the tantalum silicide.In the present embodiment, the material of described NMOS metal silicide region 109a and PMOS metal silicide region 109b is nickel-silicon compound, utilize the nickel beam-plasma to be sputtered onto in the described Semiconductor substrate 100, in follow-up high-temperature annealing process with described Semiconductor substrate 100 in silicon generation chemical reaction, thereby form nickel-silicon compound.Described NMOS metal silicide region 109a and PMOS metal silicide region 109b help electrically drawing of source-drain area for the resistance characteristic at interface between the metal interconnecting wires that improves Semiconductor substrate 100 source-drain areas and follow-up formation.
In the process of NMOS metal silicide region 109a and PMOS metal silicide region 109b, described silicon nitride layer 105 blocks described polysilicon layer 103a, 103b, prevent from forming simultaneously metal silicide on polysilicon layer 103a, the 103b, avoid when follow-up removal polysilicon layer 103a, 103b, stopping the problem that is difficult to remove because of the metal silicide on it.
Step S07: carry out high-temperature annealing process.
The annealing temperature of described high-temperature annealing process is 900 ℃～1300 ℃.In the high-temperature annealing process process, the polysilicon layer of described NMOS gate stack 106 is formed with pre-amorphous ion, pre-amorphous ion makes the polysilicon layer of described NMOS gate stack 106 be converted into amorphous silicon by polysilicon in high-temperature technology, produce stress in the conversion process, this effect of stress is in the Semiconductor substrate 100 in nmos area territory 10, thereby reach the electron mobility that improves nmos pass transistor, improve nmos pass transistor drive current (Idrive), and then improve the effect of the performance of nmos pass transistor.
Further, finish high-temperature annealing process after, the CMOS transistor fabrication that present embodiment provides can also may further comprise the steps:
At first, on described Semiconductor substrate, the both sides of described NMOS gate stack and PMOS gate stack form the first medium layer; Then, remove nitration case and polysilicon layer in the NMOS gate stack, remove nitration case and polysilicon layer in the PMOS gate stack; Then, the described NMOS gate stack of depositing metal layers and PMOS gate stack, thus form metal gates.Polysilicon layer in the described NMOS gate stack finally is removed, thus carry out pre-amorphous injection pair nmos transistor produce stress after pair nmos transistor without other influences.In addition, described CMOS transistor fabrication also comprises other processing steps, and processing steps such as contact hole, metal lead wire etc. are those skilled in the art's common technique means, do not do at this and give unnecessary details.
Embodiment two:
Fig. 9 is the structural representation in the transistorized manufacturing process of the embodiment of the invention two CMOS, as shown in Figure 9, on the process base of the CMOS of embodiment one preparation method of transistor, between step S06 and step S07, be increased in the step of described nmos area territory 10 surface coverage stressor layers 110.
Preferably, the material of described stressor layers 110 is silicon nitride, and its thickness range is 200 dusts～600 dusts.The stress that described stressor layers produces is-500MPa～1600MPa, wherein-500MPa～0MPa is compression, 0MPa～1600MPa is tension stress.Stressor layers 110 stress memories that described silicon nitride forms are good, and silicon nitride is common material in the semiconductor technology, and manufacturing cost is relatively low.Stressor layers 110 can using plasma chemical vapour deposition (CVD) (PECVD), low-pressure chemical vapor deposition (LPCVD), the method such as thermalization chemical vapour deposition (CVD) (RTCVD) or high density plasma deposition (HDP) forms fast, the reacting gas of employing can comprise SiH
4, SiH
2Cl
2, SiH
2F
2And NH
3Described stressor layers 110 better thickness are 200 dusts～600 dusts, after forming stressor layers 110, stress is remembered on the Semiconductor substrate 100 in nmos area territory 10, thereby use stress to be able in a longitudinal direction stress application (when being compression), can improve the electron mobility of nmos pass transistor, and then improve the nmos pass transistor drive current, further improve the stress memory effect.
To sum up, than prior art, the present invention carries out pre-amorphous injection by the polysilicon layer to described nmos area territory, the ion of pre-amorphous injection makes polysilicon layer be converted into amorphous silicon by polysilicon at follow-up high-temperature annealing process, and in conversion process, produce stress, this effect of stress is in the Semiconductor substrate in described nmos area territory, improved the stress memory effect of nmos pass transistor, further improve electron mobility and the drive current of nmos pass transistor, thereby reach the purpose that improves the transistorized overall performance of cmos device.
Although the present invention discloses as above with preferred embodiment; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (12)
1. transistorized manufacture method of CMOS comprises:
Semi-conductive substrate is provided, and described Semiconductor substrate comprises nmos area territory and PMOS zone;
On described Semiconductor substrate, form successively dielectric layer and polysilicon layer;
Polysilicon layer on described nmos area territory carries out pre-amorphous injection;
Form silicon nitride layer at described polysilicon layer;
The described silicon nitride layer of etched portions, polysilicon layer and dielectric layer to form the NMOS gate stack in described nmos area territory, form the PMOS gate stack in described PMOS zone;
Form the NMOS grid curb wall at described NMOS gate stack sidewall, form the PMOS grid curb wall at described PMOS gate stack sidewall;
Carry out high-temperature annealing process.
2. the transistorized manufacture method of CMOS as claimed in claim 1 is characterized in that the step that the polysilicon layer on described nmos area territory carries out pre-amorphous injection comprises:
At described polysilicon layer surface-coated photoresist layer;
The described photoresist layer of patterning is positioned at photoresist layer on the described nmos area territory with removal, exposes the polysilicon layer in described nmos area territory;
Carry out pre-amorphous injection to described Semiconductor substrate;
Remove remaining photoresist layer.
3. the transistorized manufacture method of CMOS as claimed in claim 1 is characterized in that the ion of described pre-amorphous injection comprises a kind of or its combination of boron, phosphorus, germanium, arsenic.
4. the transistorized manufacture method of CMOS as claimed in claim 1 is characterized in that the Implantation Energy of described pre-amorphous injection is 5KeV～25KeV.
5. the transistorized manufacture method of CMOS as claimed in claim 1 is characterized in that, in the step that forms NMOS grid curb wall and PMOS grid curb wall and carry out also comprising between the step of high-temperature annealing process:
In the Semiconductor substrate of described NMOS gate stack both sides, form the NMOS source-drain area and be positioned at NMOS metal silicide region above the described NMOS source-drain area; And
In the Semiconductor substrate of described PMOS gate stack both sides, form the PMOS source-drain area and be positioned at PMOS metal silicide region above the described PMOS source-drain area.
6. the transistorized manufacture method of CMOS as claimed in claim 5, it is characterized in that the material of described NMOS metal silicide region and PMOS metal silicide region is a kind of or its combination in nickel silicide, cobalt silicide, tungsten silicide, Titanium silicide and the tantalum silicide.
7. the transistorized manufacture method of CMOS as claimed in claim 1 is characterized in that, the step that forms described NMOS grid curb wall and PMOS grid curb wall with carry out between the step of high-temperature annealing process, also be included in described nmos area field surface covering stressor layers.
8. the transistorized manufacture method of CMOS as claimed in claim 7 is characterized in that the material of described stressor layers is silicon nitride, and thickness is 200 dusts～600 dusts.
9. the transistorized manufacture method of CMOS as claimed in claim 7 is characterized in that, the stress that described stressor layers produces is-500MPa～1600MPa.
10. such as the transistorized manufacture method of CMOS as described in any one in the claim 1 to 9, it is characterized in that the annealing temperature of described high-temperature annealing process is 900 ℃～1300 ℃.
11. such as the transistorized manufacture method of CMOS as described in any one in the claim 1 to 9, it is characterized in that the thickness of described polysilicon layer is 500 dusts～700 dusts.
12. such as the transistorized manufacture method of CMOS as described in any one in the claim 1 to 9, it is characterized in that the thickness of described silicon nitride layer is 300 dusts～500 dusts.
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