CN106783557B - The preparation method of multiple graphical exposure mask - Google Patents
The preparation method of multiple graphical exposure mask Download PDFInfo
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- CN106783557B CN106783557B CN201611086146.8A CN201611086146A CN106783557B CN 106783557 B CN106783557 B CN 106783557B CN 201611086146 A CN201611086146 A CN 201611086146A CN 106783557 B CN106783557 B CN 106783557B
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- layer
- polysilicon layer
- amorphous silicon
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- exposure mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention relates to a kind of preparation methods of multiple graphical exposure mask, comprising: provides semiconductor substrate, forms hard mask layer on the semiconductor substrate；The amorphous silicon layer stacked gradually and the first polysilicon layer are formed on the hard mask layer of part；It is formed and is rolled around the amorphous silicon layer and first polysilicon layer；Stressor layers are formed on the hard mask layer, the side wall and the amorphous silicon layer；Thermal anneal process is carried out to the semiconductor substrate, the amorphous silicon layer is changed into the second polysilicon layer, and the width of second polysilicon layer is greater than the width of first polysilicon layer；Remove second polysilicon layer, the stressor layers and first polysilicon layer.In the present invention, the varying topography of side wall two sidewalls can be reduced, thus etching technics of the optimization to hard mask layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field more particularly to a kind of preparations of multiple graphical exposure mask
Method.
Background technique
Semiconductor technology is constantly strided forward towards smaller process node under the driving of Moore's Law.With semiconductor technology
Be constantly progressive, the function of device is gradually become strong, but semiconductors manufacture difficulty is also growing day by day.And photoetching technique is semiconductor
The most key production technology in manufacturing process, it is even lower as semiconductor technology node enters 65 nanometers, 45 nanometers
32 nanometers, the ArF light source photoetching technique of existing 193nm can no longer meet the needs of semiconductors manufacture, extreme ultraviolet light photoetching
Technology (EUV), multi-beam become the research hotspot of Next Generation Lithographies candidate technologies without mask technique and nanometer embossing.But
Above-mentioned Next Generation Lithographies candidate technologies have still had inconvenient and defect, it would be highly desirable to further be improved.
In order to improve the integrated level of semiconductor devices, industry has been presented for the preparation method of a variety of pattern masks, wherein
Self-alignment duplex pattern technique is as one such, still, the semiconductor figure two formed using the self-alignment duplex pattern
The pattern of the side wall of side can be different, will affect the performance of semiconductor devices.
Therefore, how side wall can be formed using multiple graphical mask layer, and the side wall two for reducing mask layer can be made
The difference of the side wall of side becomes a great problem that those skilled in the art face.
Summary of the invention
The purpose of the present invention is to provide the preparation method of multiple graphical exposure mask, side wall two sides in the prior art are solved
The technical issues of side wall has differences.
In order to solve the above technical problems, the present invention provides a kind of preparation method of multiple graphical exposure mask, comprising:
Semiconductor substrate is provided, forms hard mask layer on the semiconductor substrate；
The amorphous silicon layer stacked gradually and the first polysilicon layer are formed on the hard mask layer of part；
It is formed and is rolled around the amorphous silicon layer and first polysilicon layer；
Stressor layers are formed on the hard mask layer, the side wall and the amorphous silicon layer；
Thermal anneal process is carried out to the semiconductor substrate, the amorphous silicon layer is changed into the second polysilicon layer, and described
The width of second polysilicon layer is greater than the width of first polysilicon layer；
Remove second polysilicon layer, the stressor layers and first polysilicon layer.
Optionally, it forms first polysilicon layer and the step of amorphous silicon layer includes:
Polycrystalline silicon membrane is formed on the hard mask layer；
Ion implantation technology is carried out to the polycrystalline silicon membrane, so that the polycrystalline silicon membrane on surface forms the amorphous silicon
Layer, remaining polycrystalline silicon membrane form first polysilicon layer.
Optionally, germanium ion is carried out to the surface of the polycrystalline silicon membrane or arsenic ion injects.
Optionally, the concentration for carrying out ion implanting is 1012Atom number/cm3~1016Atom number/cm3。
Optionally, the thickness of the amorphous silicon layer is less than the thickness of first polysilicon layer.
Optionally, first polysilicon layer and described is formed on the hard mask layer using chemical vapor deposition process
Amorphous silicon layer.
Optionally, first polysilicon layer with a thickness of 50nm~100nm, second polysilicon layer with a thickness of
20nm~60nm.
Optionally, the width of second polysilicon layer is wider by 10%~50% than the width of first polysilicon layer.
Optionally, the material of the hard mask layer be amorphous carbon or boron nitride, the hard mask layer with a thickness of 20nm~
100nm。
Optionally, the material of the side wall be silica, the side wall with a thickness of 20nm~50nm.
Optionally, the stressor layers are compressive stress layer.
Optionally, the material of the stressor layers be silicon nitride, the stressor layers with a thickness of 20nm~100nm.
Compared with prior art, in the preparation method of multiple graphical exposure mask provided by the invention, the shape on hard mask layer
At the first polysilicon layer and amorphous silicon layer, graphical amorphous silicon layer and the first polysilicon layer, and in amorphous silicon layer and the first polycrystalline
Side wall is formed around silicon layer, forms stressor layers on amorphous silicon layer and side wall, and semiconductor substrate is carried out at thermal anneal process
Reason, amorphous silicon layer are changed into the second polysilicon layer, and the second polysilicon layer is due to thermal expansion so that its width is greater than the first polysilicon
Layer, the stress of the second polysilicon layer and compressive stress layer, so that the pattern of the side wall of side wall changes, to reduce side wall
The varying topography of two sidewalls optimizes the etching technics to hard mask layer.
Detailed description of the invention
Fig. 1 is the flow chart of multiple graphical exposure mask preparation method in one embodiment of the invention；
Fig. 2 is the structural schematic diagram that hard mask layer is formed in one embodiment of the invention；
Fig. 3 is the structural schematic diagram that polycrystalline silicon membrane is formed in one embodiment of the invention；
Fig. 4 is the structural schematic diagram that the first polysilicon layer and amorphous silicon layer are formed in one embodiment of the invention；
Fig. 5 is the structural schematic diagram of graphical first polysilicon layer and amorphous silicon layer in one embodiment of the invention；
Fig. 6 is the structural schematic diagram that side wall is formed in one embodiment of the invention；
Fig. 7 is the structural schematic diagram that stressor layers are formed in one embodiment of the invention；
Fig. 8 is the structural schematic diagram that the second polysilicon layer is formed in one embodiment of the invention；
Fig. 9 is the structural schematic diagram of the side wall optimized in one embodiment of the invention.
Specific embodiment
It is retouched in more detail below in conjunction with preparation method of the schematic diagram to multiple graphical masking process of the invention
It states, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify described herein hair
It is bright, and still realize advantageous effects of the invention.Therefore, following description should be understood as the wide of those skilled in the art
It is general to know, and it is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Core of the invention thought is, in the preparation method of the multiple graphical exposure mask provided, to semiconductor substrate into
The processing of row thermal anneal process, amorphous silicon layer are changed into the second polysilicon layer, and the second polysilicon layer is due to thermally expanding so that its width
Greater than the first polysilicon layer, the stress of the second polysilicon layer and compressive stress layer, so that the pattern of the side wall of side wall changes
Become, to reduce the varying topography of side wall two sidewalls, optimizes the etching technics to hard mask layer.
It is described in detail below in conjunction with preparation method of the attached drawing to multiple graphical exposure mask of the invention, Fig. 1 is multiple
The flow chart of pattern mask, Fig. 2~Fig. 9 is the corresponding structural schematic diagram of each step, specifically, the system of multiple graphical exposure mask
Preparation Method includes the following steps:
Firstly, executing step S1, refering to what is shown in Fig. 2, providing semiconductor substrate 100, the semiconductor substrate 100 can be
The substrat structures known in those skilled in the art such as silicon substrate, germanium silicon substrate, carbon silicon substrate, SOI substrate, with continued reference to Fig. 2
It is shown, hard mask layer 110 is formed on the surface of the semiconductor substrate 100, the hard mask layer 110 is used as subsequent etching processes
Mask layer.In the present embodiment, the material of the hard mask layer 110 is amorphous carbon or boron nitride, certainly, hard exposure mask in the present invention
The material of layer is not limited to this, and can also be the materials such as metal silication tungsten, and the hard mask layer 110 with a thickness of 20nm~
100nm, for example, with a thickness of 30nm, 50nm, 70nm, 90nm etc..
Then, step S2 is executed, forms the first polysilicon layer and amorphous silicon layer on the hard mask layer 110.This implementation
First polysilicon layer and the amorphous silicon layer are formed in example includes following sub-step:
Sub-step S21, refering to what is shown in Fig. 3, polycrystalline silicon membrane 120 is formed on the surface of the hard mask layer 110,
In, using chemical vapor deposition process (CVD) formed polycrystalline silicon membrane 120, the polycrystalline silicon membrane 120 with a thickness of 20nm~
200nm, for example, the polycrystalline silicon membrane 120 with a thickness of 50nm, 100nm, 150nm, 180nm etc..
Sub-step S22, refering to what is shown in Fig. 4, ion implantation technology is carried out to the polysilicon film 120, so that polysilicon film
The formation amorphous silicon layer 140 on 120 surface of layer, remaining polycrystalline silicon membrane 120 form first polysilicon layer 130.This
In embodiment, germanium ion (Ge) is carried out to the surface of the polycrystalline silicon membrane 120 or arsenic ion (As) injects, and carries out ion note
The concentration entered is 1012Atom number/cm3~1016Atom number/cm3, for example, the concentration of ion implanting is 1013Atom number/
cm3、1015Atom number/cm3.In addition, the thickness of the amorphous silicon layer 140 is less than first polysilicon layer in the present invention
130 thickness, for example, first polysilicon layer 130 with a thickness of 50nm~100nm, the thickness of second polysilicon layer 140
Degree is 20nm~60nm, the thickness of the second polysilicon layer of formation is controlled, to control amorphous silicon layer pair in subsequent anneal engineering
The stress of side wall optimizes the side wall of the side wall of formation.
Certainly, it will be apparent to a skilled person that being not limited to the method shape using ion implanting in the present invention
At the amorphous silicon layer, in other embodiments of the invention, can also be initially formed more than first using chemical vapor deposition process
Crystal silicon layer 130 then directly forms the amorphous silicon layer on first polysilicon layer 130 using chemical vapor deposition process
140, to directly form structure shown in Fig. 4.
Sub-step S23 (does not show refering to what is shown in Fig. 5, forming patterned photoresist on the amorphous silicon layer 140 in figure
Out), using patterned photoresist as exposure mask, the selective etching amorphous silicon layer 140, first polysilicon layer 130, thus
130 layers of graphical first polysilicon and amorphous silicon layer 140.
It should be understood that can also directly be formed graphically using other processing steps in the other embodiment of the present invention
The first polysilicon layer and amorphous silicon layer, for example, first forming patterned photoresist on hard mask layer, then directly pass through chemistry gas
Phase depositing operation forms patterned first polysilicon layer and amorphous silicon layer on hard mask layer, in this regard, the present invention not limits.
Later, step S3 is executed, with continued reference to shown in Fig. 5, using chemical vapor deposition process in the semiconductor substrate
100 and amorphous silicon layer 140 at side wall film layer 150 ', the material of the side wall film layer 150 ' is silica, silicon nitride or nitrogen oxygen
SiClx or combinations thereof, it is preferred that the present invention in use silica side wall film layer, and the side wall with a thickness of 20nm~
50nm.Then, refering to what is shown in Fig. 6, forming patterned photoresist in side wall film layer 150 ', using the patterned photoresist as exposure mask
The side wall film layer 150 ' is etched, side wall 150 is formed, side wall 150 surrounds first polysilicon layer 130 and amorphous silicon layer 140
Around.
Step S4 is executed, refering to what is shown in Fig. 7, forming stressor layers 160, the stressor layers in the semiconductor substrate 100
160 covering hard mask layers 110, side wall 150 and amorphous silicon layer 140.In the present embodiment, the stressor layers 160 of use are preferably pressed
Stressor layers, for example, the stressor layers of the material using silicon nitride, the stressor layers with a thickness of 20nm~100nm, for example, stress
Layer with a thickness of 30nm, 40nm, 60nm, 80nm etc..It should be appreciated that stressor layers 160 are to amorphous silicon layer and side in annealing process
Wall applies downward compression, so that stress is all applied on side wall, for adjusting the pattern of side wall side wall.
Then, step S5 is executed, thermal anneal process processing, 140 turns of the amorphous silicon layer are carried out to the amorphous silicon layer 140
Become the second polysilicon layer 170, also, thermally expanded after amorphous silicon layer 140 during thermal anneal process, so that second polycrystalline
The width of silicon layer 170 is greater than the width of first polysilicon layer 130.In the present embodiment, temperature that thermal anneal process uses for
800 DEG C~1000 DEG C, such as temperature is 850 DEG C, 900 DEG C, 950 DEG C etc., also, the width of the second polysilicon layer 170 formed
The range wider by 10%~50% than the width of the first polysilicon layer 130.Certainly, the edge of the second polysilicon layer is logical in the present invention
It is often formed as ramped shaped, the width of the second polysilicon layer 170 gradually increases.It should be noted that carrying out heat to semiconductor substrate
When annealing, amorphous silicon layer is changed into the second polysilicon layer, and the stress of thermal expansion enables to side wall 150 close to the second polycrystalline
The side wall of silicon layer forms slowly varying ramp shaped, adjusts the pattern of side wall side wall, thus reduce the varying topography of side wall two sidewalls,
With reference to shown in the side wall 150 in Fig. 8, and then optimize the etching technics to hard mask layer.
Step S6 is executed, refering to what is shown in Fig. 9, removing the stressor layers 160, second polysilicon layer more than 170 and first
Crystal silicon layer 130, to retain side wall 150.In the present embodiment, can be removed with using plasma etching technics the stressor layers,
Second polysilicon layer and the first polysilicon layer.Due to the influence of stress, so that the both walls varying topography of side wall reduces, thus with
When side wall is mask etching hard mask layer, the pattern of etching can be optimized.
In conclusion forming first on hard mask layer in the preparation method of multiple graphical exposure mask provided by the invention
Polysilicon layer and amorphous silicon layer, graphical amorphous silicon layer and the first polysilicon layer, and in amorphous silicon layer and the first polysilicon layer
Surrounding forms side wall and stressor layers, carries out thermal anneal process to semiconductor substrate, and amorphous silicon layer is changed into the second polysilicon layer, and
And reduce the varying topography of side wall two sidewalls, thus etching technics of the optimization to hard mask layer.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (11)
1. a kind of preparation method of multiple graphical exposure mask characterized by comprising
Semiconductor substrate is provided, forms hard mask layer on the semiconductor substrate；
Polycrystalline silicon membrane is formed on the hard mask layer；Ion implantation technology is carried out to the polycrystalline silicon membrane, so that surface
Polycrystalline silicon membrane form amorphous silicon layer, remaining polycrystalline silicon membrane forms the first polysilicon layer；
Patterned photoresist is formed on the amorphous silicon layer, using patterned photoresist as exposure mask, selective etching is described non-
Crystal silicon layer, first polysilicon layer, thus graphical first polysilicon layer and amorphous silicon layer；
Side wall is formed around the amorphous silicon layer and first polysilicon layer；
Stressor layers are formed on the hard mask layer, the side wall and the amorphous silicon layer；Heat is carried out to the semiconductor substrate
Annealing process, the amorphous silicon layer is changed into the second polysilicon layer, and the width of second polysilicon layer is greater than described first
The width of polysilicon layer；
Remove second polysilicon layer, the stressor layers and first polysilicon layer.
2. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that the polycrystalline silicon membrane
Surface carries out germanium ion or arsenic ion injection.
3. the preparation method of multiple graphical exposure mask as claimed in claim 2, which is characterized in that carry out the concentration of ion implanting
It is 1012Atom number/cm3~1016Atom number/cm3。
4. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that the thickness of the amorphous silicon layer
Less than the thickness of first polysilicon layer.
5. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that use chemical vapor deposition work
Skill forms first polysilicon layer and the amorphous silicon layer on the hard mask layer.
6. the preparation method of multiple graphical exposure mask as described in claim 4 or 5, which is characterized in that first polysilicon
Layer with a thickness of 50nm~100nm, second polysilicon layer with a thickness of 20nm~60nm.
7. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that second polysilicon layer
Width is wider by 10%~50% than the width of first polysilicon layer.
8. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that the material of the hard mask layer
For amorphous carbon or boron nitride, the hard mask layer with a thickness of 20nm~100nm.
9. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that the material of the side wall is oxygen
SiClx, the side wall with a thickness of 20nm~50nm.
10. the preparation method of multiple graphical exposure mask as described in claim 1, which is characterized in that the stressor layers are that pressure is answered
Power layer.
11. the preparation method of multiple graphical exposure mask as claimed in claim 10, which is characterized in that the material of the stressor layers
For silicon nitride, the stressor layers with a thickness of 20nm~100nm.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239040B1 (en) * | 1998-06-23 | 2001-05-29 | United Microelectronics Corp. | Method of coating amorphous silicon film |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| CN102983104A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of complementary metal oxide semiconductor (CMOS) transistors |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239040B1 (en) * | 1998-06-23 | 2001-05-29 | United Microelectronics Corp. | Method of coating amorphous silicon film |
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure |
| CN102983104A (en) * | 2011-09-07 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of complementary metal oxide semiconductor (CMOS) transistors |
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