CN106158585B - Surface treatment method of wafer, semiconductor device and manufacturing method thereof - Google Patents
Surface treatment method of wafer, semiconductor device and manufacturing method thereof Download PDFInfo
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Abstract
The application provides a surface treatment method of a wafer, a semiconductor device and a manufacturing method thereof. Wherein, the surface treatment method comprises the following steps: placing a wafer in a reaction chamber with a reaction gas; reacting the reaction gas with the oxide on the surface of the wafer to form a reaction product; and carrying out annealing treatment at least twice on the wafer to decompose and remove reaction products. According to the surface treatment method, the wafer is subjected to multiple annealing treatments, so that the reaction product generated in the surface treatment process can be decomposed for multiple times, the reaction product is decomposed by each annealing treatment so as to continuously reduce the thickness of the reaction product, the decomposition difficulty of the reaction product caused by the excessively thick thickness of the reaction product is reduced, the reaction product on the surface of the wafer is further easily decomposed, and residues of the reaction product generated on the surface of the wafer in the surface treatment process are reduced.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a surface treatment method for a wafer, a semiconductor device, and a manufacturing method thereof.
Background
In the conventional integrated circuit process, a pre-cleaning process is usually required to perform a surface treatment on a wafer having transistors to remove impurities on the surface of the wafer, and then a subsequent device is fabricated on the wafer. The variety of pre-cleaning processes is very wide, and some pre-cleaning processes react with impurities on the surface of the wafer through a reaction gas to form a reaction product, and then remove the impurities on the surface of the wafer through removing the reaction product.
For example, in the existing self-aligned process, nickel metal is deposited to form metal silicide, and a SiCoNi pre-cleaning process is usually used to perform surface treatment on the substrate before forming nickel metal. The SiCoNi precleaning process is a low-strength chemical etching method, and comprises the following two steps: first, using NF
3And NH
3Formation of NH as a reaction gas as a precursor gas
4F and NH
4F.HF, then, the formed reaction gas is utilized to react with SiO impurity on the surface of the substrate
2Reacting to form a reaction product; finally, the reaction product is decomposed by annealing treatment (the annealing temperature is generally higher than 100 ℃), so that the effect of removing impurities on the surface of the wafer is achieved.
However, the reaction product generated in the conventional precleaning process (i.e., the surface treatment process) is a solid substance that is not easily decomposed, so that the reaction product is difficult to be completely decomposed after the annealing treatment process, thereby forming a residue of the reaction product on the surface of the wafer. And residues on the wafer surface can affect the performance of the finally formed semiconductor device, and can lead to device failure in severe cases.
Disclosure of Invention
The present disclosure is directed to a method for processing a surface of a wafer, a semiconductor device and a method for fabricating the same, so as to reduce residues of reaction products generated on the surface of the wafer during a surface processing process.
In order to achieve the above object, according to one aspect of the present application, there is provided a surface treatment method of a wafer, the surface treatment method including the steps of: placing a wafer in a reaction chamber with a reaction gas; reacting the reaction gas with the oxide on the surface of the wafer to form a reaction product; and carrying out annealing treatment at least twice on the wafer to decompose and remove reaction products.
Further, the annealing temperatures of the respective annealing treatments are different.
Further, the annealing temperature of each annealing treatment is increased in turn with the increase of the times.
Furthermore, the annealing time of each annealing treatment is 1-10 min, and the annealing time interval of each annealing treatment is 10-60 s.
Further, the annealing temperature of each annealing treatment is in the range of 110 ℃ to 160 ℃.
Further, in the annealing treatment step, H is further introduced into the reaction chamber
2。
Further, H
2The gas flow rate of the gas is 200sccm to 1000 sccm.
Further, annealing the wafer twice, wherein the annealing temperature of the first annealing is 110-130 ℃, and the annealing temperature of the second annealing is 140-160 ℃.
Further, the wafer also comprises a step of forming a transistor on the wafer before the surface treatment.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of manufacturing a semiconductor device, the method comprising the steps of: carrying out surface treatment on the wafer or the wafer provided with the transistor by using the surface treatment method; and arranging a semiconductor device structure on the surface-treated wafer to form a semiconductor device.
Further, when the surface treatment method is surface treatment of a wafer provided with a transistor, the semiconductor device structure is a metal silicide electrically connected to the transistor.
Further, the step of forming the metal silicide includes: depositing a metal layer on the surface-treated wafer; and performing heat treatment to enable the metal layer to react with the wafer to form metal silicide.
Further, the metal layer is a NiPt layer, and the step of forming the metal silicide comprises the following steps: carrying out first heat treatment to enable part of the metal layer to react with the wafer to form a Ni2Si layer; removing the residual metal layer by wet etching; and performing a second heat treatment to transform the Ni2Si layer into a NiSi layer, the NiSi layer constituting a metal silicide.
Furthermore, after the metal silicide is formed, the manufacturing method further comprises the step of forming a mask layer on the metal silicide.
Further, in the step of forming a metal silicide, a metal silicide electrically connected to the source-drain of the transistor and/or the gate of the transistor is formed.
According to another aspect of the present application, a semiconductor device is provided, which is made by the above-mentioned manufacturing method.
By applying the technical scheme, the surface treatment method of the wafer provided by the application carries out annealing treatment on the wafer for multiple times, so that the reaction product generated in the surface treatment process can be decomposed for multiple times, the reaction product can be decomposed by annealing treatment at each time so as to continuously reduce the thickness of the reaction product, the decomposition difficulty of the reaction product caused by the over-thick thickness of the reaction product is also reduced, the reaction product on the surface of the wafer is further easily decomposed, and the residues of the reaction product generated on the surface of the wafer in the surface treatment process are reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 is a schematic flow chart illustrating a method for processing a surface of a wafer according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As described in the background art, the reaction product generated in the prior precleaning process (i.e., the surface treatment process) is a solid substance that is not easily decomposed, so that the reaction product is not easily decomposed completely after the annealing treatment process, thereby forming a residue of the reaction product on the surface of the wafer. The inventors of the present application have studied the above-described problems and have proposed a method for surface treatment of a wafer. As shown in fig. 1, the processing method includes the steps of: placing a wafer in a reaction chamber with a reaction gas; reacting the reaction gas with the oxide on the surface of the wafer to form a reaction product; and carrying out annealing treatment on the wafer for at least two times to remove reaction products.
According to the surface treatment method, the wafer is subjected to multiple annealing treatments, so that the reaction product generated in the surface treatment process can be decomposed for multiple times, the reaction product is decomposed by each annealing treatment so as to continuously reduce the thickness of the reaction product, the decomposition difficulty of the reaction product caused by the excessively thick thickness of the reaction product is reduced, the reaction product on the surface of the wafer is further easily decomposed, and the residues of the reaction product generated on the surface of the wafer in the surface treatment process are reduced.
Exemplary embodiments of a surface treatment method of a wafer provided according to the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a wafer is placed in a reaction chamber having a reaction gas. Wherein the reaction gas may be generated by a precursor gas. The techniques of the artThe person may select a suitable precursor gas according to the actual process requirements, and in a preferred embodiment, in the step of introducing the precursor gas into the reaction chamber, the precursor gas is NF
3And NH
3And the precursor gas generates reaction gas NH under the action of radio frequency power
4F and NH
4F. HF. The reaction gas can well react with the impurities on the surface of the wafer, and the impurities on the surface of the wafer can be removed through the subsequent annealing treatment.
After the step of placing the wafer in the reaction chamber with the reaction gas is completed, the reaction gas reacts with the oxide on the surface of the wafer to form a reaction product. The reaction product varies according to the reaction gas generated and the impurities on the surface of the wafer, and in a preferred embodiment, the reaction gas is NH
4F and NH
4F.HF, and NH
4F and NH
4F.HF condensed on the wafer surface and SiO as an impurity
2Reaction is carried out, and solid (NH) can be generated at normal temperature
4)
2SiF
6As a reaction product.
And after the step of forming reaction products by the reaction of the reaction gas and the oxides on the surface of the wafer is completed, carrying out annealing treatment on the wafer for multiple times to decompose and remove the reaction products. Because the annealing treatment is carried out for a plurality of times, the residues generated in the surface treatment process can be decomposed for a plurality of times, and the annealing treatment can decompose the residues every time so as to continuously reduce the thickness of the residues, and simultaneously, the decomposition difficulty of the residues caused by the over-thick thickness of the residues is also reduced, so that the residues on the surface of the wafer are more easily decomposed, and the residues generated on the surface of the wafer in the surface treatment process are reduced.
In a preferred embodiment, the wafer is annealed a plurality of times, with different annealing temperatures for each annealing. More preferably, the annealing temperature of each annealing treatment is increased in sequence with the increase of the times. The sequential increase of the annealing temperature enables the reaction product to be continuously thinned in multiple annealing treatments, thereby being beneficial to the decomposition reaction of the reaction product.
The annealing temperature and the annealing time of each annealing treatment can be set according to the prior art. Preferably, the annealing temperature of each annealing treatment is in the range of 110 ℃ to 160 ℃. Wherein, the oxide as the impurity on the surface of the wafer forms a reaction product by reacting with the reaction gas, the reaction product can be better decomposed under the high temperature treatment with the annealing temperature of 110 ℃ to 160 ℃, and the higher the temperature is, the more beneficial to remove the reaction product. Meanwhile, the annealing time of each annealing treatment is preferably 1-10 min, and the annealing time interval of each annealing treatment is preferably 10-60 s.
The number of annealing treatments can be set by one skilled in the art according to the teachings of the present application, and in a preferred embodiment, the wafer is annealed twice, and the annealing temperature of the first annealing treatment is 110-130 ℃ and the annealing temperature of the second annealing treatment is 140-160 ℃. The specific process comprises the following steps: firstly, the reaction gas is NH
4F and NH
4F, HF, performing a first annealing treatment at an annealing temperature of 110-130 ℃, wherein NH which does not react with impurities on the surface of the wafer
4F and NH
4F.HF, and reaction product (NH)
4)
2SiF
6Is removed from the wafer surface by sublimation under heat, but still has a portion (NH)
4)
2SiF
6The wafer is not decomposed and is not remained on the surface of the wafer because of being subjected to the annealing treatment; then, a second annealing treatment is carried out at a higher annealing temperature of 140-160 ℃, and the thickness of the reaction product after the previous annealing treatment is reduced, so that the residual reaction product (NH) can be further removed
4)
2SiF
6。
In the preferred embodiment, further, in the annealing step, H may be further introduced into the reaction chamber
2. In the process of multiple annealing treatment to decompose reaction products, H is introduced
2Can facilitate the decomposition of the reaction product. Those skilled in the art can select a suitable gas flow rate, preferably H, according to the actual process requirements
2The gas flow rate of the gas is 200sccm to 1000 sccm. The above preferred process parameters can further promote the decomposition of the reaction gas and the reaction product to form residues on the wafer surfaceIs more broken down.
In a preferred embodiment, the wafer further comprises a step of forming a transistor on the wafer before the surface treatment. After the transistor is formed on the surface of the wafer, the surface of the wafer is processed, so that reaction products generated on the surface of the wafer in the process of forming the transistor can be reduced, and the performance of a subsequently formed semiconductor device can be improved.
The present application further provides a method for manufacturing a semiconductor device, as shown in fig. 2, the method includes the following steps: carrying out surface treatment on the wafer or the wafer provided with the transistor by using the surface treatment method; and arranging a semiconductor device structure on the surface-treated wafer to form a semiconductor device.
According to the manufacturing method of the semiconductor device, the wafer is subjected to multiple annealing treatments, so that the reaction product generated in the surface treatment process can be decomposed for multiple times, the reaction product is decomposed by each annealing treatment so as to continuously reduce the thickness of the reaction product, the decomposition difficulty of the reaction product caused by the excessively thick thickness of the reaction product is reduced, the reaction product on the surface of the wafer is further easily decomposed, the influence of the residue of the reaction product generated in the surface treatment process on the performance of the semiconductor device is reduced, and the semiconductor device has higher device stability and yield.
Exemplary embodiments of methods of fabricating semiconductor devices provided in accordance with the present application will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
First, a wafer or a wafer provided with a transistor is subjected to surface treatment by the above-described surface treatment method. The step of surface treatment comprises the step of annealing the wafer for a plurality of times, so that residues generated in the surface treatment process can be decomposed for a plurality of times, the residues are decomposed by annealing treatment each time, the thickness of the residues is reduced continuously, the difficulty of decomposition of the residues caused by the excessively thick thickness of the residues is reduced, the residues on the surface of the wafer are decomposed more easily, and the residues generated on the surface of the wafer in the surface treatment process are reduced.
After the step of surface processing the wafer by using the surface processing method is completed, a semiconductor device structure is arranged on the surface-processed wafer to form a semiconductor device. Preferably, when the surface treatment method is surface treatment of a wafer provided with a transistor, the semiconductor device structure is a metal silicide electrically connected to the transistor. There are many ways to form the metal silicide, and in a preferred embodiment, the step of forming the metal silicide comprises: depositing a metal layer on the surface-treated wafer; and performing heat treatment to enable the metal layer to react with the wafer to form metal silicide. The metal silicide can reduce the source-drain contact resistance and the parasitic series resistance, thereby improving the performance of the semiconductor device.
In a preferred embodiment, the transistor is a source and a drain, and in the step of forming the metal silicide, the metal silicide is formed to be electrically connected to the source and drain of the transistor and/or the gate of the transistor. Because the surface of the wafer after surface treatment has less impurities and reaction products, the formation of the metal silicide can effectively reduce the source-drain contact resistance and the parasitic series resistance and further improve the performance of the semiconductor device.
In the above preferred embodiment, it is more preferred that the metal layer is a NiPt layer, and the step of forming a metal silicide includes: performing a first heat treatment to react part of the metal layer with the wafer to form Ni
2A Si layer; removing the residual metal layer by wet etching; and performing a second heat treatment to make Ni
2The Si layer is converted to a NiSi layer, and the NiSi layer constitutes a metal silicide. In the process steps, a small amount of Pt is doped into Ni, and two-step annealing treatment is carried out, so that an NiSi layer with high-temperature stability is obtained; and, of a NiSi layerThe formation process consumes less silicon in the source/drain, and the silicon near the surface is just the region with the highest doping concentration, which is very beneficial to reduce the overall contact resistance.
It is to be noted that the step of forming the metal silicide is not limited to the above preferred embodiment. For example, the step of forming the metal silicide may further include: depositing a metal layer on the surface-treated wafer; performing heat treatment to enable the metal layer to react with the wafer to form metal silicide; and forming a mask layer on the metal silicide. The mask layer can be made of dielectric materials commonly used in the art. Preferably, the material of the mask layer is TiN, the process for forming the mask layer may be chemical vapor deposition, and the like, and those skilled in the art may select an appropriate process and parameters thereof according to actual process requirements.
The present application further provides a semiconductor device. The semiconductor device comprises a wafer formed with a transistor and a metal silicide electrically connected with the transistor, and is manufactured by the manufacturing method. The manufacturing method comprises the step of annealing the wafer for multiple times, so that the reaction product generated in the surface treatment process can be decomposed for multiple times, the reaction product is decomposed by each annealing treatment so as to continuously reduce the thickness of the reaction product, the decomposition difficulty of the reaction product caused by the excessively thick thickness of the reaction product is reduced, the reaction product on the surface of the wafer is easier to decompose, and the residues of the reaction product generated on the surface of the wafer in the surface treatment process are reduced. Therefore, the semiconductor device formed by the wafer has higher device stability and yield.
The method for processing the surface of the wafer provided by the present application will be further described with reference to the following examples.
Example 1
The step of surface treatment of the wafer provided by the embodiment includes:
firstly, a wafer is placed in a reaction chamber; then, NF was introduced into the reaction chamber
3And NH
3As a precursor gas to generate NH
4F and NH
4F, HF as reaction gasA body; next, the reaction gas is used to react with SiO on the wafer surface
2Reacting the impurities to form a reaction product; and finally, carrying out two times of annealing treatment on the wafer to decompose and remove reaction products, wherein the temperature of the two times of annealing treatment is 140 ℃, and the annealing time is 1 min.
Example 2
The step of surface treatment of the wafer provided by the embodiment includes:
firstly, a wafer is placed in a reaction chamber; then, NF was introduced into the reaction chamber
3And NH
3As a precursor gas to generate NH
4F and NH
4F, HF is used as reaction gas; next, the reaction gas is used to react with SiO on the wafer surface
2Reacting the impurities to form a reaction product; and finally, carrying out annealing treatment on the wafer twice to decompose and remove reaction products, wherein the annealing treatment temperatures of the first annealing position and the second annealing treatment are 110 ℃ and 160 ℃ in sequence, and the annealing time is 5 min.
Example 3
The step of surface treatment of the wafer provided by the embodiment includes:
firstly, a wafer is placed in a reaction chamber; then, NF was introduced into the reaction chamber
3And NH
3As a precursor gas to generate NH
4F and NH
4F, HF is used as reaction gas; next, the reaction gas is used to react with SiO on the wafer surface
2Reacting the impurities to form a reaction product; and finally, carrying out three times of annealing treatment on the wafer to decompose and remove reaction products, wherein the temperatures of the first annealing treatment, the second annealing treatment and the third annealing treatment are 110 ℃, 130 ℃ and 150 ℃ in sequence, and the annealing time is 10 min.
Comparative example 1
The step of surface treatment of the wafer provided by the comparative example comprises:
firstly, a wafer is placed in a reaction chamber; then, NF was introduced into the reaction chamber
3And NH
3As a precursor gas to generate NH
4F and NH
4F, HF is used as reaction gas; next, using the reaction gas and the wafer surfaceSiO on
2Reacting the impurities to form a reaction product; and finally, carrying out primary annealing treatment on the wafer to decompose and remove reaction products, wherein the annealing treatment temperature is 140 ℃, and the annealing time is 5 min.
The shapes of the wafers of examples 1 to 3 and comparative example 1 before and after surface treatment were observed by a scanning electron microscope, and the removal rates of the residues before and after surface treatment were calculated, and the results are shown in table 1. As can be seen from table 1, the removal rate of the residue before and after the surface treatment of the wafers in examples 1 to 3 was 88% to 93%, while the removal rate of the residue before and after the surface treatment of the wafer in comparative example 1 was only 67%. Therefore, the surface treatment method provided by the invention can reduce residues generated on the surface of the wafer in the surface treatment process.
TABLE 1
| Removal rate of residue | |
| Example 1 | 92％ |
| Example 2 | 93％ |
| Example 3 | 88％ |
| Comparative example 1 | 67％ |
Semiconductor device structures were provided on the wafers surface-treated in the above-described examples 1 to 3 and comparative example 1, respectively, to form semiconductor devices. Since the surface-treated wafers in examples 1 to 3 have less residue on the surface and the less residue affects the performance of the formed semiconductor devices, the semiconductor devices formed by using the surface-treated wafers in examples 1 to 3 have higher device stability and yield.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects: according to the surface treatment method of the wafer, multiple times of annealing treatment are carried out on the wafer, so that reaction products generated in the surface treatment process can be decomposed for multiple times, the reaction products are decomposed by annealing treatment every time, the thickness of the reaction products is reduced continuously, the decomposition difficulty of the reaction products caused by the fact that the thickness of the reaction products is too thick is reduced, the reaction products on the surface of the wafer are decomposed more easily, and residues of the reaction products generated on the surface of the wafer in the surface treatment process are reduced.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (11)
1. A method for manufacturing a semiconductor device, the method comprising:
carrying out surface treatment on the wafer or the wafer provided with the transistor by using a surface treatment method; and
disposing a semiconductor device structure on the surface-treated wafer to form a semiconductor device,
the surface treatment method comprises the following steps:
placing the wafer in a reaction chamber having a reaction gas;
the reaction gas reacts with the oxide on the surface of the wafer to form a reaction product; and
carrying out annealing treatment on the wafer for at least two times to decompose and remove the reaction product,
in the step of annealing treatment, H is further introduced into the reaction chamber
2，
When the surface treatment method is surface treatment of a wafer provided with a transistor, the semiconductor device structure is a metal silicide electrically connected with the transistor, and the step of forming the metal silicide comprises the following steps:
depositing a metal layer on the surface-treated wafer;
performing a heat treatment to react the metal layer and the wafer to form the metal silicide,
the metal layer is a NiPt layer, and the step of forming the metal silicide comprises the following steps:
performing a first heat treatment to react a portion of the metal layer with the wafer to form Ni
2A Si layer;
removing the residual metal layer by wet etching; and
performing a second heat treatment to make Ni
2The Si layer is converted to a NiSi layer, and the NiSi layer constitutes the metal silicide.
2. The method of claim 1, wherein the annealing temperature is different for each annealing treatment.
3. The method according to claim 1, wherein the annealing temperature of each annealing treatment is increased in order as the number of times increases.
4. The method of claim 1, wherein the annealing time for each annealing treatment is 1-10 min, and the annealing time interval for each annealing treatment is 10-60 s.
5. The method of claim 2, wherein the annealing temperature of each annealing treatment is in a range of 110 ℃ to 160 ℃.
6. The method of claim 1, wherein the H is
2The gas flow rate of the gas is 200sccm to 1000 sccm.
7. The method according to claim 4, wherein the annealing is performed twice on the wafer, and the annealing temperature in the first annealing is 110 to 130 ℃ and the annealing temperature in the second annealing is 140 to 160 ℃.
8. The method of claim 1, wherein the wafer further comprises a step of forming a transistor on the wafer before the surface treatment.
9. The method of claim 1, wherein after forming the metal silicide, the method further comprises forming a mask layer over the metal silicide.
10. The manufacturing method according to claim 1 or 9, wherein in the step of forming the metal silicide, the metal silicide electrically connected to a source/drain of the transistor and/or a gate of the transistor is formed.
11. A semiconductor device manufactured by the manufacturing method of any one of claims 1 to 10.
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| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
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| US8163607B2 (en) * | 2010-04-29 | 2012-04-24 | United Microelectronics Corp. | Semiconductor device and method of making the same |
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| CN103137462A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Method for forming self-aligned metal silicide |
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